Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1126018581	11013	0	0
auto_block_debounce_ctl_rd_A	1126018581	1864	0	0
auto_block_out_ctl_rd_A	1126018581	2604	0	0
com_det_ctl_0_rd_A	1126018581	4309	0	0
com_det_ctl_1_rd_A	1126018581	4330	0	0
com_det_ctl_2_rd_A	1126018581	4145	0	0
com_det_ctl_3_rd_A	1126018581	4234	0	0
com_out_ctl_0_rd_A	1126018581	4892	0	0
com_out_ctl_1_rd_A	1126018581	4609	0	0
com_out_ctl_2_rd_A	1126018581	4820	0	0
com_out_ctl_3_rd_A	1126018581	4826	0	0
com_pre_det_ctl_0_rd_A	1126018581	1469	0	0
com_pre_det_ctl_1_rd_A	1126018581	1659	0	0
com_pre_det_ctl_2_rd_A	1126018581	1542	0	0
com_pre_det_ctl_3_rd_A	1126018581	1539	0	0
com_pre_sel_ctl_0_rd_A	1126018581	4867	0	0
com_pre_sel_ctl_1_rd_A	1126018581	4951	0	0
com_pre_sel_ctl_2_rd_A	1126018581	4913	0	0
com_pre_sel_ctl_3_rd_A	1126018581	5077	0	0
com_sel_ctl_0_rd_A	1126018581	5071	0	0
com_sel_ctl_1_rd_A	1126018581	5186	0	0
com_sel_ctl_2_rd_A	1126018581	4782	0	0
com_sel_ctl_3_rd_A	1126018581	4953	0	0
ec_rst_ctl_rd_A	1126018581	2868	0	0
intr_enable_rd_A	1126018581	2272	0	0
key_intr_ctl_rd_A	1126018581	3075	0	0
key_intr_debounce_ctl_rd_A	1126018581	1547	0	0
key_invert_ctl_rd_A	1126018581	4869	0	0
pin_allowed_ctl_rd_A	1126018581	5888	0	0
pin_out_ctl_rd_A	1126018581	4677	0	0
pin_out_value_rd_A	1126018581	4903	0	0
regwen_rd_A	1126018581	1778	0	0
ulp_ac_debounce_ctl_rd_A	1126018581	1617	0	0
ulp_ctl_rd_A	1126018581	1788	0	0
ulp_lid_debounce_ctl_rd_A	1126018581	1614	0	0
ulp_pwrb_debounce_ctl_rd_A	1126018581	1697	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	11013	0	0
T2	933435	10	0	0
T3	529406	6	0	0
T6	152855	0	0	0
T10	0	22	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T25	109767	0	0	0
T34	0	35	0	0
T43	410749	11	0	0
T45	0	14	0	0
T51	238278	0	0	0
T58	0	3	0	0
T59	0	12	0	0
T60	0	5	0	0
T61	60619	0	0	0
T102	0	15	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1864	0	0
T2	933435	0	0	0
T3	529406	40	0	0
T14	340124	22	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T40	0	21	0	0
T43	410749	0	0	0
T45	0	20	0	0
T47	0	18	0	0
T58	0	23	0	0
T59	0	42	0	0
T60	0	4	0	0
T108	0	4	0	0
T293	0	14	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	2604	0	0
T2	933435	0	0	0
T3	529406	23	0	0
T14	340124	4	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T40	0	25	0	0
T43	410749	0	0	0
T45	0	30	0	0
T47	0	4	0	0
T58	0	9	0	0
T59	0	39	0	0
T60	0	22	0	0
T108	0	6	0	0
T293	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4309	0	0
T1	160947	53	0	0
T2	933435	0	0	0
T3	0	28	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	42	0	0
T42	0	15	0	0
T45	0	44	0	0
T58	0	12	0	0
T59	0	35	0	0
T65	0	56	0	0
T71	0	66	0	0
T107	0	55	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4330	0	0
T1	160947	75	0	0
T2	933435	0	0	0
T3	0	13	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	49	0	0
T42	0	36	0	0
T45	0	39	0	0
T58	0	12	0	0
T59	0	37	0	0
T65	0	67	0	0
T71	0	41	0	0
T107	0	46	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4145	0	0
T1	160947	59	0	0
T2	933435	0	0	0
T3	0	11	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	57	0	0
T42	0	20	0	0
T45	0	26	0	0
T58	0	15	0	0
T59	0	31	0	0
T65	0	45	0	0
T71	0	30	0	0
T107	0	35	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4234	0	0
T1	160947	81	0	0
T2	933435	0	0	0
T3	0	21	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	49	0	0
T42	0	25	0	0
T45	0	29	0	0
T58	0	19	0	0
T59	0	35	0	0
T65	0	61	0	0
T71	0	25	0	0
T107	0	25	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4892	0	0
T1	160947	70	0	0
T2	933435	0	0	0
T3	0	14	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	47	0	0
T42	0	41	0	0
T45	0	24	0	0
T58	0	8	0	0
T59	0	27	0	0
T65	0	69	0	0
T71	0	62	0	0
T107	0	32	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4609	0	0
T1	160947	82	0	0
T2	933435	0	0	0
T3	0	10	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	57	0	0
T42	0	32	0	0
T45	0	26	0	0
T58	0	4	0	0
T59	0	33	0	0
T65	0	64	0	0
T71	0	47	0	0
T107	0	60	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4820	0	0
T1	160947	53	0	0
T2	933435	0	0	0
T3	0	10	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	51	0	0
T42	0	43	0	0
T45	0	44	0	0
T58	0	17	0	0
T59	0	51	0	0
T65	0	59	0	0
T71	0	59	0	0
T107	0	43	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4826	0	0
T1	160947	66	0	0
T2	933435	0	0	0
T3	0	16	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	41	0	0
T42	0	39	0	0
T45	0	29	0	0
T58	0	25	0	0
T59	0	36	0	0
T65	0	70	0	0
T71	0	40	0	0
T107	0	34	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1469	0	0
T3	529406	30	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	27	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	15	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	11	0	0
T59	0	37	0	0
T60	0	20	0	0
T61	60619	0	0	0
T88	0	6	0	0
T113	0	12	0	0
T206	0	37	0	0
T294	0	13	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1659	0	0
T3	529406	18	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	21	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	32	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	18	0	0
T59	0	25	0	0
T60	0	17	0	0
T61	60619	0	0	0
T88	0	3	0	0
T113	0	9	0	0
T206	0	32	0	0
T294	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1542	0	0
T3	529406	15	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	16	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	32	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	24	0	0
T59	0	33	0	0
T60	0	11	0	0
T61	60619	0	0	0
T88	0	10	0	0
T206	0	29	0	0
T294	0	6	0	0
T295	0	8	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1539	0	0
T3	529406	12	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	11	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	28	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	14	0	0
T59	0	48	0	0
T60	0	11	0	0
T61	60619	0	0	0
T113	0	11	0	0
T206	0	31	0	0
T294	0	10	0	0
T295	0	5	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4867	0	0
T1	160947	68	0	0
T2	933435	0	0	0
T3	0	19	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	58	0	0
T42	0	41	0	0
T45	0	36	0	0
T58	0	9	0	0
T59	0	27	0	0
T65	0	63	0	0
T71	0	36	0	0
T107	0	35	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4951	0	0
T1	160947	67	0	0
T2	933435	0	0	0
T3	0	15	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	55	0	0
T42	0	33	0	0
T45	0	51	0	0
T58	0	11	0	0
T59	0	51	0	0
T65	0	56	0	0
T71	0	32	0	0
T107	0	34	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4913	0	0
T1	160947	65	0	0
T2	933435	0	0	0
T3	0	8	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	42	0	0
T42	0	57	0	0
T45	0	33	0	0
T58	0	19	0	0
T59	0	34	0	0
T65	0	71	0	0
T71	0	47	0	0
T107	0	34	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	5077	0	0
T1	160947	61	0	0
T2	933435	0	0	0
T3	0	18	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	46	0	0
T42	0	45	0	0
T45	0	30	0	0
T58	0	28	0	0
T59	0	23	0	0
T65	0	82	0	0
T71	0	41	0	0
T107	0	55	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	5071	0	0
T1	160947	64	0	0
T2	933435	0	0	0
T3	0	11	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	50	0	0
T42	0	30	0	0
T45	0	35	0	0
T58	0	21	0	0
T59	0	44	0	0
T65	0	83	0	0
T71	0	46	0	0
T107	0	37	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	5186	0	0
T1	160947	50	0	0
T2	933435	0	0	0
T3	0	19	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	58	0	0
T42	0	25	0	0
T45	0	39	0	0
T58	0	11	0	0
T59	0	33	0	0
T65	0	50	0	0
T71	0	47	0	0
T107	0	39	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4782	0	0
T1	160947	53	0	0
T2	933435	0	0	0
T3	0	13	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	51	0	0
T42	0	37	0	0
T45	0	22	0	0
T58	0	15	0	0
T59	0	39	0	0
T65	0	67	0	0
T71	0	47	0	0
T107	0	49	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4953	0	0
T1	160947	60	0	0
T2	933435	0	0	0
T3	0	18	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	61	0	0
T42	0	40	0	0
T45	0	34	0	0
T58	0	10	0	0
T59	0	40	0	0
T65	0	62	0	0
T71	0	48	0	0
T107	0	40	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	2868	0	0
T1	160947	57	0	0
T2	933435	0	0	0
T3	0	10	0	0
T13	204787	0	0	0
T14	340124	0	0	0
T15	97358	0	0	0
T16	236721	0	0	0
T17	62035	0	0	0
T18	98134	0	0	0
T19	61811	0	0	0
T20	154132	0	0	0
T26	0	10	0	0
T42	0	6	0	0
T45	0	47	0	0
T58	0	16	0	0
T59	0	40	0	0
T65	0	1	0	0
T107	0	40	0	0
T214	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	2272	0	0
T3	529406	51	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T36	0	17	0	0
T40	0	23	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	61	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	28	0	0
T59	0	54	0	0
T60	0	40	0	0
T61	60619	0	0	0
T88	0	8	0	0
T108	0	4	0	0
T296	0	9	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	3075	0	0
T3	529406	20	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T36	0	7	0	0
T40	0	26	0	0
T41	0	2	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	37	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	16	0	0
T59	0	35	0	0
T60	0	14	0	0
T61	60619	0	0	0
T88	0	1	0	0
T136	0	1	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1547	0	0
T3	529406	7	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	22	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	42	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	8	0	0
T59	0	24	0	0
T61	60619	0	0	0
T88	0	1	0	0
T206	0	23	0	0
T259	0	1	0	0
T260	0	18	0	0
T294	0	16	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4869	0	0
T3	529406	61	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	17	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	73	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	15	0	0
T59	0	37	0	0
T60	0	1	0	0
T61	60619	0	0	0
T62	0	73	0	0
T130	0	60	0	0
T250	0	31	0	0
T297	0	68	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	5888	0	0
T3	529406	27	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	22	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	42	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	19	0	0
T59	0	41	0	0
T60	0	7	0	0
T61	60619	0	0	0
T88	0	155	0	0
T130	0	70	0	0
T132	0	86	0	0
T251	0	57	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4677	0	0
T3	529406	25	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	14	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	31	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	17	0	0
T59	0	29	0	0
T60	0	6	0	0
T61	60619	0	0	0
T88	0	134	0	0
T130	0	71	0	0
T132	0	74	0	0
T251	0	80	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	4903	0	0
T3	529406	10	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	26	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	40	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	28	0	0
T59	0	48	0	0
T60	0	13	0	0
T61	60619	0	0	0
T88	0	171	0	0
T130	0	76	0	0
T132	0	90	0	0
T251	0	62	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1778	0	0
T3	529406	28	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	10	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	33	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T58	0	14	0	0
T59	0	35	0	0
T60	0	3	0	0
T61	60619	0	0	0
T113	0	9	0	0
T206	0	27	0	0
T294	0	13	0	0
T295	0	15	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1617	0	0
T3	529406	11	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	26	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	12	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T57	0	4	0	0
T58	0	22	0	0
T59	0	30	0	0
T60	0	18	0	0
T61	60619	0	0	0
T69	0	9	0	0
T108	0	13	0	0
T298	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1788	0	0
T3	529406	20	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	48	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	35	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T57	0	3	0	0
T58	0	21	0	0
T59	0	42	0	0
T60	0	32	0	0
T61	60619	0	0	0
T69	0	8	0	0
T108	0	4	0	0
T298	0	6	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1614	0	0
T3	529406	24	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	21	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	33	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T57	0	9	0	0
T58	0	15	0	0
T59	0	39	0	0
T60	0	11	0	0
T61	60619	0	0	0
T69	0	6	0	0
T88	0	11	0	0
T298	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1126018581	1697	0	0
T3	529406	24	0	0
T6	152855	0	0	0
T7	90655	0	0	0
T25	109767	0	0	0
T40	0	30	0	0
T43	410749	0	0	0
T44	159477	0	0	0
T45	0	38	0	0
T51	238278	0	0	0
T52	18518	0	0	0
T53	50791	0	0	0
T57	0	7	0	0
T58	0	16	0	0
T59	0	36	0	0
T60	0	5	0	0
T61	60619	0	0	0
T69	0	10	0	0
T108	0	1	0	0
T298	0	4	0	0