Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T2 |
9 |
|
T44 |
11 |
|
T358 |
11 |
| auto[1] |
60 |
1 |
|
|
T2 |
11 |
|
T44 |
9 |
|
T358 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T2 |
10 |
|
T44 |
9 |
|
T358 |
10 |
| auto[1] |
54 |
1 |
|
|
T2 |
10 |
|
T44 |
11 |
|
T358 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
58 |
1 |
|
|
T2 |
8 |
|
T44 |
9 |
|
T358 |
8 |
| auto[1] |
62 |
1 |
|
|
T2 |
12 |
|
T44 |
11 |
|
T358 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T2 |
10 |
|
T44 |
11 |
|
T358 |
10 |
| auto[1] |
65 |
1 |
|
|
T2 |
10 |
|
T44 |
9 |
|
T358 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T2 |
12 |
|
T44 |
8 |
|
T358 |
11 |
| auto[1] |
58 |
1 |
|
|
T2 |
8 |
|
T44 |
12 |
|
T358 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T2 |
11 |
|
T44 |
8 |
|
T358 |
11 |
| auto[1] |
65 |
1 |
|
|
T2 |
9 |
|
T44 |
12 |
|
T358 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T2 |
10 |
|
T44 |
10 |
|
T358 |
9 |
| auto[1] |
63 |
1 |
|
|
T2 |
10 |
|
T44 |
10 |
|
T358 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T2 |
7 |
|
T44 |
10 |
|
T358 |
12 |
| auto[1] |
63 |
1 |
|
|
T2 |
13 |
|
T44 |
10 |
|
T358 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69 |
1 |
|
|
T2 |
14 |
|
T44 |
8 |
|
T358 |
14 |
| auto[1] |
51 |
1 |
|
|
T2 |
6 |
|
T44 |
12 |
|
T358 |
6 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
61 |
1 |
|
|
T2 |
10 |
|
T44 |
9 |
|
T358 |
8 |
| auto[1] |
59 |
1 |
|
|
T2 |
10 |
|
T44 |
11 |
|
T358 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T2 |
11 |
|
T44 |
9 |
|
T358 |
10 |
| auto[1] |
58 |
1 |
|
|
T2 |
9 |
|
T44 |
11 |
|
T358 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T2 |
10 |
|
T44 |
14 |
|
T358 |
9 |
| auto[1] |
54 |
1 |
|
|
T2 |
10 |
|
T44 |
6 |
|
T358 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T2 |
9 |
|
T44 |
6 |
|
T358 |
10 |
| auto[1] |
67 |
1 |
|
|
T2 |
11 |
|
T44 |
14 |
|
T358 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
58 |
1 |
|
|
T2 |
12 |
|
T44 |
11 |
|
T358 |
8 |
| auto[1] |
62 |
1 |
|
|
T2 |
8 |
|
T44 |
9 |
|
T358 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T2 |
8 |
|
T44 |
10 |
|
T358 |
15 |
| auto[1] |
56 |
1 |
|
|
T2 |
12 |
|
T44 |
10 |
|
T358 |
5 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T2 |
8 |
|
T44 |
10 |
|
T358 |
9 |
| auto[1] |
61 |
1 |
|
|
T2 |
12 |
|
T44 |
10 |
|
T358 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T2 |
12 |
|
T44 |
8 |
|
T358 |
11 |
| auto[1] |
58 |
1 |
|
|
T2 |
8 |
|
T44 |
12 |
|
T358 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
34 |
1 |
|
|
T2 |
5 |
|
T44 |
4 |
|
T358 |
5 |
| auto[0] |
auto[1] |
23 |
1 |
|
|
T2 |
2 |
|
T44 |
6 |
|
T358 |
7 |
| auto[1] |
auto[0] |
31 |
1 |
|
|
T2 |
6 |
|
T44 |
3 |
|
T358 |
5 |
| auto[1] |
auto[1] |
32 |
1 |
|
|
T2 |
7 |
|
T44 |
7 |
|
T358 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
34 |
1 |
|
|
T2 |
9 |
|
T44 |
4 |
|
T358 |
4 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T2 |
5 |
|
T44 |
4 |
|
T358 |
10 |
| auto[1] |
auto[0] |
19 |
1 |
|
|
T2 |
3 |
|
T44 |
5 |
|
T358 |
2 |
| auto[1] |
auto[1] |
32 |
1 |
|
|
T2 |
3 |
|
T44 |
7 |
|
T358 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
24 |
1 |
|
|
T2 |
5 |
|
T44 |
3 |
|
T358 |
2 |
| auto[0] |
auto[1] |
37 |
1 |
|
|
T2 |
5 |
|
T44 |
6 |
|
T358 |
6 |
| auto[1] |
auto[0] |
32 |
1 |
|
|
T2 |
6 |
|
T44 |
6 |
|
T358 |
8 |
| auto[1] |
auto[1] |
27 |
1 |
|
|
T2 |
4 |
|
T44 |
5 |
|
T358 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
27 |
1 |
|
|
T2 |
6 |
|
T44 |
4 |
|
T358 |
2 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T2 |
5 |
|
T44 |
5 |
|
T358 |
8 |
| auto[1] |
auto[0] |
34 |
1 |
|
|
T2 |
6 |
|
T44 |
7 |
|
T358 |
6 |
| auto[1] |
auto[1] |
24 |
1 |
|
|
T2 |
3 |
|
T44 |
4 |
|
T358 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
29 |
1 |
|
|
T2 |
4 |
|
T44 |
7 |
|
T358 |
2 |
| auto[0] |
auto[1] |
37 |
1 |
|
|
T2 |
6 |
|
T44 |
7 |
|
T358 |
7 |
| auto[1] |
auto[0] |
30 |
1 |
|
|
T2 |
6 |
|
T44 |
2 |
|
T358 |
6 |
| auto[1] |
auto[1] |
24 |
1 |
|
|
T2 |
4 |
|
T44 |
4 |
|
T358 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
23 |
1 |
|
|
T2 |
3 |
|
T44 |
4 |
|
T358 |
4 |
| auto[0] |
auto[1] |
30 |
1 |
|
|
T2 |
6 |
|
T44 |
2 |
|
T358 |
6 |
| auto[1] |
auto[0] |
37 |
1 |
|
|
T2 |
6 |
|
T44 |
7 |
|
T358 |
7 |
| auto[1] |
auto[1] |
30 |
1 |
|
|
T2 |
5 |
|
T44 |
7 |
|
T358 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
29 |
1 |
|
|
T2 |
3 |
|
T44 |
4 |
|
T358 |
6 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T2 |
5 |
|
T44 |
6 |
|
T358 |
9 |
| auto[1] |
auto[0] |
29 |
1 |
|
|
T2 |
5 |
|
T44 |
5 |
|
T358 |
2 |
| auto[1] |
auto[1] |
27 |
1 |
|
|
T2 |
7 |
|
T44 |
5 |
|
T358 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
25 |
1 |
|
|
T2 |
4 |
|
T44 |
5 |
|
T358 |
4 |
| auto[0] |
auto[1] |
34 |
1 |
|
|
T2 |
4 |
|
T44 |
5 |
|
T358 |
5 |
| auto[1] |
auto[0] |
30 |
1 |
|
|
T2 |
6 |
|
T44 |
6 |
|
T358 |
6 |
| auto[1] |
auto[1] |
31 |
1 |
|
|
T2 |
6 |
|
T44 |
4 |
|
T358 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
25 |
1 |
|
|
T2 |
4 |
|
T44 |
5 |
|
T358 |
7 |
| auto[0] |
auto[1] |
30 |
1 |
|
|
T2 |
7 |
|
T44 |
3 |
|
T358 |
4 |
| auto[1] |
auto[0] |
31 |
1 |
|
|
T2 |
5 |
|
T44 |
5 |
|
T358 |
5 |
| auto[1] |
auto[1] |
34 |
1 |
|
|
T2 |
4 |
|
T44 |
7 |
|
T358 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T2 |
10 |
|
T44 |
10 |
|
T358 |
9 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T2 |
10 |
|
T44 |
10 |
|
T358 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
29 |
1 |
|
|
T2 |
6 |
|
T44 |
2 |
|
T358 |
4 |
| auto[0] |
auto[1] |
29 |
1 |
|
|
T2 |
6 |
|
T44 |
9 |
|
T358 |
4 |
| auto[1] |
auto[0] |
37 |
1 |
|
|
T2 |
4 |
|
T44 |
7 |
|
T358 |
6 |
| auto[1] |
auto[1] |
25 |
1 |
|
|
T2 |
4 |
|
T44 |
2 |
|
T358 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T2 |
12 |
|
T44 |
8 |
|
T358 |
11 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T2 |
8 |
|
T44 |
12 |
|
T358 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |