Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
926 |
1 |
|
|
T5 |
9 |
|
T22 |
10 |
|
T23 |
10 |
| auto[1] |
868 |
1 |
|
|
T5 |
11 |
|
T22 |
10 |
|
T23 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T5 |
6 |
|
T22 |
11 |
|
T23 |
9 |
| auto[1] |
904 |
1 |
|
|
T5 |
14 |
|
T22 |
9 |
|
T23 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T5 |
12 |
|
T22 |
13 |
|
T23 |
11 |
| auto[1] |
922 |
1 |
|
|
T5 |
8 |
|
T22 |
7 |
|
T23 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
895 |
1 |
|
|
T5 |
11 |
|
T22 |
10 |
|
T23 |
11 |
| auto[1] |
899 |
1 |
|
|
T5 |
9 |
|
T22 |
10 |
|
T23 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
908 |
1 |
|
|
T5 |
7 |
|
T22 |
13 |
|
T23 |
16 |
| auto[1] |
886 |
1 |
|
|
T5 |
13 |
|
T22 |
7 |
|
T23 |
4 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T5 |
12 |
|
T22 |
10 |
|
T23 |
7 |
| auto[1] |
930 |
1 |
|
|
T5 |
8 |
|
T22 |
10 |
|
T23 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
940 |
1 |
|
|
T5 |
8 |
|
T22 |
11 |
|
T23 |
14 |
| auto[1] |
854 |
1 |
|
|
T5 |
12 |
|
T22 |
9 |
|
T23 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
900 |
1 |
|
|
T5 |
11 |
|
T22 |
5 |
|
T23 |
10 |
| auto[1] |
894 |
1 |
|
|
T5 |
9 |
|
T22 |
15 |
|
T23 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T5 |
6 |
|
T22 |
9 |
|
T23 |
7 |
| auto[1] |
922 |
1 |
|
|
T5 |
14 |
|
T22 |
11 |
|
T23 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T5 |
12 |
|
T22 |
14 |
|
T23 |
9 |
| auto[1] |
893 |
1 |
|
|
T5 |
8 |
|
T22 |
6 |
|
T23 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T5 |
11 |
|
T22 |
9 |
|
T23 |
10 |
| auto[1] |
926 |
1 |
|
|
T5 |
9 |
|
T22 |
11 |
|
T23 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T5 |
8 |
|
T22 |
12 |
|
T23 |
8 |
| auto[1] |
895 |
1 |
|
|
T5 |
12 |
|
T22 |
8 |
|
T23 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T5 |
7 |
|
T22 |
12 |
|
T23 |
8 |
| auto[1] |
890 |
1 |
|
|
T5 |
13 |
|
T22 |
8 |
|
T23 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T5 |
6 |
|
T22 |
11 |
|
T23 |
9 |
| auto[1] |
905 |
1 |
|
|
T5 |
14 |
|
T22 |
9 |
|
T23 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
912 |
1 |
|
|
T5 |
9 |
|
T22 |
12 |
|
T23 |
10 |
| auto[1] |
882 |
1 |
|
|
T5 |
11 |
|
T22 |
8 |
|
T23 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
943 |
1 |
|
|
T5 |
10 |
|
T22 |
13 |
|
T23 |
14 |
| auto[1] |
851 |
1 |
|
|
T5 |
10 |
|
T22 |
7 |
|
T23 |
6 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T5 |
8 |
|
T22 |
12 |
|
T23 |
8 |
| auto[1] |
896 |
1 |
|
|
T5 |
12 |
|
T22 |
8 |
|
T23 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T5 |
11 |
|
T22 |
11 |
|
T23 |
11 |
| auto[1] |
914 |
1 |
|
|
T5 |
9 |
|
T22 |
9 |
|
T23 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
925 |
1 |
|
|
T5 |
7 |
|
T22 |
11 |
|
T23 |
11 |
| auto[1] |
869 |
1 |
|
|
T5 |
13 |
|
T22 |
9 |
|
T23 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T5 |
10 |
|
T22 |
9 |
|
T23 |
7 |
| auto[1] |
905 |
1 |
|
|
T5 |
10 |
|
T22 |
11 |
|
T23 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
925 |
1 |
|
|
T5 |
12 |
|
T22 |
6 |
|
T23 |
11 |
| auto[1] |
869 |
1 |
|
|
T5 |
8 |
|
T22 |
14 |
|
T23 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T5 |
11 |
|
T22 |
10 |
|
T23 |
12 |
| auto[1] |
909 |
1 |
|
|
T5 |
9 |
|
T22 |
10 |
|
T23 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T5 |
8 |
|
T22 |
13 |
|
T23 |
11 |
| auto[1] |
890 |
1 |
|
|
T5 |
12 |
|
T22 |
7 |
|
T23 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
898 |
1 |
|
|
T5 |
8 |
|
T22 |
12 |
|
T23 |
8 |
| auto[1] |
896 |
1 |
|
|
T5 |
12 |
|
T22 |
8 |
|
T23 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
454 |
1 |
|
|
T5 |
5 |
|
T22 |
9 |
|
T23 |
6 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T5 |
4 |
|
T22 |
3 |
|
T23 |
4 |
| auto[1] |
auto[0] |
418 |
1 |
|
|
T5 |
7 |
|
T22 |
4 |
|
T23 |
5 |
| auto[1] |
auto[1] |
464 |
1 |
|
|
T5 |
4 |
|
T22 |
4 |
|
T23 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
481 |
1 |
|
|
T5 |
5 |
|
T22 |
8 |
|
T23 |
8 |
| auto[0] |
auto[1] |
462 |
1 |
|
|
T5 |
5 |
|
T22 |
5 |
|
T23 |
6 |
| auto[1] |
auto[0] |
414 |
1 |
|
|
T5 |
6 |
|
T22 |
2 |
|
T23 |
3 |
| auto[1] |
auto[1] |
437 |
1 |
|
|
T5 |
4 |
|
T22 |
5 |
|
T23 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
453 |
1 |
|
|
T5 |
3 |
|
T22 |
8 |
|
T23 |
6 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T5 |
5 |
|
T22 |
4 |
|
T23 |
2 |
| auto[1] |
auto[0] |
455 |
1 |
|
|
T5 |
4 |
|
T22 |
5 |
|
T23 |
10 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T5 |
8 |
|
T22 |
3 |
|
T23 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T5 |
7 |
|
T22 |
6 |
|
T23 |
3 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T5 |
4 |
|
T22 |
5 |
|
T23 |
8 |
| auto[1] |
auto[0] |
442 |
1 |
|
|
T5 |
5 |
|
T22 |
4 |
|
T23 |
4 |
| auto[1] |
auto[1] |
472 |
1 |
|
|
T5 |
4 |
|
T22 |
5 |
|
T23 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
472 |
1 |
|
|
T5 |
4 |
|
T22 |
6 |
|
T23 |
9 |
| auto[0] |
auto[1] |
453 |
1 |
|
|
T5 |
3 |
|
T22 |
5 |
|
T23 |
2 |
| auto[1] |
auto[0] |
468 |
1 |
|
|
T5 |
4 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[1] |
401 |
1 |
|
|
T5 |
9 |
|
T22 |
4 |
|
T23 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T5 |
7 |
|
T22 |
2 |
|
T23 |
5 |
| auto[0] |
auto[1] |
455 |
1 |
|
|
T5 |
3 |
|
T22 |
7 |
|
T23 |
2 |
| auto[1] |
auto[0] |
466 |
1 |
|
|
T5 |
4 |
|
T22 |
3 |
|
T23 |
5 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T5 |
6 |
|
T22 |
8 |
|
T23 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
444 |
1 |
|
|
T5 |
5 |
|
T22 |
7 |
|
T23 |
5 |
| auto[0] |
auto[1] |
441 |
1 |
|
|
T5 |
6 |
|
T22 |
3 |
|
T23 |
7 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T5 |
7 |
|
T22 |
7 |
|
T23 |
4 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T5 |
2 |
|
T22 |
3 |
|
T23 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T5 |
3 |
|
T22 |
6 |
|
T23 |
5 |
| auto[0] |
auto[1] |
467 |
1 |
|
|
T5 |
5 |
|
T22 |
7 |
|
T23 |
6 |
| auto[1] |
auto[0] |
431 |
1 |
|
|
T5 |
8 |
|
T22 |
3 |
|
T23 |
5 |
| auto[1] |
auto[1] |
459 |
1 |
|
|
T5 |
4 |
|
T22 |
4 |
|
T23 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
447 |
1 |
|
|
T5 |
1 |
|
T22 |
5 |
|
T23 |
5 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T5 |
6 |
|
T22 |
7 |
|
T23 |
3 |
| auto[1] |
auto[0] |
479 |
1 |
|
|
T5 |
8 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T5 |
5 |
|
T22 |
3 |
|
T23 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
889 |
1 |
|
|
T5 |
6 |
|
T22 |
11 |
|
T23 |
9 |
| auto[1] |
auto[1] |
904 |
1 |
|
|
T5 |
14 |
|
T22 |
9 |
|
T23 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
463 |
1 |
|
|
T5 |
2 |
|
T22 |
3 |
|
T23 |
4 |
| auto[0] |
auto[1] |
462 |
1 |
|
|
T5 |
10 |
|
T22 |
3 |
|
T23 |
7 |
| auto[1] |
auto[0] |
409 |
1 |
|
|
T5 |
4 |
|
T22 |
6 |
|
T23 |
3 |
| auto[1] |
auto[1] |
460 |
1 |
|
|
T5 |
4 |
|
T22 |
8 |
|
T23 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
898 |
1 |
|
|
T5 |
8 |
|
T22 |
12 |
|
T23 |
8 |
| auto[1] |
auto[1] |
895 |
1 |
|
|
T5 |
12 |
|
T22 |
8 |
|
T23 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T5 |
6 |
|
T32 |
9 |
|
T260 |
10 |
| auto[1] |
153 |
1 |
|
|
T5 |
14 |
|
T32 |
11 |
|
T260 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T5 |
12 |
|
T32 |
10 |
|
T260 |
9 |
| auto[1] |
134 |
1 |
|
|
T5 |
8 |
|
T32 |
10 |
|
T260 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T5 |
12 |
|
T32 |
10 |
|
T260 |
10 |
| auto[1] |
147 |
1 |
|
|
T5 |
8 |
|
T32 |
10 |
|
T260 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T5 |
9 |
|
T32 |
8 |
|
T260 |
11 |
| auto[1] |
153 |
1 |
|
|
T5 |
11 |
|
T32 |
12 |
|
T260 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T5 |
12 |
|
T32 |
10 |
|
T260 |
11 |
| auto[1] |
136 |
1 |
|
|
T5 |
8 |
|
T32 |
10 |
|
T260 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T5 |
8 |
|
T32 |
11 |
|
T260 |
13 |
| auto[1] |
146 |
1 |
|
|
T5 |
12 |
|
T32 |
9 |
|
T260 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T5 |
11 |
|
T32 |
9 |
|
T260 |
10 |
| auto[1] |
137 |
1 |
|
|
T5 |
9 |
|
T32 |
11 |
|
T260 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T5 |
13 |
|
T32 |
7 |
|
T260 |
11 |
| auto[1] |
133 |
1 |
|
|
T5 |
7 |
|
T32 |
13 |
|
T260 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T5 |
11 |
|
T32 |
9 |
|
T260 |
10 |
| auto[1] |
149 |
1 |
|
|
T5 |
9 |
|
T32 |
11 |
|
T260 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T5 |
11 |
|
T32 |
8 |
|
T260 |
10 |
| auto[1] |
143 |
1 |
|
|
T5 |
9 |
|
T32 |
12 |
|
T260 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T5 |
11 |
|
T32 |
11 |
|
T260 |
11 |
| auto[1] |
141 |
1 |
|
|
T5 |
9 |
|
T32 |
9 |
|
T260 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T5 |
9 |
|
T32 |
10 |
|
T260 |
9 |
| auto[1] |
134 |
1 |
|
|
T5 |
11 |
|
T32 |
10 |
|
T260 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T5 |
13 |
|
T32 |
11 |
|
T260 |
11 |
| auto[1] |
141 |
1 |
|
|
T5 |
7 |
|
T32 |
9 |
|
T260 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T5 |
12 |
|
T32 |
10 |
|
T260 |
9 |
| auto[1] |
134 |
1 |
|
|
T5 |
8 |
|
T32 |
10 |
|
T260 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T5 |
7 |
|
T32 |
8 |
|
T260 |
12 |
| auto[1] |
149 |
1 |
|
|
T5 |
13 |
|
T32 |
12 |
|
T260 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T5 |
6 |
|
T32 |
12 |
|
T260 |
7 |
| auto[1] |
149 |
1 |
|
|
T5 |
14 |
|
T32 |
8 |
|
T260 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T5 |
11 |
|
T32 |
13 |
|
T260 |
9 |
| auto[1] |
127 |
1 |
|
|
T5 |
9 |
|
T32 |
7 |
|
T260 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T5 |
9 |
|
T32 |
12 |
|
T260 |
7 |
| auto[1] |
137 |
1 |
|
|
T5 |
11 |
|
T32 |
8 |
|
T260 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T5 |
10 |
|
T32 |
7 |
|
T260 |
13 |
| auto[1] |
141 |
1 |
|
|
T5 |
10 |
|
T32 |
13 |
|
T260 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T5 |
8 |
|
T32 |
11 |
|
T260 |
12 |
| auto[1] |
141 |
1 |
|
|
T5 |
12 |
|
T32 |
9 |
|
T260 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T5 |
8 |
|
T32 |
8 |
|
T260 |
8 |
| auto[1] |
148 |
1 |
|
|
T5 |
12 |
|
T32 |
12 |
|
T260 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T5 |
11 |
|
T32 |
11 |
|
T260 |
8 |
| auto[1] |
132 |
1 |
|
|
T5 |
9 |
|
T32 |
9 |
|
T260 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T5 |
7 |
|
T32 |
10 |
|
T260 |
13 |
| auto[1] |
142 |
1 |
|
|
T5 |
13 |
|
T32 |
10 |
|
T260 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T5 |
9 |
|
T32 |
10 |
|
T260 |
9 |
| auto[1] |
134 |
1 |
|
|
T5 |
11 |
|
T32 |
10 |
|
T260 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T5 |
3 |
|
T32 |
3 |
|
T260 |
5 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T5 |
4 |
|
T32 |
5 |
|
T260 |
7 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T5 |
9 |
|
T32 |
7 |
|
T260 |
5 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T5 |
4 |
|
T32 |
5 |
|
T260 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T5 |
1 |
|
T32 |
4 |
|
T260 |
3 |
| auto[0] |
auto[1] |
72 |
1 |
|
|
T5 |
5 |
|
T32 |
8 |
|
T260 |
4 |
| auto[1] |
auto[0] |
68 |
1 |
|
|
T5 |
8 |
|
T32 |
4 |
|
T260 |
8 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T5 |
6 |
|
T32 |
4 |
|
T260 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T5 |
7 |
|
T32 |
6 |
|
T260 |
5 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T5 |
4 |
|
T32 |
7 |
|
T260 |
4 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T5 |
5 |
|
T32 |
4 |
|
T260 |
6 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T5 |
4 |
|
T32 |
3 |
|
T260 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T5 |
4 |
|
T32 |
6 |
|
T260 |
5 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T5 |
5 |
|
T32 |
6 |
|
T260 |
2 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T5 |
4 |
|
T32 |
5 |
|
T260 |
8 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T5 |
7 |
|
T32 |
3 |
|
T260 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T5 |
6 |
|
T32 |
3 |
|
T260 |
7 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T5 |
4 |
|
T32 |
4 |
|
T260 |
6 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T5 |
5 |
|
T32 |
6 |
|
T260 |
3 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T5 |
5 |
|
T32 |
7 |
|
T260 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T5 |
6 |
|
T32 |
4 |
|
T260 |
7 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T5 |
2 |
|
T32 |
7 |
|
T260 |
5 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T5 |
7 |
|
T32 |
3 |
|
T260 |
4 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T5 |
5 |
|
T32 |
6 |
|
T260 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T5 |
7 |
|
T32 |
2 |
|
T260 |
3 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T5 |
4 |
|
T32 |
9 |
|
T260 |
5 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T5 |
4 |
|
T32 |
6 |
|
T260 |
7 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T5 |
5 |
|
T32 |
3 |
|
T260 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T5 |
5 |
|
T32 |
3 |
|
T260 |
6 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T5 |
2 |
|
T32 |
7 |
|
T260 |
7 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T5 |
6 |
|
T32 |
8 |
|
T260 |
5 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T5 |
7 |
|
T32 |
2 |
|
T260 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
62 |
1 |
|
|
T5 |
3 |
|
T32 |
5 |
|
T260 |
6 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T5 |
10 |
|
T32 |
6 |
|
T260 |
5 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T5 |
3 |
|
T32 |
4 |
|
T260 |
4 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T5 |
4 |
|
T32 |
5 |
|
T260 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
146 |
1 |
|
|
T5 |
12 |
|
T32 |
10 |
|
T260 |
9 |
| auto[1] |
auto[1] |
134 |
1 |
|
|
T5 |
8 |
|
T32 |
10 |
|
T260 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T5 |
6 |
|
T32 |
1 |
|
T260 |
3 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T5 |
2 |
|
T32 |
7 |
|
T260 |
5 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T5 |
5 |
|
T32 |
8 |
|
T260 |
7 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T5 |
7 |
|
T32 |
4 |
|
T260 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
146 |
1 |
|
|
T5 |
9 |
|
T32 |
10 |
|
T260 |
9 |
| auto[1] |
auto[1] |
134 |
1 |
|
|
T5 |
11 |
|
T32 |
10 |
|
T260 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T20 |
13 |
|
T32 |
9 |
|
T104 |
10 |
| auto[1] |
54 |
1 |
|
|
T20 |
7 |
|
T32 |
11 |
|
T104 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T20 |
8 |
|
T32 |
14 |
|
T104 |
13 |
| auto[1] |
50 |
1 |
|
|
T20 |
12 |
|
T32 |
6 |
|
T104 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T20 |
9 |
|
T32 |
7 |
|
T104 |
12 |
| auto[1] |
66 |
1 |
|
|
T20 |
11 |
|
T32 |
13 |
|
T104 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
65 |
1 |
|
|
T20 |
8 |
|
T32 |
13 |
|
T104 |
12 |
| auto[1] |
55 |
1 |
|
|
T20 |
12 |
|
T32 |
7 |
|
T104 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T20 |
11 |
|
T32 |
9 |
|
T104 |
7 |
| auto[1] |
61 |
1 |
|
|
T20 |
9 |
|
T32 |
11 |
|
T104 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T20 |
9 |
|
T32 |
12 |
|
T104 |
12 |
| auto[1] |
56 |
1 |
|
|
T20 |
11 |
|
T32 |
8 |
|
T104 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T20 |
13 |
|
T32 |
9 |
|
T104 |
11 |
| auto[1] |
56 |
1 |
|
|
T20 |
7 |
|
T32 |
11 |
|
T104 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T20 |
12 |
|
T32 |
9 |
|
T104 |
9 |
| auto[1] |
66 |
1 |
|
|
T20 |
8 |
|
T32 |
11 |
|
T104 |
11 |