Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.96 99.37 96.71 100.00 96.79 98.85 99.52 94.50


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
70.52 70.52 86.49 86.49 77.63 77.63 87.21 87.21 39.74 39.74 87.47 87.47 75.14 75.14 39.92 39.92 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1802154685
78.89 8.38 93.41 6.92 87.08 9.45 96.58 9.36 51.28 11.54 93.09 5.62 84.20 9.06 46.61 6.69 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2741188503
85.88 6.99 95.84 2.43 89.53 2.45 96.80 0.23 68.59 17.31 95.34 2.26 89.40 5.20 65.67 19.07 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.912998497
88.28 2.39 96.96 1.12 90.95 1.42 97.03 0.23 76.28 7.69 96.34 1.00 92.68 3.28 67.69 2.02 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3558919361
90.28 2.01 98.04 1.08 92.52 1.57 97.03 0.00 86.54 10.26 97.49 1.15 92.68 0.00 67.69 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.559575344
91.75 1.46 98.04 0.00 92.59 0.08 97.49 0.46 86.54 0.00 97.52 0.04 92.97 0.29 77.09 9.40 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2081632283
92.92 1.17 98.12 0.07 93.76 1.16 98.17 0.68 86.54 0.00 97.63 0.11 92.97 0.00 83.23 6.14 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2133124034
93.85 0.93 98.19 0.07 93.88 0.13 98.17 0.00 87.18 0.64 97.67 0.04 96.34 3.37 85.52 2.29 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.36701570
94.39 0.54 98.43 0.24 94.06 0.18 98.17 0.00 89.10 1.92 97.82 0.15 96.82 0.48 86.30 0.78 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3698642840
94.82 0.43 98.51 0.07 94.11 0.05 98.17 0.00 90.38 1.28 97.89 0.07 97.01 0.19 87.63 1.33 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2996270322
95.21 0.39 98.64 0.13 94.26 0.15 98.17 0.00 91.67 1.28 98.08 0.18 97.40 0.39 88.22 0.60 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.328438803
95.55 0.35 98.77 0.13 94.39 0.13 98.17 0.00 92.95 1.28 98.26 0.18 97.69 0.29 88.63 0.41 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2537507611
95.83 0.28 98.77 0.00 94.41 0.03 99.77 1.60 92.95 0.00 98.26 0.00 97.78 0.10 88.86 0.23 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3117620489
96.07 0.24 98.84 0.07 94.46 0.05 99.77 0.00 93.59 0.64 98.30 0.04 98.17 0.39 89.32 0.46 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3459620028
96.23 0.17 98.88 0.04 94.82 0.35 99.77 0.00 94.23 0.64 98.34 0.04 98.27 0.10 89.32 0.00 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.812053938
96.37 0.14 98.88 0.00 94.82 0.00 99.77 0.00 94.23 0.00 98.34 0.00 98.27 0.00 90.28 0.96 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2388885742
96.51 0.14 98.88 0.00 95.73 0.91 99.77 0.00 94.23 0.00 98.34 0.00 98.27 0.00 90.33 0.05 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.184440679
96.64 0.14 98.96 0.07 95.75 0.03 99.77 0.00 94.87 0.64 98.45 0.11 98.36 0.10 90.33 0.00 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1423095753
96.77 0.13 98.99 0.04 95.78 0.03 99.77 0.00 95.51 0.64 98.48 0.04 98.46 0.10 90.38 0.05 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2788317687
96.89 0.13 99.03 0.04 95.80 0.03 99.77 0.00 96.15 0.64 98.52 0.04 98.55 0.10 90.42 0.05 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1685739417
97.02 0.12 99.03 0.00 95.90 0.10 99.77 0.00 96.15 0.00 98.52 0.00 99.33 0.77 90.42 0.00 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2409717600
97.14 0.12 99.07 0.04 95.93 0.03 99.77 0.00 96.79 0.64 98.56 0.04 99.42 0.10 90.42 0.00 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3931231855
97.24 0.10 99.07 0.00 95.93 0.00 99.77 0.00 96.79 0.00 98.56 0.00 99.42 0.00 91.15 0.73 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.4111944614
97.32 0.08 99.12 0.06 95.93 0.00 99.77 0.00 96.79 0.00 98.56 0.00 99.42 0.00 91.66 0.50 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1081395656
97.38 0.06 99.12 0.00 96.33 0.40 99.77 0.00 96.79 0.00 98.56 0.00 99.42 0.00 91.66 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1651364878
97.43 0.05 99.12 0.00 96.33 0.00 99.77 0.00 96.79 0.00 98.56 0.00 99.42 0.00 92.03 0.37 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1553994568
97.48 0.05 99.18 0.06 96.41 0.08 100.00 0.23 96.79 0.00 98.56 0.00 99.42 0.00 92.03 0.00 /workspace/coverage/default/18.sysrst_ctrl_alert_test.1847862654
97.53 0.04 99.18 0.00 96.44 0.03 100.00 0.00 96.79 0.00 98.56 0.00 99.52 0.10 92.21 0.18 /workspace/coverage/default/37.sysrst_ctrl_stress_all.625530615
97.57 0.04 99.18 0.00 96.44 0.00 100.00 0.00 96.79 0.00 98.56 0.00 99.52 0.00 92.48 0.27 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3111608994
97.60 0.04 99.22 0.04 96.59 0.15 100.00 0.00 96.79 0.00 98.63 0.07 99.52 0.00 92.48 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2419803385
97.64 0.03 99.22 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 92.71 0.23 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1643402590
97.67 0.03 99.22 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 92.94 0.23 /workspace/coverage/default/6.sysrst_ctrl_stress_all.2516150130
97.70 0.03 99.23 0.02 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 93.13 0.18 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1288825662
97.73 0.03 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 93.31 0.18 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1315723039
97.74 0.02 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 93.45 0.14 /workspace/coverage/default/48.sysrst_ctrl_stress_all.2329734022
97.76 0.02 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 93.58 0.14 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1953299270
97.78 0.02 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 93.72 0.14 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1985555837
97.80 0.01 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 93.81 0.09 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.955727260
97.81 0.01 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 93.90 0.09 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1011311514
97.82 0.01 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 94.00 0.09 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1517270338
97.84 0.01 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 94.09 0.09 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3429734682
97.85 0.01 99.23 0.00 96.59 0.00 100.00 0.00 96.79 0.00 98.63 0.00 99.52 0.00 94.18 0.09 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.242295843
97.86 0.01 99.25 0.02 96.61 0.03 100.00 0.00 96.79 0.00 98.67 0.04 99.52 0.00 94.18 0.00 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.99831868
97.87 0.01 99.27 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.67 0.00 99.52 0.00 94.23 0.05 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3485151246
97.88 0.01 99.29 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.71 0.04 99.52 0.00 94.23 0.00 /workspace/coverage/default/11.sysrst_ctrl_stress_all.1251191738
97.89 0.01 99.31 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.74 0.04 99.52 0.00 94.23 0.00 /workspace/coverage/default/2.sysrst_ctrl_stress_all.3062365931
97.89 0.01 99.33 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.78 0.04 99.52 0.00 94.23 0.00 /workspace/coverage/default/23.sysrst_ctrl_stress_all.4174313526
97.90 0.01 99.35 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.82 0.04 99.52 0.00 94.23 0.00 /workspace/coverage/default/27.sysrst_ctrl_stress_all.867452824
97.91 0.01 99.37 0.02 96.61 0.00 100.00 0.00 96.79 0.00 98.85 0.04 99.52 0.00 94.23 0.00 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2258712089
97.92 0.01 99.37 0.00 96.66 0.05 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.23 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.573327221
97.92 0.01 99.37 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.27 0.05 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1840506761
97.93 0.01 99.37 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.32 0.05 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.969278618
97.94 0.01 99.37 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.36 0.05 /workspace/coverage/default/0.sysrst_ctrl_stress_all.1187060324
97.94 0.01 99.37 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.41 0.05 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.1204207775
97.95 0.01 99.37 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.45 0.05 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3505055166
97.96 0.01 99.37 0.00 96.66 0.00 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.50 0.05 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.636869809
97.96 0.01 99.37 0.00 96.69 0.03 100.00 0.00 96.79 0.00 98.85 0.00 99.52 0.00 94.50 0.00 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2163614074

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.424745802
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.394551518
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4140441100
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3445158820
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2499630731
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1823525998
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4164619242
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1043991015
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1916377490
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1235221120
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2358914023
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2474996566
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1784066819
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2024575175
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.715810310
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1391481763
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3395630599
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3144940543
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4272793880
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.534809401
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1093179140
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.112292601
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2931277215
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3263070999
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1729273418
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.330203729
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1858599677
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3614116304
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.289207170
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2361597053
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2558113577
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.552471093
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1739384325
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3090660751
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2830552722
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.554546075
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1873284595
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.213222075
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2084246789
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3276853070
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1033015210
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3022233056
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3418676766
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1959380110
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1212454920
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.39591991
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3220234597
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1519628571
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.765380086
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2887365184
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1034027034
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3056469670
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1730852246
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1110137607
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3732882
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.325654399
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1920196283
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3900547196
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.4131728935
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3043980704
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.644674079
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.4022086284
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3173096448
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2304852528
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3867059266
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2421917236
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.993327594
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.812007251
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.89491044
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1467352840
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.28429381
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2737188053
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3887633368
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.221369586
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.174183440
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1612646816
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.449254580
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1041499824
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1892057888
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2280065901
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.948518177
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4082497159
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1456119893
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2574594607
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3644973761
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2613959787
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.113682181
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3610771781
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.154588055
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1620758547
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3931799803
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2650811355
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.745798542
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1724935425
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.881029758
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3084139954
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1692098225
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1546528443
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1286454579
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1283855520
/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3969623921
/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1935008756
/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3913756927
/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.103403792
/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3159763826
/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.105082842
/workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2780140664
/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.167706894
/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1261867107
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/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3910475970
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2251531553
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2598477201
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2933069281
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.992320429
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3348784950
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3049922982
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.237694974
/workspace/coverage/default/43.sysrst_ctrl_smoke.930177419
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2893010939
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3737025765
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3501066132
/workspace/coverage/default/44.sysrst_ctrl_alert_test.663155472
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4201576656
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.410822379
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1189866211
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1710053107
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.2904044764
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.360607027
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1721595985
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2762436604
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3366438109
/workspace/coverage/default/44.sysrst_ctrl_smoke.3980086622
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2898931762
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2567659197
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2186455181
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3090888585
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3504108548
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1536068463
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3337250569
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1443800551
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3851608261
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3860390930
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2556853336
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2270307852
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1865988335
/workspace/coverage/default/45.sysrst_ctrl_smoke.1759833721
/workspace/coverage/default/45.sysrst_ctrl_stress_all.3147106558
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2172451138
/workspace/coverage/default/46.sysrst_ctrl_alert_test.4288038857
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1242165619
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.4160352997
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3863830929
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.19105848
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.956586536
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3269589238
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2737022227
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1469865973
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2069052730
/workspace/coverage/default/46.sysrst_ctrl_smoke.2934250650
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1486857672
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3973938142
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1292568219
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1371728689
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3467496462
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2819104905
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.932978589
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1211154303
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.255788372
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2232452271
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1310880501
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.235412600
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2628313248
/workspace/coverage/default/47.sysrst_ctrl_smoke.347981166
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3661986200
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4101692247
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.844024414
/workspace/coverage/default/48.sysrst_ctrl_alert_test.4036919880
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3751239812
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.709663184
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2322765958
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2272917227
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1545879171
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.863548642
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3713553576
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3422123859
/workspace/coverage/default/48.sysrst_ctrl_smoke.1487755598
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3907919671
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2042961995
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3653016137
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1342931318
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2214344303
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.658935146
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.4047989327
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2634315822
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3941834741
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3271703235
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1015916343
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.841611310
/workspace/coverage/default/49.sysrst_ctrl_smoke.1877434148
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2728156971
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.260751543
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1112483042
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.285937046
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2274979245
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1199778663
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.50106172
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3392932026
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.948220966
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3655426303
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2979336211
/workspace/coverage/default/5.sysrst_ctrl_smoke.3220016196
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2932057595
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1803688032
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.494855089
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1343163373
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2989999838
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2144141184
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1931946314
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1631727324
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2233442066
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1055149707
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2501074236
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3100883669
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1036084771
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.615518408
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.947518044
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2228346039
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1199676709
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.506764769
/workspace/coverage/default/6.sysrst_ctrl_smoke.94401768
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1040867163
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2462164452
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1166688882
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.765973773
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3244900138
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4275474136
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2696804376
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4208239809
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.283019997
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2477476484
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.349814224
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1561901949
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1616470328
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.513033476
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1779305033
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1440203508
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1891989606
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2437822282
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1480442004
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4086214901
/workspace/coverage/default/7.sysrst_ctrl_smoke.3345565703
/workspace/coverage/default/7.sysrst_ctrl_stress_all.464893359
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1567850871
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2630921959
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.4131577189
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.824381487
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.660582626
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1391823021
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1301158261
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.373654441
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1951715424
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1746383844
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1042486491
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3211751455
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.2579332116
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.4252892518
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2981410764
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2815835839
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3899919331
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.103417903
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3029203613
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.523434569
/workspace/coverage/default/8.sysrst_ctrl_smoke.4116442853
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3979106286
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.778374247
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.274036019
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1129834912
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2307176785
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2898667853
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3029279656
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.494660960
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.4244547377
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.828448531
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.912237512
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1234929463
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.4095317305
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.377934855
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1487270564
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1413829202
/workspace/coverage/default/9.sysrst_ctrl_smoke.3523100960
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2019455570
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2200719607
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1358324277
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3714943051
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.309788048
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3810668124
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.4102613206
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2415062544
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3302284417
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2461939187



Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3919848429 Jul 28 05:13:00 PM PDT 24 Jul 28 05:13:29 PM PDT 24 79067515504 ps
T4 /workspace/coverage/default/30.sysrst_ctrl_smoke.525165477 Jul 28 05:12:53 PM PDT 24 Jul 28 05:12:59 PM PDT 24 2111831480 ps
T2 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3746456492 Jul 28 05:12:43 PM PDT 24 Jul 28 05:13:55 PM PDT 24 103470711790 ps
T3 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3459620028 Jul 28 05:13:27 PM PDT 24 Jul 28 05:15:40 PM PDT 24 103458550487 ps
T12 /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3001970637 Jul 28 05:11:55 PM PDT 24 Jul 28 05:11:57 PM PDT 24 3642154453 ps
T13 /workspace/coverage/default/34.sysrst_ctrl_alert_test.1549423718 Jul 28 05:12:49 PM PDT 24 Jul 28 05:12:52 PM PDT 24 2024250182 ps
T14 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1342931318 Jul 28 05:13:10 PM PDT 24 Jul 28 05:24:28 PM PDT 24 251648463756 ps
T15 /workspace/coverage/default/35.sysrst_ctrl_alert_test.2903052138 Jul 28 05:13:04 PM PDT 24 Jul 28 05:13:09 PM PDT 24 2011130790 ps
T16 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1815674402 Jul 28 05:13:04 PM PDT 24 Jul 28 05:13:06 PM PDT 24 2179509652 ps
T5 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1802154685 Jul 28 05:12:22 PM PDT 24 Jul 28 05:14:11 PM PDT 24 170247493081 ps
T24 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2809688609 Jul 28 05:13:07 PM PDT 24 Jul 28 05:13:11 PM PDT 24 2519879557 ps
T6 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1431041949 Jul 28 05:12:35 PM PDT 24 Jul 28 05:12:38 PM PDT 24 4373520801 ps
T45 /workspace/coverage/default/18.sysrst_ctrl_alert_test.1847862654 Jul 28 05:12:33 PM PDT 24 Jul 28 05:12:39 PM PDT 24 2011941497 ps
T7 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.291335076 Jul 28 05:13:04 PM PDT 24 Jul 28 05:14:54 PM PDT 24 88431962529 ps
T25 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3698642840 Jul 28 05:12:32 PM PDT 24 Jul 28 05:14:46 PM PDT 24 66797057425 ps
T36 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1418573305 Jul 28 05:12:31 PM PDT 24 Jul 28 05:12:32 PM PDT 24 3691179008 ps
T8 /workspace/coverage/default/9.sysrst_ctrl_stress_all.2019455570 Jul 28 05:12:18 PM PDT 24 Jul 28 05:12:42 PM PDT 24 10389559682 ps
T46 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3861468823 Jul 28 05:13:05 PM PDT 24 Jul 28 05:13:12 PM PDT 24 2613288781 ps
T47 /workspace/coverage/default/10.sysrst_ctrl_smoke.1786640867 Jul 28 05:12:12 PM PDT 24 Jul 28 05:12:15 PM PDT 24 2135585022 ps
T48 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1865988335 Jul 28 05:13:12 PM PDT 24 Jul 28 05:13:13 PM PDT 24 2574463863 ps
T49 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2431983120 Jul 28 05:12:37 PM PDT 24 Jul 28 05:12:43 PM PDT 24 2607606467 ps
T101 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3117620489 Jul 28 05:11:59 PM PDT 24 Jul 28 05:13:42 PM PDT 24 42008286466 ps
T9 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3851608261 Jul 28 05:13:12 PM PDT 24 Jul 28 05:13:15 PM PDT 24 2601775116 ps
T151 /workspace/coverage/default/23.sysrst_ctrl_alert_test.110454695 Jul 28 05:12:32 PM PDT 24 Jul 28 05:12:35 PM PDT 24 2020954277 ps
T10 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4101692247 Jul 28 05:13:27 PM PDT 24 Jul 28 05:15:38 PM PDT 24 50752318879 ps
T11 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.513033476 Jul 28 05:12:29 PM PDT 24 Jul 28 05:12:56 PM PDT 24 77120628047 ps
T30 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2356148734 Jul 28 05:12:58 PM PDT 24 Jul 28 05:13:07 PM PDT 24 5334011337 ps
T29 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2741188503 Jul 28 05:13:31 PM PDT 24 Jul 28 05:18:34 PM PDT 24 125037727058 ps
T37 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1951715424 Jul 28 05:13:31 PM PDT 24 Jul 28 05:14:43 PM PDT 24 27331706993 ps
T34 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2320875986 Jul 28 05:12:01 PM PDT 24 Jul 28 05:12:03 PM PDT 24 4927441401 ps
T38 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1391823021 Jul 28 05:13:28 PM PDT 24 Jul 28 05:15:48 PM PDT 24 57144074073 ps
T64 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.715828707 Jul 28 05:12:32 PM PDT 24 Jul 28 05:12:41 PM PDT 24 2999253535 ps
T39 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.3409007259 Jul 28 05:12:19 PM PDT 24 Jul 28 05:13:29 PM PDT 24 108604869473 ps
T131 /workspace/coverage/default/24.sysrst_ctrl_alert_test.818710682 Jul 28 05:12:27 PM PDT 24 Jul 28 05:12:32 PM PDT 24 2009585432 ps
T35 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3534367744 Jul 28 05:13:04 PM PDT 24 Jul 28 05:13:06 PM PDT 24 3860688643 ps
T132 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.221709022 Jul 28 05:12:24 PM PDT 24 Jul 28 05:12:35 PM PDT 24 3927186101 ps
T40 /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3951621782 Jul 28 05:12:28 PM PDT 24 Jul 28 05:12:37 PM PDT 24 3531743494 ps
T156 /workspace/coverage/default/25.sysrst_ctrl_alert_test.2992076060 Jul 28 05:12:34 PM PDT 24 Jul 28 05:12:37 PM PDT 24 2021285332 ps
T65 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.2169993985 Jul 28 05:12:56 PM PDT 24 Jul 28 05:12:59 PM PDT 24 2459957947 ps
T347 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.19105848 Jul 28 05:13:25 PM PDT 24 Jul 28 05:28:10 PM PDT 24 1340549807751 ps
T22 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.863548642 Jul 28 05:13:11 PM PDT 24 Jul 28 05:13:13 PM PDT 24 2494129097 ps
T61 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.992320429 Jul 28 05:13:18 PM PDT 24 Jul 28 05:13:20 PM PDT 24 2628034521 ps
T23 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.195054398 Jul 28 05:12:23 PM PDT 24 Jul 28 05:12:29 PM PDT 24 2437238156 ps
T20 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3558919361 Jul 28 05:12:31 PM PDT 24 Jul 28 05:13:23 PM PDT 24 113223126985 ps
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T21 /workspace/coverage/default/39.sysrst_ctrl_stress_all.3207414792 Jul 28 05:13:07 PM PDT 24 Jul 28 05:13:21 PM PDT 24 12056654184 ps
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T41 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3041955477 Jul 28 05:12:59 PM PDT 24 Jul 28 05:13:08 PM PDT 24 3342499906 ps
T63 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1216258342 Jul 28 05:12:09 PM PDT 24 Jul 28 05:12:12 PM PDT 24 2524329134 ps
T51 /workspace/coverage/default/33.sysrst_ctrl_stress_all.2631602687 Jul 28 05:13:05 PM PDT 24 Jul 28 05:13:12 PM PDT 24 7137801578 ps
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T42 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3367706471 Jul 28 05:13:00 PM PDT 24 Jul 28 05:13:02 PM PDT 24 4109050180 ps
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T149 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2964362274 Jul 28 05:11:55 PM PDT 24 Jul 28 05:12:06 PM PDT 24 4296174325 ps
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T220 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1535994748 Jul 28 05:13:05 PM PDT 24 Jul 28 05:13:09 PM PDT 24 2520865556 ps
T32 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.912998497 Jul 28 05:12:54 PM PDT 24 Jul 28 05:14:42 PM PDT 24 196496673978 ps
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T56 /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3449686113 Jul 28 05:12:25 PM PDT 24 Jul 28 05:12:30 PM PDT 24 2449430858 ps
T52 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.812053938 Jul 28 05:12:18 PM PDT 24 Jul 28 05:12:22 PM PDT 24 5958802651 ps
T113 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.71773219 Jul 28 05:12:25 PM PDT 24 Jul 28 05:12:26 PM PDT 24 2123463063 ps
T44 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3683086553 Jul 28 05:12:58 PM PDT 24 Jul 28 05:16:55 PM PDT 24 89007462303 ps
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T53 /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1232875723 Jul 28 05:12:34 PM PDT 24 Jul 28 05:12:42 PM PDT 24 7168360605 ps
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T58 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4029932530 Jul 28 05:13:03 PM PDT 24 Jul 28 05:13:10 PM PDT 24 2446536862 ps
T114 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.1852327331 Jul 28 05:12:32 PM PDT 24 Jul 28 05:12:41 PM PDT 24 3166267600 ps
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T351 /workspace/coverage/default/30.sysrst_ctrl_alert_test.1923929217 Jul 28 05:12:56 PM PDT 24 Jul 28 05:12:58 PM PDT 24 2092218542 ps
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T355 /workspace/coverage/default/44.sysrst_ctrl_stress_all.2898931762 Jul 28 05:13:15 PM PDT 24 Jul 28 05:13:22 PM PDT 24 13444074311 ps
T70 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1685739417 Jul 28 05:11:59 PM PDT 24 Jul 28 05:13:21 PM PDT 24 132170568398 ps
T54 /workspace/coverage/default/40.sysrst_ctrl_stress_all.1360786463 Jul 28 05:13:05 PM PDT 24 Jul 28 05:13:37 PM PDT 24 12652058565 ps
T55 /workspace/coverage/default/23.sysrst_ctrl_stress_all.4174313526 Jul 28 05:12:28 PM PDT 24 Jul 28 05:16:34 PM PDT 24 182833793784 ps
T67 /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1854507573 Jul 28 05:12:42 PM PDT 24 Jul 28 05:12:48 PM PDT 24 4889528796 ps
T96 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3860390930 Jul 28 05:13:08 PM PDT 24 Jul 28 05:13:16 PM PDT 24 2633407882 ps
T97 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1211154303 Jul 28 05:13:08 PM PDT 24 Jul 28 05:13:09 PM PDT 24 2729110373 ps
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T59 /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.4106294960 Jul 28 05:12:47 PM PDT 24 Jul 28 05:12:49 PM PDT 24 2499177826 ps
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T60 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3202928878 Jul 28 05:13:02 PM PDT 24 Jul 28 05:13:03 PM PDT 24 2508552501 ps
T356 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1393239562 Jul 28 05:13:07 PM PDT 24 Jul 28 05:13:14 PM PDT 24 2177962680 ps
T82 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1406737602 Jul 28 05:12:38 PM PDT 24 Jul 28 05:13:49 PM PDT 24 27581314228 ps
T100 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2401363103 Jul 28 05:12:36 PM PDT 24 Jul 28 05:14:24 PM PDT 24 91789672320 ps
T357 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2374902878 Jul 28 05:12:33 PM PDT 24 Jul 28 05:12:38 PM PDT 24 2617462273 ps
T349 /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.3261103360 Jul 28 05:12:46 PM PDT 24 Jul 28 05:12:48 PM PDT 24 2552815572 ps
T126 /workspace/coverage/default/25.sysrst_ctrl_stress_all.1247662116 Jul 28 05:12:29 PM PDT 24 Jul 28 05:12:48 PM PDT 24 6879906501 ps
T358 /workspace/coverage/default/48.sysrst_ctrl_alert_test.4036919880 Jul 28 05:13:27 PM PDT 24 Jul 28 05:13:31 PM PDT 24 2018679048 ps
T359 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1779305033 Jul 28 05:12:05 PM PDT 24 Jul 28 05:12:09 PM PDT 24 4478841420 ps
T213 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2307176785 Jul 28 05:13:34 PM PDT 24 Jul 28 05:15:07 PM PDT 24 34589629333 ps
T259 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2981410764 Jul 28 05:12:17 PM PDT 24 Jul 28 05:12:20 PM PDT 24 3663186193 ps
T360 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4234143431 Jul 28 05:11:57 PM PDT 24 Jul 28 05:12:00 PM PDT 24 2197732307 ps
T68 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.4023682516 Jul 28 05:12:35 PM PDT 24 Jul 28 05:13:51 PM PDT 24 36182651714 ps
T281 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2152650777 Jul 28 05:12:40 PM PDT 24 Jul 28 05:12:49 PM PDT 24 3679605131 ps
T282 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2280298762 Jul 28 05:13:07 PM PDT 24 Jul 28 05:13:13 PM PDT 24 2611327345 ps
T77 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.956586536 Jul 28 05:13:16 PM PDT 24 Jul 28 05:13:23 PM PDT 24 2724378589 ps
T83 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.36701570 Jul 28 05:13:15 PM PDT 24 Jul 28 05:13:54 PM PDT 24 281271308730 ps
T171 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3528323209 Jul 28 05:11:50 PM PDT 24 Jul 28 05:11:52 PM PDT 24 2480719157 ps
T103 /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1502794196 Jul 28 05:11:54 PM PDT 24 Jul 28 05:12:04 PM PDT 24 44560944012 ps
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T173 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3505055166 Jul 28 05:13:29 PM PDT 24 Jul 28 05:14:25 PM PDT 24 37885593245 ps
T174 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3422123859 Jul 28 05:13:24 PM PDT 24 Jul 28 05:13:28 PM PDT 24 2522109081 ps
T175 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3271703235 Jul 28 05:13:37 PM PDT 24 Jul 28 05:13:44 PM PDT 24 2446165881 ps
T127 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1339194570 Jul 28 05:12:44 PM PDT 24 Jul 28 05:12:46 PM PDT 24 3615667693 ps
T176 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.76293739 Jul 28 05:12:17 PM PDT 24 Jul 28 05:12:19 PM PDT 24 2467148435 ps
T361 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3039170950 Jul 28 05:12:14 PM PDT 24 Jul 28 05:12:18 PM PDT 24 5226699019 ps
T362 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2731191687 Jul 28 05:13:03 PM PDT 24 Jul 28 05:13:06 PM PDT 24 2459490981 ps
T260 /workspace/coverage/default/1.sysrst_ctrl_stress_all.2088456459 Jul 28 05:11:57 PM PDT 24 Jul 28 05:12:17 PM PDT 24 13962630736 ps
T169 /workspace/coverage/default/21.sysrst_ctrl_edge_detect.168151391 Jul 28 05:12:28 PM PDT 24 Jul 28 05:12:31 PM PDT 24 3099657053 ps
T218 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1271696415 Jul 28 05:12:53 PM PDT 24 Jul 28 05:13:24 PM PDT 24 46135269676 ps
T363 /workspace/coverage/default/13.sysrst_ctrl_alert_test.733023397 Jul 28 05:12:23 PM PDT 24 Jul 28 05:12:28 PM PDT 24 2012495997 ps
T364 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1977143495 Jul 28 05:12:25 PM PDT 24 Jul 28 05:12:33 PM PDT 24 2475902204 ps
T365 /workspace/coverage/default/18.sysrst_ctrl_smoke.670045138 Jul 28 05:12:30 PM PDT 24 Jul 28 05:12:36 PM PDT 24 2109687868 ps
T366 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.4127865819 Jul 28 05:12:55 PM PDT 24 Jul 28 05:13:02 PM PDT 24 2445593026 ps
T367 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3047469683 Jul 28 05:12:25 PM PDT 24 Jul 28 05:12:31 PM PDT 24 3057097517 ps
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T71 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.328438803 Jul 28 05:13:00 PM PDT 24 Jul 28 05:14:34 PM PDT 24 1771986221448 ps
T137 /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1891989606 Jul 28 05:12:19 PM PDT 24 Jul 28 05:12:28 PM PDT 24 2621702193 ps
T138 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2757688591 Jul 28 05:13:02 PM PDT 24 Jul 28 05:13:03 PM PDT 24 2659836278 ps
T139 /workspace/coverage/default/35.sysrst_ctrl_stress_all.3623140785 Jul 28 05:13:04 PM PDT 24 Jul 28 05:13:22 PM PDT 24 13887578282 ps
T140 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1288657692 Jul 28 05:12:54 PM PDT 24 Jul 28 05:13:04 PM PDT 24 3578600502 ps
T141 /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.309104117 Jul 28 05:12:14 PM PDT 24 Jul 28 05:12:16 PM PDT 24 2631900076 ps
T142 /workspace/coverage/default/5.sysrst_ctrl_smoke.3220016196 Jul 28 05:11:45 PM PDT 24 Jul 28 05:11:49 PM PDT 24 2111057011 ps
T143 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.4133304853 Jul 28 05:12:40 PM PDT 24 Jul 28 05:12:46 PM PDT 24 2260714321 ps
T144 /workspace/coverage/default/49.sysrst_ctrl_smoke.1877434148 Jul 28 05:13:21 PM PDT 24 Jul 28 05:13:25 PM PDT 24 2115498746 ps
T145 /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.237694974 Jul 28 05:13:10 PM PDT 24 Jul 28 05:13:12 PM PDT 24 2538963366 ps
T84 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.10293100 Jul 28 05:12:48 PM PDT 24 Jul 28 05:13:20 PM PDT 24 24587331842 ps
T85 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1746383844 Jul 28 05:13:30 PM PDT 24 Jul 28 05:15:17 PM PDT 24 41976894749 ps
T86 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3093320983 Jul 28 05:13:07 PM PDT 24 Jul 28 05:14:07 PM PDT 24 30215296834 ps
T369 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1199676709 Jul 28 05:11:58 PM PDT 24 Jul 28 05:12:03 PM PDT 24 2175100901 ps
T370 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.371845659 Jul 28 05:12:05 PM PDT 24 Jul 28 05:12:07 PM PDT 24 2135485599 ps
T262 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2628313248 Jul 28 05:13:18 PM PDT 24 Jul 28 05:13:22 PM PDT 24 2521045152 ps
T146 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.312842013 Jul 28 05:12:17 PM PDT 24 Jul 28 05:12:19 PM PDT 24 3522718746 ps
T371 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1443800551 Jul 28 05:13:13 PM PDT 24 Jul 28 05:13:16 PM PDT 24 3157452958 ps
T372 /workspace/coverage/default/36.sysrst_ctrl_smoke.996007624 Jul 28 05:12:58 PM PDT 24 Jul 28 05:13:00 PM PDT 24 2132398115 ps
T147 /workspace/coverage/default/7.sysrst_ctrl_stress_all.464893359 Jul 28 05:12:06 PM PDT 24 Jul 28 05:12:42 PM PDT 24 14685653605 ps
T373 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3850909009 Jul 28 05:12:18 PM PDT 24 Jul 28 05:12:22 PM PDT 24 2613842593 ps
T256 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1288825662 Jul 28 05:13:23 PM PDT 24 Jul 28 05:14:30 PM PDT 24 93328013045 ps
T374 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1399790573 Jul 28 05:13:09 PM PDT 24 Jul 28 05:13:10 PM PDT 24 2215077821 ps
T104 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.99831868 Jul 28 05:12:28 PM PDT 24 Jul 28 05:12:59 PM PDT 24 57361536328 ps
T375 /workspace/coverage/default/24.sysrst_ctrl_smoke.2564980181 Jul 28 05:12:31 PM PDT 24 Jul 28 05:12:36 PM PDT 24 2114750559 ps
T376 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1507224007 Jul 28 05:12:06 PM PDT 24 Jul 28 05:12:10 PM PDT 24 2620678904 ps
T377 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.143607683 Jul 28 05:13:03 PM PDT 24 Jul 28 05:13:12 PM PDT 24 3642357154 ps
T378 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1197953109 Jul 28 05:13:07 PM PDT 24 Jul 28 05:13:09 PM PDT 24 3176805682 ps
T87 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1808657911 Jul 28 05:12:31 PM PDT 24 Jul 28 05:13:21 PM PDT 24 80978208783 ps
T379 /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1205107541 Jul 28 05:11:58 PM PDT 24 Jul 28 05:12:00 PM PDT 24 2191095359 ps
T254 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.18053750 Jul 28 05:13:01 PM PDT 24 Jul 28 05:13:46 PM PDT 24 19842875705 ps
T380 /workspace/coverage/default/20.sysrst_ctrl_alert_test.716722189 Jul 28 05:12:47 PM PDT 24 Jul 28 05:12:51 PM PDT 24 2014811843 ps
T381 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1007079481 Jul 28 05:12:15 PM PDT 24 Jul 28 05:12:18 PM PDT 24 2489076647 ps
T382 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3436118203 Jul 28 05:11:50 PM PDT 24 Jul 28 05:11:57 PM PDT 24 2390981971 ps
T255 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4201576656 Jul 28 05:13:09 PM PDT 24 Jul 28 05:13:12 PM PDT 24 3107686194 ps
T261 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.4274970861 Jul 28 05:12:35 PM PDT 24 Jul 28 05:12:42 PM PDT 24 2476951214 ps
T326 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1081395656 Jul 28 05:12:16 PM PDT 24 Jul 28 05:13:36 PM PDT 24 67237058765 ps
T128 /workspace/coverage/default/32.sysrst_ctrl_stress_all.3673474390 Jul 28 05:12:49 PM PDT 24 Jul 28 05:12:58 PM PDT 24 14096913341 ps
T150 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2904044764 Jul 28 05:13:05 PM PDT 24 Jul 28 05:13:07 PM PDT 24 2563867508 ps
T119 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1343055219 Jul 28 05:12:09 PM PDT 24 Jul 28 05:12:16 PM PDT 24 7778472061 ps
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T164 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.4047989327 Jul 28 05:13:15 PM PDT 24 Jul 28 05:13:18 PM PDT 24 2922897381 ps
T165 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2556853336 Jul 28 05:13:11 PM PDT 24 Jul 28 05:13:15 PM PDT 24 2480470733 ps
T158 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2788317687 Jul 28 05:13:11 PM PDT 24 Jul 28 05:15:51 PM PDT 24 64630679586 ps
T88 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.127540043 Jul 28 05:12:21 PM PDT 24 Jul 28 05:12:44 PM PDT 24 30449943476 ps
T79 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2023715795 Jul 28 05:13:08 PM PDT 24 Jul 28 05:13:11 PM PDT 24 3350173402 ps
T166 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1581480077 Jul 28 05:11:57 PM PDT 24 Jul 28 05:13:01 PM PDT 24 21203675556 ps
T201 /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.431211780 Jul 28 05:12:40 PM PDT 24 Jul 28 05:12:44 PM PDT 24 2476305403 ps
T202 /workspace/coverage/default/12.sysrst_ctrl_smoke.2133523482 Jul 28 05:12:16 PM PDT 24 Jul 28 05:12:18 PM PDT 24 2136563687 ps
T203 /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.2191084830 Jul 28 05:12:55 PM PDT 24 Jul 28 05:12:56 PM PDT 24 2136014706 ps
T204 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1569250110 Jul 28 05:12:53 PM PDT 24 Jul 28 05:13:10 PM PDT 24 4705088407 ps
T89 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.3729181956 Jul 28 05:13:10 PM PDT 24 Jul 28 05:18:24 PM PDT 24 115564028921 ps
T157 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1382648264 Jul 28 05:12:32 PM PDT 24 Jul 28 05:12:46 PM PDT 24 93466617548 ps
T263 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1864754240 Jul 28 05:12:23 PM PDT 24 Jul 28 05:12:26 PM PDT 24 2541399228 ps
T75 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2081632283 Jul 28 05:11:56 PM PDT 24 Jul 28 05:13:50 PM PDT 24 428256978571 ps
T274 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2816454564 Jul 28 05:12:01 PM PDT 24 Jul 28 05:12:03 PM PDT 24 2417313030 ps
T90 /workspace/coverage/default/4.sysrst_ctrl_combo_detect.3268391874 Jul 28 05:12:18 PM PDT 24 Jul 28 05:15:18 PM PDT 24 70087071543 ps
T275 /workspace/coverage/default/15.sysrst_ctrl_alert_test.4085387377 Jul 28 05:12:10 PM PDT 24 Jul 28 05:12:11 PM PDT 24 2054946032 ps
T276 /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1133439700 Jul 28 05:13:05 PM PDT 24 Jul 28 05:13:10 PM PDT 24 2632008073 ps
T91 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.2093243120 Jul 28 05:12:42 PM PDT 24 Jul 28 05:14:00 PM PDT 24 114729298907 ps
T277 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2152518332 Jul 28 05:12:32 PM PDT 24 Jul 28 05:12:34 PM PDT 24 2264321707 ps
T278 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1128899753 Jul 28 05:12:47 PM PDT 24 Jul 28 05:12:54 PM PDT 24 2614062931 ps
T105 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.344179371 Jul 28 05:12:53 PM PDT 24 Jul 28 05:15:17 PM PDT 24 55307523815 ps
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T417 /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1242165619 Jul 28 05:13:07 PM PDT 24 Jul 28 05:13:10 PM PDT 24 3449588855 ps
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T420 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3674957263 Jul 28 05:12:28 PM PDT 24 Jul 28 05:12:36 PM PDT 24 2598482602 ps
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