Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1312

1

T7

11

T8

1

T44

13

auto[1]

1815

1

T7

15

T8

2

T43

10

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2545

1

T7

19

T8

3

T44

13

auto[1]

582

1

T7

7

T41

1

T42

3

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2939

1

T7

20

T8

3

T44

13

auto[1]

188

1

T7

6

T32

2

T33

6

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2982

1

T7

26

T8

2

T44

13

auto[1]

145

1

T8

1

T34

1

T33

3

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2950

1

T7

26

T8

3

T44

13

auto[1]

177

1

T35

5

T32

1

T36

1

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1954

1

T7

6

T8

2

T44

13

auto[1]

1173

1

T7

20

T8

1

T41

9

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1326

1

T7

11

T8

1

T44

2

auto[1]

1801

1

T7

15

T8

2

T44

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1357

1

T7

8

T8

1

T44

2

auto[1]

1770

1

T7

18

T8

2

T44

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1366

1

T7

10

T8

1

T44

13

auto[1]

1761

1

T7

16

T8

2

T43

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1301

1

T7

9

T8

1

T44

3

auto[1]

1826

1

T7

17

T8

2

T44

10

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

66

1

T44

1

T43

1

T35

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T7

1

T364

1

T365

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T43

1

T41

1

T33

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T366

2

T263

1

T367

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T43

1

T42

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T98

1

T99

1

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T43

1

T45

2

T261

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T125

3

T258

1

T368

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

31

1

T43

1

T261

1

T259

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T8

1

T98

2

T254

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T35

2

T32

1

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T7

1

T35

3

T124

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T35

1

T32

2

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T33

1

T254

1

T364

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

35

1

T35

3

T125

2

T364

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T7

1

T35

1

T125

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T44

1

T43

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T99

1

T263

2

T202

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T43

1

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T98

1

T368

1

T264

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T43

1

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T7

2

T99

2

T368

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T43

1

T34

1

T261

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T7

2

T125

1

T99

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T43

1

T32

2

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T7

2

T124

1

T99

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T32

1

T33

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T124

1

T254

2

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T32

1

T260

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T98

1

T99

1

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T43

1

T41

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

56

1

T41

8

T253

7

T98

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T42

1

T35

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T255

1

T366

1

T369

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T35

2

T34

2

T260

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T7

1

T124

2

T99

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T44

1

T43

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T124

2

T364

1

T367

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T43

1

T42

1

T124

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T42

3

T99

1

T101

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T45

2

T260

1

T261

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T7

1

T366

2

T368

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T35

1

T34

2

T36

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T35

5

T33

1

T124

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T7

1

T43

1

T42

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

33

1

T45

3

T99

2

T369

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50

1

T32

2

T45

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35

1

T45

1

T124

1

T98

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T44

1

T45

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T364

1

T370

1

T366

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

89

1

T43

1

T32

2

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T99

1

T364

1

T101

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T44

9

T43

2

T42

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T7

1

T42

6

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T8

1

T34

2

T36

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T7

1

T124

1

T99

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T32

1

T36

3

T260

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T264

1

T331

1

T272

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

58

1

T43

3

T32

1

T33

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T33

7

T256

9

T371

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T45

1

T34

1

T97

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T45

5

T255

3

T364

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

281

1

T7

5

T8

1

T32

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T98

1

T99

2

T364

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T98

1

T370

1

T202

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T7

1

T372

1

T373

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T367

1

T331

1

T374

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T374

1

T375

1

T212

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T367

1

T202

1

T376

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T35

2

T98

1

T365

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T33

1

T124

1

T377

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T364

1

T367

1

T212

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T366

1

T263

1

T264

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T124

1

T370

1

T366

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T98

1

T378

2

T379

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T263

1

T365

1

T374

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T98

1

T254

3

T364

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T7

1

T254

1

T380

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T331

1

T381

1

T378

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T41

1

T253

2

T98

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T366

1

T264

1

T272

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T382

1

T383

2

T272

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T42

1

T124

1

T370

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T258

1

T370

1

T382

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T264

1

T365

1

T272

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T35

2

T124

2

T382

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T7

1

T45

3

T98

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T98

1

T366

1

T86

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T98

1

T370

1

T212

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T124

1

T368

1

T374

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T7

1

T42

2

T212

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T98

1

T366

2

T264

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T7

1

T364

1

T370

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T370

1

T264

1

T331

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T45

3

T124

1

T159

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

143

1

T7

2

T124

7

T98

1

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

77

1

T44

1

T43

1

T35

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T98

1

T364

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T43

1

T41

1

T33

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T7

1

T366

2

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T43

1

T42

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T98

1

T99

1

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T43

1

T45

2

T260

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T125

3

T258

1

T368

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T43

1

T261

1

T266

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T8

1

T98

2

T254

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T35

2

T32

1

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T7

1

T35

5

T124

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T35

1

T32

2

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T33

2

T124

1

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T35

3

T125

2

T364

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T35

1

T125

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T44

1

T43

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T99

1

T366

1

T263

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T43

1

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T124

1

T98

1

T370

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T43

1

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T7

2

T98

1

T99

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T43

1

T34

1

T261

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T7

2

T125

1

T99

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T43

1

T32

2

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

38

1

T7

2

T124

1

T98

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T32

1

T33

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T7

1

T124

1

T254

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T32

1

T260

3

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T98

1

T99

1

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

81

1

T43

1

T41

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

67

1

T41

9

T253

9

T98

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T42

1

T35

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T255

1

T366

2

T369

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T35

2

T34

2

T260

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T7

1

T124

2

T99

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T44

1

T43

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T42

1

T124

3

T364

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T43

1

T42

1

T124

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T42

3

T99

1

T101

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T45

2

T260

3

T261

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T366

2

T368

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T35

1

T34

2

T36

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

56

1

T35

7

T33

1

T124

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T7

1

T43

1

T42

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T7

1

T45

6

T98

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T32

2

T45

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T45

1

T124

1

T98

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T44

1

T45

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T98

1

T364

1

T370

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

86

1

T43

1

T32

2

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T124

1

T99

1

T364

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T44

9

T43

2

T42

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

43

1

T7

2

T42

8

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T8

1

T34

2

T36

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T7

1

T124

1

T98

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T32

2

T36

3

T260

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T7

1

T364

1

T370

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

56

1

T43

3

T32

1

T33

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T33

7

T370

1

T256

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T45

1

T34

1

T97

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T45

8

T124

1

T255

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

167

1

T8

1

T34

1

T64

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

141

1

T7

1

T124

7

T98

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T384

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T7

1

T364

1

T370

2

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

77

1

T44

1

T43

1

T35

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T98

1

T364

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T43

1

T41

1

T33

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T7

1

T366

2

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T43

1

T42

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T98

1

T99

1

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T43

1

T45

2

T260

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T125

3

T258

1

T368

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T43

1

T261

1

T266

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T8

1

T98

2

T254

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T35

2

T32

1

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T7

1

T35

5

T124

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T35

1

T32

2

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T33

1

T124

1

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T35

3

T125

2

T364

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T35

1

T125

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T44

1

T43

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T99

1

T366

1

T263

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T43

1

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T124

1

T98

1

T370

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T43

1

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T7

2

T98

1

T99

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T43

1

T34

1

T261

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T7

2

T125

1

T99

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T43

1

T32

2

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

38

1

T7

2

T124

1

T98

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T32

1

T33

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T7

1

T124

1

T254

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T32

1

T260

3

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T98

1

T99

1

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

72

1

T43

1

T41

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

67

1

T41

9

T253

9

T98

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T42

1

T35

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T255

1

T366

2

T369

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T35

2

T34

2

T260

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T7

1

T124

2

T99

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T44

1

T43

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T42

1

T124

3

T364

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T43

1

T42

1

T124

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T42

3

T99

1

T101

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T45

2

T260

3

T261

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T366

2

T368

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T35

1

T34

2

T36

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

56

1

T35

7

T33

1

T124

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T7

1

T43

1

T42

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T7

1

T45

6

T98

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T32

2

T45

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T45

1

T124

1

T98

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T44

1

T45

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T98

1

T364

1

T370

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

92

1

T43

1

T32

2

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T124

1

T99

1

T364

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T44

9

T43

2

T42

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

43

1

T7

2

T42

8

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T8

1

T34

2

T36

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T7

1

T124

1

T98

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T32

2

T36

3

T260

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T7

1

T364

1

T370

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T43

3

T32

1

T33

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T33

7

T370

1

T256

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T45

1

T34

1

T97

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T45

8

T124

1

T255

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

197

1

T7

5

T32

2

T260

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

144

1

T7

2

T124

7

T98

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T372

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T33

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T258

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T264

2

T272

4

T374

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

77

1

T44

1

T43

1

T35

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T98

1

T364

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T43

1

T41

1

T33

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T7

1

T366

2

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T43

1

T42

1

T35

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T98

1

T99

1

T263

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

61

1

T43

1

T45

2

T260

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T125

3

T258

1

T368

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T43

1

T261

1

T266

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T8

1

T98

2

T254

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T35

1

T32

1

T34

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T7

1

T35

3

T124

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T35

1

T32

2

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T33

2

T124

1

T254

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

33

1

T35

1

T125

1

T364

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T7

1

T35

1

T125

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T44

1

T43

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T99

1

T366

1

T263

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T43

1

T34

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T124

1

T98

1

T370

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T43

1

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T7

2

T98

1

T99

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

67

1

T43

1

T34

1

T261

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T7

2

T125

1

T99

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T43

1

T32

2

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T7

2

T124

1

T98

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T32

1

T33

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T7

1

T124

1

T254

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T32

1

T260

3

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T98

1

T99

1

T364

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T43

1

T41

1

T34

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

66

1

T41

9

T253

9

T98

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T42

1

T35

1

T34

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T255

1

T366

2

T369

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T35

2

T34

2

T260

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T7

1

T124

2

T99

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T44

1

T43

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T42

1

T124

3

T364

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

48

1

T43

1

T42

1

T124

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

42

1

T42

3

T99

1

T101

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T45

2

T260

3

T261

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T7

1

T366

2

T368

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T35

1

T34

2

T36

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

56

1

T35

7

T33

1

T124

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T7

1

T43

1

T42

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T7

1

T45

6

T98

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50

1

T32

2

T45

1

T34

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T45

1

T124

1

T98

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T44

1

T45

1

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T98

1

T364

1

T370

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

87

1

T43

1

T32

2

T34

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T124

1

T99

1

T364

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T44

9

T43

2

T42

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

43

1

T7

2

T42

8

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T8

1

T34

2

T36

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T7

1

T124

1

T98

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T32

2

T36

2

T260

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T7

1

T364

1

T370

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T43

3

T32

1

T33

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

41

1

T33

7

T370

1

T256

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T45

1

T34

1

T97

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T45

8

T124

1

T255

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

186

1

T7

5

T8

1

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

131

1

T7

2

T124

7

T98

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T35

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T254

3

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T385

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T364

4

T370

7

T374

2

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded