Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1347

1

T2

8

T7

17

T9

7

auto[1]

1508

1

T2

16

T7

5

T9

18

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2361

1

T2

20

T7

22

T9

20

auto[1]

494

1

T2

4

T9

5

T31

1

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2693

1

T2

24

T7

19

T9

25

auto[1]

162

1

T7

3

T10

4

T11

1

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2738

1

T2

24

T7

22

T9

20

auto[1]

117

1

T9

5

T10

4

T11

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2714

1

T2

20

T7

21

T9

25

auto[1]

141

1

T2

4

T7

1

T32

2

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1653

1

T2

5

T7

22

T9

25

auto[1]

1202

1

T2

19

T31

9

T32

25

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1174

1

T2

11

T7

5

T9

12

auto[1]

1681

1

T2

13

T7

17

T9

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T2

9

T7

22

T9

9

auto[1]

1713

1

T2

15

T9

16

T10

19

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T2

13

T7

12

T9

13

auto[1]

1716

1

T2

11

T7

10

T9

12

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1219

1

T2

14

T7

10

T9

11

auto[1]

1636

1

T2

10

T7

12

T9

14

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T7

1

T9

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T92

1

T266

2

T310

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T7

1

T9

2

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T2

2

T32

2

T211

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T7

1

T9

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T2

1

T32

1

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T31

1

T41

1

T238

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T2

1

T93

1

T311

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T10

2

T11

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T2

1

T21

1

T211

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T10

1

T41

2

T114

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T211

1

T93

1

T156

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T7

2

T21

1

T114

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T2

1

T32

1

T211

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T9

1

T10

1

T238

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T93

1

T37

1

T266

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T9

1

T38

1

T188

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T311

1

T156

2

T312

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T11

1

T38

1

T238

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T2

2

T211

1

T212

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T9

1

T10

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T211

1

T212

2

T266

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T10

1

T209

2

T214

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T2

1

T113

4

T211

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T10

3

T31

1

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T32

1

T212

1

T37

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T9

1

T10

2

T11

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T211

1

T93

1

T311

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T9

1

T31

1

T41

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T2

1

T31

3

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T9

1

T10

4

T41

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

31

1

T41

5

T212

1

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T7

5

T9

1

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T2

1

T31

2

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T7

1

T31

1

T38

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T2

1

T211

1

T212

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T38

1

T114

1

T188

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

25

1

T211

1

T92

2

T208

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T7

3

T11

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T31

1

T32

1

T211

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T7

2

T31

1

T114

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T32

1

T93

2

T266

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T11

1

T38

2

T114

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T32

1

T92

1

T93

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T7

6

T38

1

T91

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

48

1

T93

2

T156

1

T96

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T91

1

T178

3

T169

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T32

1

T92

1

T311

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T2

1

T10

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T211

1

T212

2

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23

1

T9

2

T214

2

T172

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

43

1

T2

1

T211

1

T92

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

36

1

T38

1

T238

1

T91

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T32

1

T21

1

T212

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T9

1

T11

8

T78

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

46

1

T78

9

T113

3

T211

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

69

1

T10

7

T238

2

T188

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T2

1

T31

2

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T9

1

T11

1

T238

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T266

1

T313

4

T310

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

73

1

T41

3

T38

2

T114

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

78

1

T32

1

T41

2

T69

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

204

1

T2

4

T9

5

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T2

1

T21

1

T211

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T32

1

T266

1

T314

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T2

1

T190

1

T315

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T21

1

T266

1

T190

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T316

1

T314

1

T317

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T212

1

T314

1

T317

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T32

1

T318

1

T319

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T314

1

T319

1

T317

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T32

1

T316

1

T317

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T93

1

T310

3

T190

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T212

1

T93

1

T215

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T113

1

T311

1

T316

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T32

1

T316

1

T320

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T31

1

T314

1

T319

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T212

1

T266

1

T210

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T190

2

T321

2

T322

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T210

1

T216

1

T323

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T212

1

T311

1

T266

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T156

1

T324

1

T317

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T92

1

T95

1

T325

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T190

1

T318

1

T325

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T312

3

T314

1

T216

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T211

1

T92

1

T311

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T314

1

T318

1

T317

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T32

1

T319

1

T216

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T92

1

T326

1

T317

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T2

1

T212

1

T316

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T93

1

T314

1

T320

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T113

1

T211

2

T212

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T2

1

T266

1

T312

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T2

1

T266

2

T156

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T32

1

T311

1

T208

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

150

1

T32

6

T21

2

T211

2

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	23	73	76.04	23
Automatically Generated Cross Bins	96	23	73	76.04	23
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T7

1

T9

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T32

1

T92

1

T266

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T7

1

T9

2

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T2

3

T32

2

T211

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T7

1

T9

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T2

1

T32

1

T21

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T9

1

T31

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T2

1

T93

1

T311

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T10

1

T11

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T21

1

T211

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T10

1

T41

2

T114

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T32

1

T211

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T7

2

T21

1

T114

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T2

1

T32

1

T211

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43

1

T9

1

T10

1

T238

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T32

1

T93

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

35

1

T9

1

T38

1

T188

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T93

1

T311

1

T156

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36

1

T11

1

T38

1

T238

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T2

2

T211

1

T212

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T9

1

T10

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T211

1

T212

2

T311

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T9

1

T10

1

T209

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T2

1

T32

1

T113

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T10

2

T31

1

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T32

1

T212

1

T37

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

64

1

T9

1

T10

2

T11

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T211

1

T212

1

T93

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T9

1

T31

1

T41

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

47

1

T2

1

T31

3

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T9

1

T10

4

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T41

5

T212

1

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T7

3

T9

1

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T2

1

T31

2

T212

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T7

1

T9

1

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T2

1

T211

1

T212

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T38

1

T114

1

T188

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T211

1

T92

3

T208

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T7

2

T11

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T31

1

T32

1

T211

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T7

2

T31

1

T114

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T32

1

T93

2

T266

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T11

1

T38

2

T114

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T32

1

T211

1

T92

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T7

6

T38

1

T91

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T93

2

T156

1

T96

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

42

1

T9

1

T91

1

T178

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T32

2

T92

1

T311

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T2

1

T10

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T211

1

T212

2

T92

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23

1

T9

2

T38

1

T188

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

53

1

T2

2

T211

1

T212

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T38

1

T114

1

T238

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T32

1

T21

1

T212

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T9

1

T11

7

T78

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

59

1

T78

9

T113

4

T211

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

71

1

T9

1

T10

5

T238

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T2

2

T31

2

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T9

1

T11

1

T238

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

42

1

T2

1

T266

3

T156

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

68

1

T41

3

T38

3

T114

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

90

1

T32

2

T41

2

T69

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

129

1

T2

4

T9

5

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

154

1

T2

1

T32

6

T21

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T327

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T328

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T113

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T31

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T321

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T329

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T326

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T326

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T316

2

T190

1

T319

2

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T7

1

T9

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T32

1

T92

1

T266

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T7

1

T9

2

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T2

3

T32

2

T211

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T7

1

T9

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T2

1

T32

1

T21

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T9

1

T31

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T2

1

T93

1

T311

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T10

1

T11

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T21

1

T211

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T10

1

T41

2

T114

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T32

1

T211

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T7

2

T21

1

T114

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T2

1

T32

1

T211

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T9

1

T10

1

T238

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T32

1

T93

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

36

1

T9

1

T38

1

T188

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T93

1

T311

1

T156

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36

1

T11

1

T38

1

T238

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T2

2

T211

1

T212

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T9

1

T10

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T113

1

T211

1

T212

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T9

1

T10

1

T209

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T2

1

T32

1

T113

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T10

2

T31

1

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T31

1

T32

1

T212

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T9

1

T10

2

T11

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T211

1

T212

1

T93

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T9

1

T31

1

T41

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

48

1

T2

1

T31

3

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

46

1

T9

1

T10

4

T41

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T41

5

T212

1

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T7

5

T9

1

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T2

1

T31

2

T212

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T7

1

T9

1

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T2

1

T211

1

T212

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T38

1

T114

1

T188

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T211

1

T92

3

T208

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T7

3

T11

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T31

1

T32

1

T211

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T7

2

T31

1

T114

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T93

2

T266

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T11

1

T38

2

T114

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T32

1

T211

1

T92

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T7

6

T38

1

T91

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T93

2

T156

1

T96

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

45

1

T9

1

T91

1

T178

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T32

2

T92

1

T311

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T2

1

T10

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T211

1

T212

2

T92

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

25

1

T9

2

T38

1

T188

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

53

1

T2

2

T211

1

T212

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T38

1

T114

1

T238

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T32

1

T21

1

T212

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T9

1

T11

8

T78

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

59

1

T78

9

T113

4

T211

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

71

1

T9

1

T10

5

T238

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T2

2

T31

2

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T9

1

T238

1

T204

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T2

1

T266

3

T156

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

73

1

T41

3

T38

3

T114

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

92

1

T32

2

T41

2

T69

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

134

1

T2

4

T32

1

T38

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

163

1

T2

1

T32

6

T21

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T313

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T318

3

T232

1

-

-

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	26	70	72.92	26
Automatically Generated Cross Bins	96	26	70	72.92	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T7

1

T9

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T32

1

T92

1

T266

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T7

1

T9

2

T11

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T2

3

T32

2

T211

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T7

1

T9

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T2

1

T32

1

T21

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T9

1

T31

1

T41

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T2

1

T93

1

T311

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T10

2

T11

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T21

1

T211

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T10

1

T41

2

T114

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T32

1

T211

1

T93

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

53

1

T7

2

T21

1

T114

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T2

1

T32

1

T211

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43

1

T9

1

T10

1

T238

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T32

1

T93

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

36

1

T9

1

T38

1

T188

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T93

1

T311

1

T156

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36

1

T11

1

T38

1

T238

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T2

2

T211

1

T212

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T9

1

T10

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T113

1

T211

1

T212

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T9

1

T10

1

T209

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T2

1

T32

1

T113

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T10

3

T31

1

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T31

1

T32

1

T212

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

56

1

T9

1

T10

2

T11

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T211

1

T212

1

T93

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T9

1

T31

1

T41

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

47

1

T2

1

T31

3

T32

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

46

1

T9

1

T10

4

T41

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T41

5

T212

1

T37

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T7

5

T9

1

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T2

1

T31

2

T212

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T7

1

T9

1

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T2

1

T211

1

T212

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T38

1

T114

1

T188

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T211

1

T92

3

T208

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T7

3

T11

1

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T31

1

T32

1

T211

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T7

1

T31

1

T114

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T93

2

T266

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T11

1

T38

2

T114

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T32

1

T211

1

T92

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T7

6

T38

1

T91

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T93

2

T156

1

T96

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

40

1

T9

1

T91

1

T178

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T32

2

T92

1

T311

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T2

1

T10

1

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T211

1

T212

2

T92

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

22

1

T9

2

T38

1

T188

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

53

1

T2

2

T211

1

T212

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T38

1

T114

1

T238

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T32

1

T21

1

T212

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T9

1

T11

8

T78

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

59

1

T78

9

T113

4

T211

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T9

1

T10

7

T238

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T2

2

T31

2

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T9

1

T11

1

T238

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

42

1

T2

1

T266

3

T156

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

74

1

T41

2

T38

3

T114

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

92

1

T32

2

T41

2

T69

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

137

1

T9

5

T38

1

T114

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

145

1

T2

1

T32

5

T21

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T328

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T321

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T325

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T325

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T326

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

22

1

T32

1

T211

1

T210

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded