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Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer

Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 211 1 T244 1 T245 3 T246 1
auto[1] 332 1 T3 1 T4 1 T12 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 239 1 T244 2 T245 1 T246 2
auto[1] 327 1 T1 1 T12 1 T21 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 229 1 T244 2 T245 1 T354 3
auto[1] 259 1 T4 1 T8 1 T12 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 228 1 T244 2 T245 1 T354 5
auto[1] 349 1 T3 1 T4 1 T12 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 225 1 T244 1 T245 2 T246 2
auto[1] 288 1 T1 1 T3 1 T4 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 182 1 T244 1 T245 3 T246 1
auto[1] 301 1 T3 1 T4 1 T12 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 201 1 T244 1 T246 2 T354 4
auto[1] 282 1 T3 1 T33 1 T44 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 273 1 T245 2 T246 1 T354 4
auto[1] 358 1 T3 1 T4 1 T33 3


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 247 1 T244 1 T245 2 T246 2
auto[1] 328 1 T3 1 T4 1 T33 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 291 1 T244 1 T245 5 T257 1
auto[1] 494 1 T30 1 T244 9 T360 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 191 1 T244 1 T245 4 T359 1
auto[1] 2265 1 T22 20 T23 37 T24 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 210 1 T245 3 T246 1 T354 1
auto[1] 2255 1 T22 19 T23 40 T24 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 262 1 T244 1 T245 3 T359 1
auto[1] 2334 1 T22 18 T23 40 T24 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 229 1 T244 1 T245 3 T246 3
auto[1] 2259 1 T22 20 T23 39 T24 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 269 1 T244 2 T245 6 T246 1
auto[1] 2299 1 T22 20 T23 39 T24 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 184 1 T245 6 T246 1 T354 2
auto[1] 2262 1 T22 20 T23 34 T24 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 241 1 T244 2 T245 3 T359 1
auto[1] 2268 1 T22 20 T23 35 T24 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 229 1 T244 1 T245 5 T359 1
auto[1] 2326 1 T22 17 T23 37 T24 17


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 208 1 T244 1 T245 3 T359 1
auto[1] 2254 1 T22 17 T23 40 T24 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 198 1 T244 2 T245 1 T359 1
auto[1] 2296 1 T22 20 T23 40 T24 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 232 1 T244 2 T245 5 T246 2
auto[1] 2296 1 T22 20 T23 40 T24 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 219 1 T244 1 T245 3 T246 3
auto[1] 2280 1 T22 20 T23 38 T24 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 249 1 T244 1 T245 3 T359 1
auto[1] 2206 1 T14 20 T59 17 T66 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 173 1 T245 3 T359 1 T246 1
auto[1] 2232 1 T14 20 T59 16 T66 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 237 1 T244 1 T245 3 T359 1
auto[1] 2215 1 T14 19 T59 20 T66 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 180 1 T244 1 T245 1 T246 1
auto[1] 2185 1 T14 19 T59 20 T66 14


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 192 1 T245 2 T359 1 T246 3
auto[1] 2131 1 T14 20 T59 20 T66 16


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 133 1 T246 2 T354 2 T292 8
auto[1] 2214 1 T14 19 T59 13 T66 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 235 1 T244 1 T245 2 T359 1
auto[1] 2238 1 T14 20 T59 20 T66 17


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 188 1 T245 4 T359 1 T246 1
auto[1] 2190 1 T14 19 T59 18 T66 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 219 1 T245 1 T246 1 T354 1
auto[1] 2179 1 T14 19 T59 18 T66 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 186 1 T244 1 T245 1 T359 1
auto[1] 2098 1 T14 20 T59 16 T66 19


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 219 1 T244 1 T245 3 T359 1
auto[1] 2118 1 T14 20 T59 19 T66 16


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 172 1 T244 1 T245 3 T246 3
auto[1] 2185 1 T14 20 T59 19 T66 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 220 1 T244 1 T245 2 T359 1
auto[1] 2137 1 T14 19 T59 19 T66 16


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 199 1 T245 2 T354 3 T292 8
auto[1] 2236 1 T14 19 T59 20 T66 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 203 1 T245 1 T359 1 T246 2
auto[1] 2181 1 T14 17 T59 20 T66 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 168 1 T244 1 T245 3 T359 1
auto[1] 2148 1 T14 19 T59 19 T66 18


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333 1 T244 1 T245 7 T246 2
auto[1] 536 1 T19 3 T20 1 T21 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 349 1 T244 3 T245 7 T359 1
auto[1] 547 1 T19 3 T20 1 T21 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 294 1 T244 2 T245 6 T359 1
auto[1] 628 1 T19 3 T20 1 T21 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%