Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1284

1

T1

4

T3

11

T6

3

auto[1]

1885

1

T1

4

T3

6

T6

3

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2752

1

T1

6

T3

17

T6

6

auto[1]

417

1

T1

2

T7

3

T8

6

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3026

1

T1

8

T3

15

T6

6

auto[1]

143

1

T3

2

T7

3

T11

3

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3000

1

T1

8

T3

17

T6

5

auto[1]

169

1

T6

1

T8

4

T30

3

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3016

1

T1

8

T3

17

T6

4

auto[1]

153

1

T6

2

T8

3

T10

6

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1998

1

T1

1

T3

17

T6

5

auto[1]

1171

1

T1

7

T6

1

T7

19

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1280

1

T1

3

T3

12

T6

2

auto[1]

1889

1

T1

5

T3

5

T6

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1333

1

T1

4

T3

4

T6

1

auto[1]

1836

1

T1

4

T3

13

T6

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1320

1

T1

2

T3

6

T6

3

auto[1]

1849

1

T1

6

T3

11

T6

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1373

1

T1

4

T3

6

T6

3

auto[1]

1796

1

T1

4

T3

11

T6

3

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T3

1

T10

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

25

1

T7

1

T11

2

T77

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T3

1

T30

4

T44

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T8

1

T11

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T3

1

T10

2

T307

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T7

1

T75

1

T314

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T8

1

T10

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T8

1

T77

1

T33

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T7

1

T44

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T11

1

T30

2

T307

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T1

1

T7

1

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T312

1

T32

2

T304

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T11

2

T44

1

T75

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

42

1

T76

1

T53

1

T305

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T8

2

T44

1

T75

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T3

1

T10

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T6

1

T8

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T44

1

T75

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T10

2

T111

1

T77

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T6

1

T10

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T10

3

T75

2

T82

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T3

1

T10

2

T307

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T1

1

T11

1

T44

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T8

1

T44

1

T111

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T3

2

T10

8

T307

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T7

1

T10

1

T75

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

61

1

T3

5

T75

1

T307

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

86

1

T111

1

T64

9

T314

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T3

1

T6

1

T46

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T11

2

T75

1

T111

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T47

2

T32

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T44

1

T77

1

T314

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T30

3

T46

2

T47

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T8

1

T11

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T30

1

T307

1

T76

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T7

1

T8

1

T30

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T1

1

T7

1

T307

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T7

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

67

1

T30

2

T47

2

T62

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

56

1

T30

1

T44

1

T62

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T307

2

T46

3

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T8

1

T44

1

T111

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

80

1

T312

1

T62

4

T305

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

77

1

T1

1

T7

1

T11

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T3

1

T10

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T1

1

T7

2

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T307

1

T46

2

T47

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T7

2

T8

1

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T307

1

T47

4

T312

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

34

1

T7

1

T75

1

T111

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

85

1

T307

1

T46

6

T62

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

42

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T6

1

T76

1

T53

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T44

1

T75

1

T111

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

86

1

T307

1

T47

20

T62

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

54

1

T44

1

T80

1

T83

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

77

1

T3

3

T32

1

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

51

1

T75

1

T111

2

T77

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

236

1

T6

2

T7

3

T8

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T7

2

T8

1

T11

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T11

1

T314

1

T149

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T378

1

T379

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T7

1

T77

1

T314

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T44

1

T380

1

T309

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T33

1

T317

1

T378

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T172

2

T178

1

T381

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T1

1

T8

1

T382

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T322

1

T149

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T10

1

T33

1

T82

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T172

1

T380

1

T322

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T10

1

T11

1

T77

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T10

3

T33

2

T172

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T44

1

T314

1

T199

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T8

3

T381

1

T380

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T8

1

T11

2

T172

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T44

1

T172

1

T382

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T11

1

T44

1

T111

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T382

1

T322

1

T137

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T33

1

T383

1

T322

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T30

4

T77

1

T322

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T33

1

T309

1

T384

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T8

1

T314

1

T305

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T33

1

T178

1

T385

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T381

1

T380

1

T386

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T7

1

T322

2

T387

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T322

1

T388

3

T137

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T111

2

T314

1

T172

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T322

1

T389

1

T243

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T7

1

T304

2

T390

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T11

1

T44

1

T380

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T11

1

T314

1

T391

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

92

1

T1

1

T11

4

T111

3

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T3

1

T10

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T7

1

T11

3

T77

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T3

1

T30

4

T44

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T8

1

T11

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T3

1

T10

2

T307

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T7

2

T75

1

T77

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T8

1

T10

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T8

1

T44

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T7

1

T44

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T11

1

T30

2

T307

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T1

1

T7

1

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T312

1

T32

3

T304

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T1

1

T8

1

T11

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T76

1

T53

1

T305

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T8

2

T44

1

T75

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T3

1

T10

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T6

1

T8

1

T10

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T44

1

T75

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T10

3

T11

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

48

1

T6

1

T10

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T10

6

T75

2

T33

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T10

2

T307

1

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T1

1

T11

1

T44

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T8

4

T44

1

T111

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T3

2

T10

8

T307

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T7

1

T8

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

66

1

T3

5

T75

1

T307

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

96

1

T44

1

T111

1

T64

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T3

1

T6

1

T46

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T11

3

T44

1

T75

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T47

2

T32

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T44

1

T77

1

T314

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T30

3

T46

2

T47

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T8

1

T11

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T30

1

T307

1

T312

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T7

1

T8

1

T30

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T1

1

T7

1

T307

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T7

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T30

2

T47

2

T62

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

71

1

T8

1

T30

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T307

2

T46

2

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T8

1

T44

1

T111

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

80

1

T312

1

T62

4

T305

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

83

1

T1

1

T7

1

T11

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T3

1

T10

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T1

1

T7

3

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T307

1

T46

2

T47

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T7

2

T8

1

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T307

1

T47

4

T312

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T7

1

T75

1

T111

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

79

1

T307

1

T46

6

T62

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

50

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T6

1

T76

1

T53

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T7

1

T44

1

T75

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

86

1

T307

1

T47

20

T62

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T11

1

T44

2

T80

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

75

1

T3

2

T32

1

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

59

1

T11

1

T75

1

T111

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

163

1

T6

2

T8

6

T11

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

87

1

T1

1

T7

2

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T392

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T393

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T304

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

25

1

T11

3

T111

1

T314

5

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T3

1

T10

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T7

1

T11

3

T77

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T3

1

T30

2

T44

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T8

1

T11

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T3

1

T10

2

T307

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T7

2

T75

1

T77

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T8

1

T10

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T8

1

T44

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T7

1

T44

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T11

1

T30

1

T307

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T1

1

T7

1

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T312

1

T32

3

T304

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T1

1

T8

1

T11

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T76

1

T53

1

T305

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T8

2

T44

1

T75

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T3

1

T10

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T6

1

T8

1

T10

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T44

1

T75

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T10

3

T11

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T6

1

T10

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T10

6

T75

2

T33

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T3

1

T10

2

T307

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T1

1

T11

1

T44

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T8

4

T44

1

T111

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

69

1

T3

2

T10

8

T307

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T7

1

T8

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

63

1

T3

5

T75

1

T307

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

96

1

T44

1

T111

1

T64

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T3

1

T6

1

T46

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T11

3

T44

1

T75

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T47

2

T32

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T44

1

T77

1

T314

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T30

3

T46

2

T47

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T8

1

T11

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T30

1

T307

1

T312

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T7

1

T8

1

T30

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T1

1

T7

1

T307

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T7

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

64

1

T30

2

T47

2

T32

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

70

1

T8

1

T30

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T307

2

T46

3

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T8

1

T44

1

T111

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

80

1

T312

1

T62

4

T298

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

83

1

T1

1

T7

1

T11

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T3

1

T10

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T1

1

T7

3

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T307

1

T46

2

T47

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T7

2

T8

1

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T307

1

T47

4

T312

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T7

1

T75

1

T111

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

85

1

T307

1

T46

6

T62

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

50

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T6

1

T76

1

T53

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T7

1

T44

1

T75

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

82

1

T307

1

T47

20

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T11

1

T44

2

T80

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T3

3

T32

1

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

59

1

T11

1

T75

1

T111

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

144

1

T6

1

T7

3

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

104

1

T1

1

T7

2

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T394

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T395

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T305

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T388

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T33

5

T380

1

T137

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T3

1

T10

1

T30

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T7

1

T11

3

T77

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T3

1

T30

4

T44

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T8

1

T11

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T3

1

T10

2

T307

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T7

2

T75

1

T77

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T8

1

T10

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T8

1

T44

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T7

1

T44

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T11

1

T30

2

T307

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T1

1

T7

1

T111

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T312

1

T32

3

T304

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T1

1

T8

1

T11

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

44

1

T76

1

T53

1

T305

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T8

2

T44

1

T75

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T3

1

T10

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T6

1

T8

1

T10

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T10

2

T47

1

T312

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T44

1

T75

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T10

3

T11

1

T111

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T6

1

T10

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T10

6

T75

2

T33

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T3

1

T10

2

T307

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T1

1

T11

1

T44

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T307

1

T47

2

T62

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T8

4

T44

1

T111

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

63

1

T3

2

T10

2

T307

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T7

1

T8

1

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T3

5

T75

1

T307

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

96

1

T44

1

T111

1

T64

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T3

1

T6

1

T46

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T11

3

T44

1

T75

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T47

2

T32

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T44

1

T77

1

T314

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T30

3

T46

2

T47

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T8

1

T11

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T30

1

T307

1

T312

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T7

1

T8

1

T30

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T1

1

T7

1

T307

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T7

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T30

2

T47

2

T62

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

70

1

T8

1

T30

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T307

2

T46

3

T76

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T8

1

T44

1

T111

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

83

1

T312

1

T62

2

T305

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

83

1

T1

1

T7

1

T11

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T3

1

T10

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T1

1

T7

3

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T307

1

T46

2

T47

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T7

2

T8

1

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T307

1

T47

4

T312

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T7

1

T75

1

T111

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

82

1

T307

1

T46

6

T62

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

49

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T6

1

T76

1

T53

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T7

1

T44

1

T75

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

73

1

T307

1

T47

8

T62

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

62

1

T11

1

T44

2

T80

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

76

1

T3

3

T32

1

T76

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

59

1

T11

1

T75

1

T111

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

180

1

T7

3

T8

3

T44

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

96

1

T1

1

T7

2

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T386

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T396

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T390

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T11

3

T381

3

T380

2

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded