Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.38	99.51	96.46	100.00	99.36	99.00	99.90	94.43

Total tests in report: 916

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
63.29	63.29	85.52	85.52	72.57	72.57	62.79	62.79	53.85	53.85	86.14	86.14	77.94	77.94	4.21	4.21	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.5450836
82.09	18.81	94.68	9.16	87.97	15.39	92.92	30.14	80.13	26.28	94.49	8.35	92.29	14.35	32.18	27.97	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2434241952
85.85	3.75	97.03	2.35	90.90	2.93	97.03	4.11	82.05	1.92	96.78	2.29	93.55	1.25	43.59	11.41	/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2725703754
88.66	2.82	97.22	0.19	91.08	0.18	97.03	0.00	82.69	0.64	96.86	0.07	93.83	0.29	61.93	18.35	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3538938392
91.04	2.37	98.17	0.95	92.26	1.19	97.03	0.00	88.46	5.77	97.56	0.70	95.95	2.12	67.82	5.89	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.406200014
92.44	1.40	98.25	0.07	93.55	1.29	97.72	0.68	88.46	0.00	97.67	0.11	96.15	0.19	75.29	7.47	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.851331564
93.50	1.06	98.58	0.34	94.08	0.53	98.17	0.46	91.03	2.56	97.97	0.30	97.11	0.96	77.55	2.26	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3200544359
94.16	0.66	98.62	0.04	94.08	0.00	98.17	0.00	91.03	0.00	97.97	0.00	97.11	0.00	82.12	4.57	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2928404676
94.59	0.43	98.73	0.11	94.19	0.10	98.17	0.00	92.95	1.92	98.08	0.11	97.50	0.39	82.49	0.37	/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1754977717
95.00	0.42	98.88	0.15	94.36	0.18	98.17	0.00	94.87	1.92	98.26	0.18	97.98	0.48	82.49	0.00	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.613887007
95.30	0.29	98.90	0.02	94.41	0.05	98.17	0.00	94.87	0.00	98.26	0.00	98.07	0.10	84.38	1.89	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.4230939727
95.54	0.25	98.99	0.09	94.46	0.05	98.17	0.00	96.15	1.28	98.37	0.11	98.27	0.19	84.38	0.00	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1823896198
95.79	0.25	99.09	0.09	94.51	0.05	98.17	0.00	97.44	1.28	98.48	0.11	98.46	0.19	84.38	0.00	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3729919681
96.03	0.24	99.14	0.06	94.59	0.08	99.54	1.37	97.44	0.00	98.48	0.00	98.46	0.00	84.54	0.16	/workspace/coverage/default/0.sysrst_ctrl_alert_test.2547024495
96.22	0.19	99.14	0.00	94.59	0.00	99.54	0.00	97.44	0.00	98.48	0.00	98.46	0.00	85.86	1.31	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.1252367054
96.40	0.19	99.16	0.02	94.64	0.05	99.54	0.00	97.44	0.00	98.52	0.04	98.55	0.10	86.96	1.10	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2038234511
96.58	0.17	99.22	0.06	94.64	0.00	99.54	0.00	97.44	0.00	98.52	0.00	98.55	0.00	88.12	1.16	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2957577619
96.71	0.14	99.29	0.07	94.67	0.03	99.54	0.00	98.08	0.64	98.63	0.11	98.65	0.10	88.12	0.00	/workspace/coverage/default/12.sysrst_ctrl_edge_detect.2679269490
96.84	0.13	99.29	0.00	94.77	0.10	99.54	0.00	98.08	0.00	98.63	0.00	99.42	0.77	88.17	0.05	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2284839711
96.97	0.13	99.29	0.00	95.53	0.76	99.54	0.00	98.08	0.00	98.63	0.00	99.42	0.00	88.33	0.16	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1060834061
97.10	0.13	99.29	0.00	95.55	0.03	99.54	0.00	98.08	0.00	98.63	0.00	99.52	0.10	89.12	0.79	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.2008271301
97.23	0.13	99.35	0.06	95.58	0.03	99.54	0.00	98.72	0.64	98.71	0.07	99.61	0.10	89.12	0.00	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3285612195
97.35	0.12	99.38	0.04	95.60	0.03	99.54	0.00	99.36	0.64	98.74	0.04	99.71	0.10	89.12	0.00	/workspace/coverage/default/15.sysrst_ctrl_edge_detect.2022273588
97.45	0.10	99.38	0.00	95.60	0.00	99.54	0.00	99.36	0.00	98.74	0.00	99.71	0.00	89.80	0.68	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2836452591
97.55	0.10	99.38	0.00	95.63	0.03	100.00	0.46	99.36	0.00	98.74	0.00	99.81	0.10	89.91	0.11	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.2780648005
97.62	0.08	99.38	0.00	95.65	0.03	100.00	0.00	99.36	0.00	98.74	0.00	99.90	0.10	90.33	0.42	/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.433532659
97.70	0.08	99.38	0.00	95.65	0.00	100.00	0.00	99.36	0.00	98.74	0.00	99.90	0.00	90.85	0.53	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.74062453
97.77	0.07	99.38	0.00	95.65	0.00	100.00	0.00	99.36	0.00	98.74	0.00	99.90	0.00	91.32	0.47	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3833791861
97.83	0.06	99.38	0.00	95.65	0.00	100.00	0.00	99.36	0.00	98.74	0.00	99.90	0.00	91.75	0.42	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.1702728084
97.88	0.05	99.38	0.00	95.65	0.00	100.00	0.00	99.36	0.00	98.74	0.00	99.90	0.00	92.11	0.37	/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.141887086
97.93	0.05	99.38	0.00	95.96	0.30	100.00	0.00	99.36	0.00	98.74	0.00	99.90	0.00	92.17	0.05	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3508282043
97.97	0.04	99.42	0.04	96.11	0.15	100.00	0.00	99.36	0.00	98.82	0.07	99.90	0.00	92.17	0.00	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2763987476
98.01	0.04	99.42	0.00	96.11	0.00	100.00	0.00	99.36	0.00	98.82	0.00	99.90	0.00	92.43	0.26	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.1432710451
98.04	0.03	99.42	0.00	96.33	0.23	100.00	0.00	99.36	0.00	98.82	0.00	99.90	0.00	92.43	0.00	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2505617700
98.06	0.02	99.48	0.06	96.33	0.00	100.00	0.00	99.36	0.00	98.93	0.11	99.90	0.00	92.43	0.00	/workspace/coverage/default/13.sysrst_ctrl_stress_all.4254128419
98.08	0.02	99.48	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.59	0.16	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2240239436
98.11	0.02	99.48	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.74	0.16	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.4195242721
98.13	0.02	99.48	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	92.90	0.16	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.3074327026
98.15	0.02	99.48	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	93.06	0.16	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2901585600
98.17	0.02	99.48	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.93	0.00	99.90	0.00	93.22	0.16	/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1984503379
98.19	0.02	99.50	0.02	96.33	0.00	100.00	0.00	99.36	0.00	98.96	0.04	99.90	0.00	93.27	0.05	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4005229634
98.20	0.02	99.50	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.96	0.00	99.90	0.00	93.38	0.11	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.4140741510
98.22	0.02	99.50	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.96	0.00	99.90	0.00	93.48	0.11	/workspace/coverage/default/34.sysrst_ctrl_combo_detect.1329001933
98.23	0.02	99.50	0.00	96.33	0.00	100.00	0.00	99.36	0.00	98.96	0.00	99.90	0.00	93.59	0.11	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3875054768
98.24	0.01	99.51	0.02	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.04	99.90	0.00	93.59	0.00	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.2521058679
98.25	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	93.64	0.05	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3833670472
98.26	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	93.69	0.05	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.2036146522
98.27	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	93.74	0.05	/workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1161880984
98.27	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	93.80	0.05	/workspace/coverage/default/15.sysrst_ctrl_combo_detect.1632564222
98.28	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	93.85	0.05	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3182132790
98.29	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	93.90	0.05	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1381046497
98.30	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	93.95	0.05	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2159434103
98.30	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.01	0.05	/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2432531646
98.31	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.06	0.05	/workspace/coverage/default/31.sysrst_ctrl_combo_detect.3696548770
98.32	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.11	0.05	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2422683649
98.33	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.16	0.05	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.84557436
98.33	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.22	0.05	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1565616126
98.34	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.27	0.05	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.817004623
98.35	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.32	0.05	/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.241538300
98.36	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.37	0.05	/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3464473330
98.36	0.01	99.51	0.00	96.33	0.00	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.43	0.05	/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.181453464
98.37	0.01	99.51	0.00	96.39	0.05	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.43	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.2041520822
98.37	0.01	99.51	0.00	96.41	0.03	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.43	0.00	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1210809761
98.38	0.01	99.51	0.00	96.44	0.03	100.00	0.00	99.36	0.00	99.00	0.00	99.90	0.00	94.43	0.00	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1124210755

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2416804128
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3367414822
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1580029628
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3813954631
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3160405703
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.93248116
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3937844271
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1276306264
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.375365656
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2901542316
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3129781628
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2772761849
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3547036156
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.247047909
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.530501249
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1327495924
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3391863541
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1797637054
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.867126186
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3702481931
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2458153692
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2859764816
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3941502607
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3124844264
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2478988401
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1005883146
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4289152989
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.872716244
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3679331491
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.781142870
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3736785798
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.491128890
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.739732127
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1890624815
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.204439558
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2154986750
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1206906160
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2442051044
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.876162717
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1686437662
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.647045073
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2050272505
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2264963919
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2315193928
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.4186348175
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.530090146
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3080975361
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.801612477
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1682015183
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1335954760
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1803866652
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1062991646
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1440935639
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.449678319
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3944749789
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3208667183
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2131906989
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.974415608
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/workspace/coverage/default/4.sysrst_ctrl_smoke.185737506
/workspace/coverage/default/4.sysrst_ctrl_stress_all.2471030380
/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.425657497
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2759841102
/workspace/coverage/default/40.sysrst_ctrl_alert_test.3815530470
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1527000994
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2438767196
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4215403653
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.2636336272
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2123980921
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.4207343629
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3685826163
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2206867731
/workspace/coverage/default/40.sysrst_ctrl_smoke.991992978
/workspace/coverage/default/40.sysrst_ctrl_stress_all.1982169243
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.262032929
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3879839227
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3771071466
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.4108831868
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.719847969
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.1001134037
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3902950336
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.89663862
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3962282050
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2406811672
/workspace/coverage/default/41.sysrst_ctrl_smoke.742551884
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2825337028
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.574009361
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.212338249
/workspace/coverage/default/42.sysrst_ctrl_alert_test.544812857
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.863815114
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1485310129
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3608454909
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2501708837
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.964091059
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3091043734
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2158017004
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.2544375258
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.868558263
/workspace/coverage/default/42.sysrst_ctrl_smoke.2462950476
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1383560699
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1656540170
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3746758720
/workspace/coverage/default/43.sysrst_ctrl_alert_test.456204640
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.545934872
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.575679901
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2453821356
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1342277264
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2890566008
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2523226140
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.346097143
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3907710932
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1325494022
/workspace/coverage/default/43.sysrst_ctrl_smoke.3876467638
/workspace/coverage/default/43.sysrst_ctrl_stress_all.430115670
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2353996906
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2915474597
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2105832044
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2291652172
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1936784640
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2873365998
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.561785855
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.609758556
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3346900813
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3458509499
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3979992670
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.4148324460
/workspace/coverage/default/44.sysrst_ctrl_smoke.2872134327
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3327913496
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3332624221
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1441133471
/workspace/coverage/default/45.sysrst_ctrl_alert_test.4032721378
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2627507992
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2596397986
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2713776104
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1629358372
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4175300637
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.878843266
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3598936073
/workspace/coverage/default/45.sysrst_ctrl_smoke.1196332248
/workspace/coverage/default/45.sysrst_ctrl_stress_all.216974603
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3026047451
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3895867011
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.300419523
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2171778460
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.627667299
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.987357623
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3291281364
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3888890723
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.152733668
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2497346714
/workspace/coverage/default/46.sysrst_ctrl_smoke.2971390653
/workspace/coverage/default/46.sysrst_ctrl_stress_all.10772436
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.36581093
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2886117710
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.572146205
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.4149586389
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1047916497
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1338295270
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2891746253
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1371980296
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1070676492
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3326063270
/workspace/coverage/default/47.sysrst_ctrl_smoke.2600307794
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2430324199
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.953285172
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2973803016
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2502006096
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.843163434
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2162407919
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1639240917
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.35034197
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.87246270
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3080555265
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2917409695
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2100929633
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1614841883
/workspace/coverage/default/48.sysrst_ctrl_smoke.2593592831
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3888214154
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4133163101
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2241613677
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2045673250
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.389843630
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3575314385
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.125504484
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3598526781
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.33838994
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4005659392
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3310505888
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1298145727
/workspace/coverage/default/49.sysrst_ctrl_smoke.1518827726
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2185225826
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.4071233024
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1833907555
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3739284139
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2829618727
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3049892675
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3915410075
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.430459604
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3454687326
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3509555673
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3435635247
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2270349016
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.127658899
/workspace/coverage/default/5.sysrst_ctrl_smoke.2334558475
/workspace/coverage/default/5.sysrst_ctrl_stress_all.687472551
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2999601766
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1242706019
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1758779803
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2592329403
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1495429270
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2449938713
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3567064927
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1864146031
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1365169065
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3657738100
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1958967212
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3207222730
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.764573975
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2586470445
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1197188101
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2942067674
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1874508340
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1339533684
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1037475017
/workspace/coverage/default/6.sysrst_ctrl_smoke.2312422579
/workspace/coverage/default/6.sysrst_ctrl_stress_all.2566481738
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2292834605
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3081392843
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1212464444
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2444889412
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3608098977
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2857700392
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.730807041
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4216505426
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.206119100
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3171042746
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2875576895
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3806424618
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.747684454
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3559532218
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2824514428
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3909644574
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2850573162
/workspace/coverage/default/7.sysrst_ctrl_smoke.4216433456
/workspace/coverage/default/7.sysrst_ctrl_stress_all.892039341
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1369529411
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.4221234431
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3944453199
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3887029738
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.519132905
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2350317953
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1146031884
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1190564619
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2118510468
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1565603302
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.266177740
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3584219866
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1650644182
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.921491896
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1862987861
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1926585199
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1610412107
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3133910006
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2437927051
/workspace/coverage/default/8.sysrst_ctrl_smoke.1398827354
/workspace/coverage/default/8.sysrst_ctrl_stress_all.167893576
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1288489074
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3710151341
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.794144093
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.689588727
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2820726074
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.642130827
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.616754179
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3144335644
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3215207188
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.842496507
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1060090391
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2113216091
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1863461019
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3893366567
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.888012096
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.836494310
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1203285822
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3279284163
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1851868167
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.84465882
/workspace/coverage/default/9.sysrst_ctrl_smoke.4212639534
/workspace/coverage/default/9.sysrst_ctrl_stress_all.3381159914
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3678607650
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3056579734
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3343967297
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3304325004
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4034817335
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2888296703
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2995689388
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.274367733
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2599276102
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.977679312
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1856760856
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2598559123

Total test records in report: 916

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2725703754	Jul 31 07:32:10 PM PDT 24	Jul 31 07:34:02 PM PDT 24	47423588131 ps
T4	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.5450836	Jul 31 07:31:25 PM PDT 24	Jul 31 07:32:59 PM PDT 24	36006202987 ps
T5	/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.2679534408	Jul 31 07:31:28 PM PDT 24	Jul 31 07:31:35 PM PDT 24	2049146751 ps
T13	/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2891746253	Jul 31 07:33:46 PM PDT 24	Jul 31 07:33:48 PM PDT 24	2639068839 ps
T14	/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3150176758	Jul 31 07:33:20 PM PDT 24	Jul 31 07:33:23 PM PDT 24	3646445278 ps
T15	/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.868558263	Jul 31 07:33:33 PM PDT 24	Jul 31 07:33:40 PM PDT 24	2511114238 ps
T16	/workspace/coverage/default/12.sysrst_ctrl_alert_test.3346637525	Jul 31 07:32:03 PM PDT 24	Jul 31 07:32:06 PM PDT 24	2028415795 ps
T17	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2341500821	Jul 31 07:33:16 PM PDT 24	Jul 31 07:33:18 PM PDT 24	2182330837 ps
T18	/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3468473599	Jul 31 07:32:42 PM PDT 24	Jul 31 07:32:46 PM PDT 24	2179576163 ps
T19	/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2910805712	Jul 31 07:32:50 PM PDT 24	Jul 31 07:32:58 PM PDT 24	3167476642 ps
T48	/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2406811672	Jul 31 07:33:35 PM PDT 24	Jul 31 07:33:38 PM PDT 24	2533255624 ps
T39	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1573524454	Jul 31 07:31:33 PM PDT 24	Jul 31 07:31:42 PM PDT 24	3594165836 ps
T40	/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3602200971	Jul 31 07:32:52 PM PDT 24	Jul 31 07:33:00 PM PDT 24	3200064560 ps
T2	/workspace/coverage/default/24.sysrst_ctrl_edge_detect.1736014685	Jul 31 07:32:36 PM PDT 24	Jul 31 07:32:43 PM PDT 24	3161923280 ps
T206	/workspace/coverage/default/21.sysrst_ctrl_alert_test.1467945142	Jul 31 07:32:28 PM PDT 24	Jul 31 07:32:30 PM PDT 24	2024595750 ps
T3	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.4230939727	Jul 31 07:32:04 PM PDT 24	Jul 31 07:32:56 PM PDT 24	74597346440 ps
T41	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2917692014	Jul 31 07:32:05 PM PDT 24	Jul 31 07:32:13 PM PDT 24	2901332354 ps
T42	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.4143810989	Jul 31 07:32:58 PM PDT 24	Jul 31 07:33:07 PM PDT 24	3243566769 ps
T59	/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.2372990066	Jul 31 07:33:07 PM PDT 24	Jul 31 07:33:09 PM PDT 24	2551170033 ps
T110	/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3685826163	Jul 31 07:33:24 PM PDT 24	Jul 31 07:33:30 PM PDT 24	2105415338 ps
T6	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3200544359	Jul 31 07:31:49 PM PDT 24	Jul 31 07:33:28 PM PDT 24	72601809403 ps
T60	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.4140741510	Jul 31 07:32:11 PM PDT 24	Jul 31 07:32:16 PM PDT 24	2511873788 ps
T43	/workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1741031485	Jul 31 07:31:19 PM PDT 24	Jul 31 07:32:13 PM PDT 24	204048451992 ps
T25	/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2437927051	Jul 31 07:31:50 PM PDT 24	Jul 31 07:31:57 PM PDT 24	2509803653 ps
T61	/workspace/coverage/default/20.sysrst_ctrl_stress_all.2039034904	Jul 31 07:32:33 PM PDT 24	Jul 31 07:32:41 PM PDT 24	10999624867 ps
T145	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2870686666	Jul 31 07:32:54 PM PDT 24	Jul 31 07:32:55 PM PDT 24	2131979059 ps
T24	/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1644807216	Jul 31 07:32:57 PM PDT 24	Jul 31 07:32:59 PM PDT 24	2493434668 ps
T7	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2434241952	Jul 31 07:33:52 PM PDT 24	Jul 31 07:35:51 PM PDT 24	1476469321892 ps
T8	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.3634517628	Jul 31 07:32:02 PM PDT 24	Jul 31 07:37:02 PM PDT 24	123754804677 ps
T9	/workspace/coverage/default/1.sysrst_ctrl_stress_all.3006435032	Jul 31 07:31:26 PM PDT 24	Jul 31 07:31:52 PM PDT 24	14440711228 ps
T50	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1497574268	Jul 31 07:32:30 PM PDT 24	Jul 31 07:32:38 PM PDT 24	5609156685 ps
T93	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2672021421	Jul 31 07:32:49 PM PDT 24	Jul 31 07:32:57 PM PDT 24	2611422995 ps
T94	/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.878843266	Jul 31 07:33:41 PM PDT 24	Jul 31 07:33:47 PM PDT 24	2194890280 ps
T95	/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2312315095	Jul 31 07:31:24 PM PDT 24	Jul 31 07:31:28 PM PDT 24	2516450558 ps
T10	/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2599276102	Jul 31 07:34:09 PM PDT 24	Jul 31 07:40:44 PM PDT 24	168206926583 ps
T11	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.2008271301	Jul 31 07:32:50 PM PDT 24	Jul 31 07:33:05 PM PDT 24	111585151681 ps
T96	/workspace/coverage/default/46.sysrst_ctrl_smoke.2971390653	Jul 31 07:33:50 PM PDT 24	Jul 31 07:33:51 PM PDT 24	2230807484 ps
T12	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.1976155038	Jul 31 07:32:46 PM PDT 24	Jul 31 07:33:01 PM PDT 24	5411053940 ps
T180	/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.719847969	Jul 31 07:33:31 PM PDT 24	Jul 31 07:34:54 PM PDT 24	455399193259 ps
T319	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1851868167	Jul 31 07:31:55 PM PDT 24	Jul 31 07:31:57 PM PDT 24	2111148256 ps
T320	/workspace/coverage/default/49.sysrst_ctrl_alert_test.2241613677	Jul 31 07:33:57 PM PDT 24	Jul 31 07:34:00 PM PDT 24	2025978933 ps
T74	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2875576895	Jul 31 07:31:50 PM PDT 24	Jul 31 07:31:59 PM PDT 24	3309045220 ps
T31	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2038234511	Jul 31 07:32:37 PM PDT 24	Jul 31 07:33:08 PM PDT 24	48229194182 ps
T30	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2836452591	Jul 31 07:33:12 PM PDT 24	Jul 31 07:34:06 PM PDT 24	81457257003 ps
T23	/workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.519958492	Jul 31 07:32:35 PM PDT 24	Jul 31 07:34:04 PM PDT 24	36672587650 ps
T44	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.1252367054	Jul 31 07:31:24 PM PDT 24	Jul 31 07:35:28 PM PDT 24	93440737483 ps
T106	/workspace/coverage/default/11.sysrst_ctrl_alert_test.2129566604	Jul 31 07:31:54 PM PDT 24	Jul 31 07:31:56 PM PDT 24	2028005423 ps
T55	/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.4286596838	Jul 31 07:33:16 PM PDT 24	Jul 31 07:33:17 PM PDT 24	2524013090 ps
T107	/workspace/coverage/default/8.sysrst_ctrl_alert_test.1565603302	Jul 31 07:31:47 PM PDT 24	Jul 31 07:31:50 PM PDT 24	2020260844 ps
T108	/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.746314877	Jul 31 07:32:58 PM PDT 24	Jul 31 07:33:05 PM PDT 24	2602334665 ps
T109	/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1298145727	Jul 31 07:33:57 PM PDT 24	Jul 31 07:34:00 PM PDT 24	2525531762 ps
T56	/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3458509499	Jul 31 07:33:37 PM PDT 24	Jul 31 07:33:44 PM PDT 24	2479630958 ps
T57	/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3418044732	Jul 31 07:32:53 PM PDT 24	Jul 31 07:32:57 PM PDT 24	2451223861 ps
T310	/workspace/coverage/default/1.sysrst_ctrl_smoke.2207769461	Jul 31 07:31:17 PM PDT 24	Jul 31 07:31:23 PM PDT 24	2108838970 ps
T311	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1339533684	Jul 31 07:31:41 PM PDT 24	Jul 31 07:31:47 PM PDT 24	2110992322 ps
T424	/workspace/coverage/default/43.sysrst_ctrl_smoke.3876467638	Jul 31 07:33:31 PM PDT 24	Jul 31 07:33:33 PM PDT 24	2135014723 ps
T75	/workspace/coverage/default/36.sysrst_ctrl_stress_all.3955960414	Jul 31 07:33:18 PM PDT 24	Jul 31 07:36:06 PM PDT 24	69024683764 ps
T425	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.260878103	Jul 31 07:32:22 PM PDT 24	Jul 31 07:32:29 PM PDT 24	2609657590 ps
T426	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.100642695	Jul 31 07:33:13 PM PDT 24	Jul 31 07:33:20 PM PDT 24	2148647102 ps
T45	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1183994880	Jul 31 07:31:25 PM PDT 24	Jul 31 07:31:32 PM PDT 24	2284304992 ps
T427	/workspace/coverage/default/22.sysrst_ctrl_smoke.1934665109	Jul 31 07:32:31 PM PDT 24	Jul 31 07:32:33 PM PDT 24	2130256882 ps
T29	/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1242706019	Jul 31 07:31:40 PM PDT 24	Jul 31 07:31:44 PM PDT 24	3162736891 ps
T428	/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.4103758803	Jul 31 07:32:02 PM PDT 24	Jul 31 07:32:03 PM PDT 24	3675617379 ps
T51	/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.262032929	Jul 31 07:33:30 PM PDT 24	Jul 31 07:33:34 PM PDT 24	6971726252 ps
T422	/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.4235086147	Jul 31 07:31:40 PM PDT 24	Jul 31 07:31:47 PM PDT 24	2509268833 ps
T58	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.400938198	Jul 31 07:32:18 PM PDT 24	Jul 31 07:32:23 PM PDT 24	2455734501 ps
T36	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3538938392	Jul 31 07:33:00 PM PDT 24	Jul 31 07:35:02 PM PDT 24	194157673720 ps
T37	/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1862987861	Jul 31 07:31:50 PM PDT 24	Jul 31 07:31:57 PM PDT 24	2741202873 ps
T307	/workspace/coverage/default/38.sysrst_ctrl_combo_detect.711207310	Jul 31 07:33:22 PM PDT 24	Jul 31 07:35:20 PM PDT 24	61180554605 ps
T429	/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.439024179	Jul 31 07:32:02 PM PDT 24	Jul 31 07:32:04 PM PDT 24	2139309875 ps
T46	/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1146031884	Jul 31 07:34:03 PM PDT 24	Jul 31 07:34:42 PM PDT 24	76566532998 ps
T423	/workspace/coverage/default/3.sysrst_ctrl_stress_all.1174575478	Jul 31 07:31:36 PM PDT 24	Jul 31 07:32:10 PM PDT 24	14294166494 ps
T354	/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2359511555	Jul 31 07:32:50 PM PDT 24	Jul 31 07:32:55 PM PDT 24	2516166060 ps
T47	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2928404676	Jul 31 07:32:01 PM PDT 24	Jul 31 07:46:08 PM PDT 24	315831428259 ps
T111	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.3238642466	Jul 31 07:33:13 PM PDT 24	Jul 31 07:34:42 PM PDT 24	45627371788 ps
T312	/workspace/coverage/default/25.sysrst_ctrl_combo_detect.2720186781	Jul 31 07:32:36 PM PDT 24	Jul 31 07:34:03 PM PDT 24	143367608523 ps
T355	/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2850573162	Jul 31 07:31:50 PM PDT 24	Jul 31 07:31:57 PM PDT 24	2507177735 ps
T430	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3558097420	Jul 31 07:32:02 PM PDT 24	Jul 31 07:32:05 PM PDT 24	2098908133 ps
T431	/workspace/coverage/default/19.sysrst_ctrl_alert_test.1628798436	Jul 31 07:32:21 PM PDT 24	Jul 31 07:32:26 PM PDT 24	2011509660 ps
T432	/workspace/coverage/default/0.sysrst_ctrl_stress_all.3723020633	Jul 31 07:31:25 PM PDT 24	Jul 31 07:31:30 PM PDT 24	6598215217 ps
T62	/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3887029738	Jul 31 07:34:00 PM PDT 24	Jul 31 07:35:39 PM PDT 24	165704692991 ps
T433	/workspace/coverage/default/44.sysrst_ctrl_alert_test.2105832044	Jul 31 07:33:38 PM PDT 24	Jul 31 07:33:41 PM PDT 24	2017972836 ps
T434	/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.864530903	Jul 31 07:33:16 PM PDT 24	Jul 31 07:33:19 PM PDT 24	2840404010 ps
T52	/workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.222770128	Jul 31 07:31:35 PM PDT 24	Jul 31 07:31:44 PM PDT 24	10474750418 ps
T435	/workspace/coverage/default/0.sysrst_ctrl_alert_test.2547024495	Jul 31 07:31:16 PM PDT 24	Jul 31 07:31:18 PM PDT 24	2035907241 ps
T436	/workspace/coverage/default/20.sysrst_ctrl_alert_test.4003793261	Jul 31 07:32:28 PM PDT 24	Jul 31 07:32:33 PM PDT 24	2012260300 ps
T437	/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.708845752	Jul 31 07:32:11 PM PDT 24	Jul 31 07:32:14 PM PDT 24	4122530628 ps
T32	/workspace/coverage/default/24.sysrst_ctrl_stress_all.3710355012	Jul 31 07:32:39 PM PDT 24	Jul 31 07:40:03 PM PDT 24	171018175451 ps
T185	/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4175300637	Jul 31 07:33:36 PM PDT 24	Jul 31 07:33:38 PM PDT 24	2498952146 ps
T186	/workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3001948141	Jul 31 07:32:10 PM PDT 24	Jul 31 07:32:16 PM PDT 24	3519766830 ps
T38	/workspace/coverage/default/45.sysrst_ctrl_stress_all.216974603	Jul 31 07:33:47 PM PDT 24	Jul 31 07:34:21 PM PDT 24	14429805415 ps
T187	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1629358372	Jul 31 07:33:40 PM PDT 24	Jul 31 07:33:41 PM PDT 24	2701855229 ps
T188	/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.1658444500	Jul 31 07:32:39 PM PDT 24	Jul 31 07:32:41 PM PDT 24	2036707868 ps
T189	/workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3662452565	Jul 31 07:32:18 PM PDT 24	Jul 31 07:32:21 PM PDT 24	3174952339 ps
T190	/workspace/coverage/default/34.sysrst_ctrl_alert_test.1410192611	Jul 31 07:33:07 PM PDT 24	Jul 31 07:33:10 PM PDT 24	2025752797 ps
T191	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.365238178	Jul 31 07:32:06 PM PDT 24	Jul 31 07:32:07 PM PDT 24	2681339029 ps
T192	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.4063337854	Jul 31 07:32:32 PM PDT 24	Jul 31 07:32:35 PM PDT 24	2479720542 ps
T438	/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2100929633	Jul 31 07:33:52 PM PDT 24	Jul 31 07:33:59 PM PDT 24	2172532965 ps
T76	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.3685675103	Jul 31 07:32:28 PM PDT 24	Jul 31 07:32:33 PM PDT 24	34221019160 ps
T63	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3056671248	Jul 31 07:32:37 PM PDT 24	Jul 31 07:34:00 PM PDT 24	37678631878 ps
T53	/workspace/coverage/default/15.sysrst_ctrl_stress_all.2206650978	Jul 31 07:32:11 PM PDT 24	Jul 31 07:33:46 PM PDT 24	148464359157 ps
T128	/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.152733668	Jul 31 07:33:54 PM PDT 24	Jul 31 07:33:55 PM PDT 24	2264000584 ps
T129	/workspace/coverage/default/6.sysrst_ctrl_smoke.2312422579	Jul 31 07:31:49 PM PDT 24	Jul 31 07:31:52 PM PDT 24	2116346279 ps
T130	/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1386575816	Jul 31 07:32:58 PM PDT 24	Jul 31 07:33:04 PM PDT 24	2089138278 ps
T131	/workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.2527610772	Jul 31 07:32:44 PM PDT 24	Jul 31 07:32:52 PM PDT 24	2468014244 ps
T132	/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.84465882	Jul 31 07:31:54 PM PDT 24	Jul 31 07:31:57 PM PDT 24	2537405772 ps
T54	/workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1369224238	Jul 31 07:32:30 PM PDT 24	Jul 31 07:32:36 PM PDT 24	2972197406 ps
T77	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3584219866	Jul 31 07:31:49 PM PDT 24	Jul 31 07:38:53 PM PDT 24	176741769927 ps
T133	/workspace/coverage/default/46.sysrst_ctrl_alert_test.3895867011	Jul 31 07:33:46 PM PDT 24	Jul 31 07:33:52 PM PDT 24	2013181370 ps
T66	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1346905785	Jul 31 07:32:46 PM PDT 24	Jul 31 07:32:55 PM PDT 24	9089239373 ps
T324	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.786114473	Jul 31 07:31:40 PM PDT 24	Jul 31 07:32:08 PM PDT 24	42096891245 ps
T64	/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1495429270	Jul 31 07:34:01 PM PDT 24	Jul 31 07:34:09 PM PDT 24	40939121714 ps
T344	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.797627971	Jul 31 07:32:52 PM PDT 24	Jul 31 07:40:18 PM PDT 24	217128807212 ps
T345	/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3909644574	Jul 31 07:31:51 PM PDT 24	Jul 31 07:31:52 PM PDT 24	2158673165 ps
T346	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3435635247	Jul 31 07:31:42 PM PDT 24	Jul 31 07:31:48 PM PDT 24	2450899399 ps
T73	/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2552678032	Jul 31 07:32:10 PM PDT 24	Jul 31 07:32:13 PM PDT 24	4502176001 ps
T65	/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3944453199	Jul 31 07:34:03 PM PDT 24	Jul 31 07:36:22 PM PDT 24	51744482541 ps
T314	/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3049892675	Jul 31 07:31:40 PM PDT 24	Jul 31 07:35:36 PM PDT 24	101151164344 ps
T347	/workspace/coverage/default/29.sysrst_ctrl_alert_test.2215661085	Jul 31 07:32:53 PM PDT 24	Jul 31 07:32:59 PM PDT 24	2012408065 ps
T112	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.4825983	Jul 31 07:31:58 PM PDT 24	Jul 31 07:32:00 PM PDT 24	9936349476 ps
T113	/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3064225691	Jul 31 07:32:35 PM PDT 24	Jul 31 07:32:36 PM PDT 24	9732093694 ps
T439	/workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.593103321	Jul 31 07:32:11 PM PDT 24	Jul 31 07:32:15 PM PDT 24	2618983220 ps
T33	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.406200014	Jul 31 07:33:30 PM PDT 24	Jul 31 07:34:08 PM PDT 24	255832991475 ps
T253	/workspace/coverage/default/8.sysrst_ctrl_smoke.1398827354	Jul 31 07:31:50 PM PDT 24	Jul 31 07:31:56 PM PDT 24	2109956228 ps
T254	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.591677436	Jul 31 07:32:37 PM PDT 24	Jul 31 07:42:52 PM PDT 24	978673195069 ps
T114	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3508282043	Jul 31 07:32:27 PM PDT 24	Jul 31 07:33:54 PM PDT 24	421049968246 ps
T255	/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2138875015	Jul 31 07:33:22 PM PDT 24	Jul 31 07:33:25 PM PDT 24	3036209713 ps
T256	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2347612404	Jul 31 07:32:35 PM PDT 24	Jul 31 07:32:40 PM PDT 24	2521349596 ps
T257	/workspace/coverage/default/49.sysrst_ctrl_stress_all.2185225826	Jul 31 07:33:53 PM PDT 24	Jul 31 07:34:08 PM PDT 24	9875360527 ps
T258	/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.141887086	Jul 31 07:33:40 PM PDT 24	Jul 31 07:34:46 PM PDT 24	46372268940 ps
T259	/workspace/coverage/default/4.sysrst_ctrl_alert_test.1435255046	Jul 31 07:31:42 PM PDT 24	Jul 31 07:31:47 PM PDT 24	2009635749 ps
T260	/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.4154956278	Jul 31 07:32:34 PM PDT 24	Jul 31 07:32:41 PM PDT 24	2030307103 ps
T304	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3833791861	Jul 31 07:31:16 PM PDT 24	Jul 31 07:33:16 PM PDT 24	189877914520 ps
T440	/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3899735717	Jul 31 07:32:43 PM PDT 24	Jul 31 07:32:45 PM PDT 24	2626024840 ps
T441	/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3559532218	Jul 31 07:31:47 PM PDT 24	Jul 31 07:31:48 PM PDT 24	2737180361 ps
T442	/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2158017004	Jul 31 07:33:40 PM PDT 24	Jul 31 07:33:42 PM PDT 24	2490922527 ps
T443	/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1371346518	Jul 31 07:32:52 PM PDT 24	Jul 31 07:32:58 PM PDT 24	2445830208 ps
T444	/workspace/coverage/default/12.sysrst_ctrl_smoke.2830503451	Jul 31 07:31:53 PM PDT 24	Jul 31 07:31:59 PM PDT 24	2113343244 ps
T445	/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3346900813	Jul 31 07:33:36 PM PDT 24	Jul 31 07:33:44 PM PDT 24	2612394242 ps
T356	/workspace/coverage/default/2.sysrst_ctrl_stress_all.2779890734	Jul 31 07:31:24 PM PDT 24	Jul 31 07:31:41 PM PDT 24	6658507873 ps
T357	/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2859498085	Jul 31 07:32:38 PM PDT 24	Jul 31 07:32:40 PM PDT 24	8528290825 ps
T351	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1685466530	Jul 31 07:32:04 PM PDT 24	Jul 31 07:32:11 PM PDT 24	4623324469 ps
T353	/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3279284163	Jul 31 07:31:59 PM PDT 24	Jul 31 07:32:01 PM PDT 24	2497404687 ps
T446	/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3280780751	Jul 31 07:33:06 PM PDT 24	Jul 31 07:33:12 PM PDT 24	2261719359 ps
T447	/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.325125847	Jul 31 07:31:54 PM PDT 24	Jul 31 07:32:02 PM PDT 24	2957015177 ps
T448	/workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3567712422	Jul 31 07:33:13 PM PDT 24	Jul 31 07:33:16 PM PDT 24	3201126445 ps
T68	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3598526781	Jul 31 07:33:54 PM PDT 24	Jul 31 07:33:59 PM PDT 24	3186097378 ps
T152	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3979992670	Jul 31 07:33:38 PM PDT 24	Jul 31 07:33:41 PM PDT 24	2038787060 ps
T153	/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3190879707	Jul 31 07:33:22 PM PDT 24	Jul 31 07:33:26 PM PDT 24	2515956879 ps
T154	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.4068383269	Jul 31 07:31:27 PM PDT 24	Jul 31 07:31:42 PM PDT 24	22059133830 ps
T155	/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1047916497	Jul 31 07:33:49 PM PDT 24	Jul 31 07:33:52 PM PDT 24	3398215717 ps
T156	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2937872626	Jul 31 07:31:54 PM PDT 24	Jul 31 07:31:57 PM PDT 24	4406812226 ps
T157	/workspace/coverage/default/29.sysrst_ctrl_smoke.2402806039	Jul 31 07:32:51 PM PDT 24	Jul 31 07:32:56 PM PDT 24	2113777465 ps
T158	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2573490255	Jul 31 07:32:03 PM PDT 24	Jul 31 07:32:05 PM PDT 24	2495964652 ps
T159	/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.656640925	Jul 31 07:32:43 PM PDT 24	Jul 31 07:32:45 PM PDT 24	2602960526 ps
T160	/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3902950336	Jul 31 07:33:32 PM PDT 24	Jul 31 07:33:34 PM PDT 24	2627881724 ps
T134	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2581000768	Jul 31 07:32:29 PM PDT 24	Jul 31 07:32:45 PM PDT 24	38791835841 ps
T196	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.4005229634	Jul 31 07:32:00 PM PDT 24	Jul 31 07:32:44 PM PDT 24	70394096546 ps
T150	/workspace/coverage/default/4.sysrst_ctrl_stress_all.2471030380	Jul 31 07:31:41 PM PDT 24	Jul 31 07:32:03 PM PDT 24	12477065543 ps
T34	/workspace/coverage/default/13.sysrst_ctrl_edge_detect.2358099682	Jul 31 07:32:01 PM PDT 24	Jul 31 07:32:07 PM PDT 24	2642315460 ps
T449	/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4151920475	Jul 31 07:31:54 PM PDT 24	Jul 31 07:31:59 PM PDT 24	4185524516 ps
T450	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4253237546	Jul 31 07:32:05 PM PDT 24	Jul 31 07:32:07 PM PDT 24	6151052833 ps
T305	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2957577619	Jul 31 07:34:00 PM PDT 24	Jul 31 07:35:24 PM PDT 24	67965240599 ps
T451	/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1766398415	Jul 31 07:32:57 PM PDT 24	Jul 31 07:33:04 PM PDT 24	2224184918 ps
T452	/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2200660437	Jul 31 07:33:23 PM PDT 24	Jul 31 07:33:29 PM PDT 24	2512689965 ps
T293	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1039478227	Jul 31 07:32:22 PM PDT 24	Jul 31 07:34:30 PM PDT 24	52830249029 ps
T313	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.274367733	Jul 31 07:34:08 PM PDT 24	Jul 31 07:34:31 PM PDT 24	59935344060 ps
T453	/workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1464375024	Jul 31 07:32:13 PM PDT 24	Jul 31 07:32:14 PM PDT 24	3844518122 ps
T454	/workspace/coverage/default/23.sysrst_ctrl_alert_test.1810462805	Jul 31 07:32:47 PM PDT 24	Jul 31 07:32:48 PM PDT 24	2121965010 ps
T455	/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.4287034023	Jul 31 07:33:16 PM PDT 24	Jul 31 07:33:24 PM PDT 24	2854380437 ps
T456	/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3326063270	Jul 31 07:33:55 PM PDT 24	Jul 31 07:33:56 PM PDT 24	2549229577 ps
T457	/workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.4185444190	Jul 31 07:31:27 PM PDT 24	Jul 31 07:31:36 PM PDT 24	3343130947 ps
T78	/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.433532659	Jul 31 07:34:01 PM PDT 24	Jul 31 07:36:06 PM PDT 24	48607581996 ps
T296	/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.157913256	Jul 31 07:32:19 PM PDT 24	Jul 31 07:32:27 PM PDT 24	2510060613 ps
T297	/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1289677600	Jul 31 07:31:54 PM PDT 24	Jul 31 07:32:00 PM PDT 24	2023997099 ps
T35	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2292834605	Jul 31 07:31:46 PM PDT 24	Jul 31 07:32:02 PM PDT 24	28103249867 ps
T298	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3115290573	Jul 31 07:33:22 PM PDT 24	Jul 31 07:34:19 PM PDT 24	87095447541 ps
T299	/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3464473330	Jul 31 07:34:00 PM PDT 24	Jul 31 07:35:12 PM PDT 24	117780649809 ps
T300	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2439128794	Jul 31 07:33:15 PM PDT 24	Jul 31 07:36:53 PM PDT 24	104862628899 ps
T301	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.4271433226	Jul 31 07:32:44 PM PDT 24	Jul 31 07:32:51 PM PDT 24	2473648772 ps
T302	/workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2581983381	Jul 31 07:33:11 PM PDT 24	Jul 31 07:33:19 PM PDT 24	2610009842 ps
T303	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3215207188	Jul 31 07:34:04 PM PDT 24	Jul 31 07:34:52 PM PDT 24	72136569476 ps
T144	/workspace/coverage/default/8.sysrst_ctrl_stress_all.167893576	Jul 31 07:31:56 PM PDT 24	Jul 31 07:32:29 PM PDT 24	125567922014 ps
T79	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3304325004	Jul 31 07:34:09 PM PDT 24	Jul 31 07:34:38 PM PDT 24	24336441044 ps
T458	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1926585199	Jul 31 07:31:56 PM PDT 24	Jul 31 07:32:03 PM PDT 24	2611857671 ps
T166	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.211906654	Jul 31 07:32:28 PM PDT 24	Jul 31 07:32:36 PM PDT 24	3154263256 ps
T408	/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1863461019	Jul 31 07:31:55 PM PDT 24	Jul 31 07:33:57 PM PDT 24	94053062306 ps
T151	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3577575926	Jul 31 07:32:04 PM PDT 24	Jul 31 07:32:06 PM PDT 24	5649533063 ps
T459	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2576214376	Jul 31 07:31:42 PM PDT 24	Jul 31 07:31:49 PM PDT 24	2545597699 ps
T80	/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1856760856	Jul 31 07:34:13 PM PDT 24	Jul 31 07:34:53 PM PDT 24	64511218778 ps
T460	/workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1323794522	Jul 31 07:32:32 PM PDT 24	Jul 31 07:32:34 PM PDT 24	2275232876 ps
T407	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.84557436	Jul 31 07:33:37 PM PDT 24	Jul 31 07:35:32 PM PDT 24	73055601829 ps
T146	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.1922983939	Jul 31 07:32:38 PM PDT 24	Jul 31 07:32:40 PM PDT 24	4146816140 ps
T461	/workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3446337438	Jul 31 07:31:25 PM PDT 24	Jul 31 07:31:29 PM PDT 24	4472004206 ps
T462	/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2497346714	Jul 31 07:33:46 PM PDT 24	Jul 31 07:33:48 PM PDT 24	2526790183 ps
T81	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.268814041	Jul 31 07:32:01 PM PDT 24	Jul 31 07:32:40 PM PDT 24	58752068407 ps
T115	/workspace/coverage/default/43.sysrst_ctrl_stress_all.430115670	Jul 31 07:33:41 PM PDT 24	Jul 31 07:34:13 PM PDT 24	15474486006 ps
T463	/workspace/coverage/default/5.sysrst_ctrl_alert_test.3739284139	Jul 31 07:31:40 PM PDT 24	Jul 31 07:31:43 PM PDT 24	2029377202 ps
T464	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.890533743	Jul 31 07:33:12 PM PDT 24	Jul 31 07:33:15 PM PDT 24	2631583784 ps
T465	/workspace/coverage/default/22.sysrst_ctrl_stress_all.3533145056	Jul 31 07:32:28 PM PDT 24	Jul 31 07:33:02 PM PDT 24	13441047426 ps
T69	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.3666711544	Jul 31 07:32:44 PM PDT 24	Jul 31 07:32:55 PM PDT 24	4986553832 ps
T197	/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.266177740	Jul 31 07:31:50 PM PDT 24	Jul 31 07:32:00 PM PDT 24	3677499070 ps
T198	/workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2477891039	Jul 31 07:33:14 PM PDT 24	Jul 31 07:33:15 PM PDT 24	2902956995 ps
T199	/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.616754179	Jul 31 07:34:04 PM PDT 24	Jul 31 07:35:36 PM PDT 24	34820975523 ps
T200	/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.943664058	Jul 31 07:31:25 PM PDT 24	Jul 31 07:31:28 PM PDT 24	2487163881 ps
T201	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.1203755969	Jul 31 07:32:40 PM PDT 24	Jul 31 07:32:42 PM PDT 24	2757422420 ps
T202	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3782537669	Jul 31 07:32:50 PM PDT 24	Jul 31 07:32:52 PM PDT 24	2210699930 ps
T203	/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.549590553	Jul 31 07:32:58 PM PDT 24	Jul 31 07:33:09 PM PDT 24	4118590955 ps
T204	/workspace/coverage/default/37.sysrst_ctrl_alert_test.1197499329	Jul 31 07:33:16 PM PDT 24	Jul 31 07:33:21 PM PDT 24	2013612924 ps
T205	/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2863532437	Jul 31 07:32:44 PM PDT 24	Jul 31 07:32:46 PM PDT 24	2492111436 ps
T466	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.125336061	Jul 31 07:31:28 PM PDT 24	Jul 31 07:31:31 PM PDT 24	4100384824 ps
T467	/workspace/coverage/default/7.sysrst_ctrl_alert_test.3171042746	Jul 31 07:31:50 PM PDT 24	Jul 31 07:31:51 PM PDT 24	2024058655 ps
T468	/workspace/coverage/default/35.sysrst_ctrl_smoke.831215828	Jul 31 07:33:08 PM PDT 24	Jul 31 07:33:11 PM PDT 24	2120941422 ps
T469	/workspace/coverage/default/4.sysrst_ctrl_smoke.185737506	Jul 31 07:31:35 PM PDT 24	Jul 31 07:31:41 PM PDT 24	2108354337 ps
T470	/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.985689959	Jul 31 07:32:50 PM PDT 24	Jul 31 07:32:52 PM PDT 24	2540011873 ps
T116	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.476603851	Jul 31 07:32:12 PM PDT 24	Jul 31 07:32:13 PM PDT 24	2932093281 ps
T471	/workspace/coverage/default/45.sysrst_ctrl_smoke.1196332248	Jul 31 07:33:39 PM PDT 24	Jul 31 07:33:40 PM PDT 24	2157281292 ps
T472	/workspace/coverage/default/41.sysrst_ctrl_alert_test.3879839227	Jul 31 07:33:32 PM PDT 24	Jul 31 07:33:34 PM PDT 24	2031195962 ps
T473	/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1468674290	Jul 31 07:32:36 PM PDT 24	Jul 31 07:32:38 PM PDT 24	2261438992 ps
T474	/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.2101848048	Jul 31 07:32:29 PM PDT 24	Jul 31 07:45:37 PM PDT 24	327214722553 ps
T475	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.1784958450	Jul 31 07:32:45 PM PDT 24	Jul 31 07:32:47 PM PDT 24	2530745618 ps
T411	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1729266179	Jul 31 07:33:21 PM PDT 24	Jul 31 07:36:01 PM PDT 24	58810457705 ps
T476	/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1986204179	Jul 31 07:33:24 PM PDT 24	Jul 31 07:33:27 PM PDT 24	3225577679 ps
T477	/workspace/coverage/default/13.sysrst_ctrl_alert_test.2019302094	Jul 31 07:32:02 PM PDT 24	Jul 31 07:32:05 PM PDT 24	2022892272 ps
T82	/workspace/coverage/default/24.sysrst_ctrl_combo_detect.1754442426	Jul 31 07:32:47 PM PDT 24	Jul 31 07:37:23 PM PDT 24	106789113238 ps
T478	/workspace/coverage/default/3.sysrst_ctrl_smoke.3948928772	Jul 31 07:31:35 PM PDT 24	Jul 31 07:31:37 PM PDT 24	2124156817 ps
T479	/workspace/coverage/default/19.sysrst_ctrl_stress_all.1956464869	Jul 31 07:32:20 PM PDT 24	Jul 31 07:32:38 PM PDT 24	13214069532 ps
T83	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.3263702286	Jul 31 07:32:46 PM PDT 24	Jul 31 07:32:58 PM PDT 24	20812140616 ps
T480	/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3894695546	Jul 31 07:31:27 PM PDT 24	Jul 31 07:31:37 PM PDT 24	3277182050 ps
T481	/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3776842002	Jul 31 07:33:07 PM PDT 24	Jul 31 07:33:09 PM PDT 24	5680749418 ps
T70	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3285612195	Jul 31 07:33:39 PM PDT 24	Jul 31 07:33:41 PM PDT 24	5182626196 ps
T274	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.3114458180	Jul 31 07:32:10 PM PDT 24	Jul 31 07:33:47 PM PDT 24	35516770148 ps
T275	/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1958967212	Jul 31 07:31:47 PM PDT 24	Jul 31 07:31:52 PM PDT 24	3200588802 ps
T276	/workspace/coverage/default/39.sysrst_ctrl_alert_test.1407100420	Jul 31 07:33:22 PM PDT 24	Jul 31 07:33:27 PM PDT 24	2014914564 ps
T277	/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3888890723	Jul 31 07:33:44 PM PDT 24	Jul 31 07:33:52 PM PDT 24	2447751055 ps
T278	/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.4095824387	Jul 31 07:32:11 PM PDT 24	Jul 31 07:32:15 PM PDT 24	2458938824 ps
T279	/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.33838994	Jul 31 07:33:55 PM PDT 24	Jul 31 07:33:59 PM PDT 24	2617041729 ps
T161	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.58191881	Jul 31 07:33:01 PM PDT 24	Jul 31 07:33:03 PM PDT 24	3824083357 ps
T280	/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1948420360	Jul 31 07:31:56 PM PDT 24	Jul 31 07:32:03 PM PDT 24	2610967078 ps
T281	/workspace/coverage/default/22.sysrst_ctrl_pin_access_test.446939026	Jul 31 07:32:34 PM PDT 24	Jul 31 07:32:37 PM PDT 24	2215098669 ps
T398	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.74062453	Jul 31 07:33:54 PM PDT 24	Jul 31 07:35:39 PM PDT 24	208882679292 ps
T482	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2942067674	Jul 31 07:31:46 PM PDT 24	Jul 31 07:31:49 PM PDT 24	2637229704 ps
T483	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3534952557	Jul 31 07:32:51 PM PDT 24	Jul 31 07:32:58 PM PDT 24	2481857652 ps
T348	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1642096096	Jul 31 07:31:55 PM PDT 24	Jul 31 07:32:24 PM PDT 24	49761997252 ps
T484	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2085979840	Jul 31 07:32:09 PM PDT 24	Jul 31 07:32:18 PM PDT 24	3139021249 ps
T400	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.33832034	Jul 31 07:33:14 PM PDT 24	Jul 31 07:38:04 PM PDT 24	113963553789 ps
T485	/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2400863592	Jul 31 07:31:15 PM PDT 24	Jul 31 07:31:18 PM PDT 24	2544418455 ps
T252	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.617997252	Jul 31 07:32:18 PM PDT 24	Jul 31 07:32:20 PM PDT 24	4933661049 ps
T486	/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4215403653	Jul 31 07:33:23 PM PDT 24	Jul 31 07:33:34 PM PDT 24	4128904558 ps
T487	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2352658928	Jul 31 07:32:07 PM PDT 24	Jul 31 07:33:16 PM PDT 24	26250388718 ps