Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T1 |
13 |
|
T24 |
9 |
|
T7 |
13 |
| auto[1] |
847 |
1 |
|
|
T1 |
7 |
|
T24 |
11 |
|
T7 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T1 |
9 |
|
T24 |
9 |
|
T7 |
9 |
| auto[1] |
866 |
1 |
|
|
T1 |
11 |
|
T24 |
11 |
|
T7 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T1 |
6 |
|
T24 |
10 |
|
T7 |
6 |
| auto[1] |
930 |
1 |
|
|
T1 |
14 |
|
T24 |
10 |
|
T7 |
14 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
881 |
1 |
|
|
T1 |
12 |
|
T24 |
9 |
|
T7 |
9 |
| auto[1] |
879 |
1 |
|
|
T1 |
8 |
|
T24 |
11 |
|
T7 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T1 |
9 |
|
T24 |
11 |
|
T7 |
10 |
| auto[1] |
928 |
1 |
|
|
T1 |
11 |
|
T24 |
9 |
|
T7 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T1 |
11 |
|
T24 |
10 |
|
T7 |
12 |
| auto[1] |
906 |
1 |
|
|
T1 |
9 |
|
T24 |
10 |
|
T7 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T1 |
12 |
|
T24 |
10 |
|
T7 |
11 |
| auto[1] |
843 |
1 |
|
|
T1 |
8 |
|
T24 |
10 |
|
T7 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
856 |
1 |
|
|
T1 |
9 |
|
T24 |
10 |
|
T7 |
13 |
| auto[1] |
904 |
1 |
|
|
T1 |
11 |
|
T24 |
10 |
|
T7 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T1 |
11 |
|
T24 |
12 |
|
T7 |
9 |
| auto[1] |
906 |
1 |
|
|
T1 |
9 |
|
T24 |
8 |
|
T7 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T1 |
15 |
|
T24 |
7 |
|
T7 |
12 |
| auto[1] |
924 |
1 |
|
|
T1 |
5 |
|
T24 |
13 |
|
T7 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T1 |
14 |
|
T24 |
12 |
|
T7 |
10 |
| auto[1] |
888 |
1 |
|
|
T1 |
6 |
|
T24 |
8 |
|
T7 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T1 |
5 |
|
T24 |
9 |
|
T7 |
11 |
| auto[1] |
877 |
1 |
|
|
T1 |
15 |
|
T24 |
11 |
|
T7 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T1 |
11 |
|
T24 |
10 |
|
T7 |
7 |
| auto[1] |
888 |
1 |
|
|
T1 |
9 |
|
T24 |
10 |
|
T7 |
13 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T1 |
9 |
|
T24 |
9 |
|
T7 |
9 |
| auto[1] |
866 |
1 |
|
|
T1 |
11 |
|
T24 |
11 |
|
T7 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T1 |
12 |
|
T24 |
7 |
|
T7 |
6 |
| auto[1] |
861 |
1 |
|
|
T1 |
8 |
|
T24 |
13 |
|
T7 |
14 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T1 |
12 |
|
T24 |
12 |
|
T7 |
5 |
| auto[1] |
888 |
1 |
|
|
T1 |
8 |
|
T24 |
8 |
|
T7 |
15 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T1 |
13 |
|
T24 |
11 |
|
T7 |
11 |
| auto[1] |
889 |
1 |
|
|
T1 |
7 |
|
T24 |
9 |
|
T7 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T1 |
11 |
|
T24 |
12 |
|
T7 |
9 |
| auto[1] |
871 |
1 |
|
|
T1 |
9 |
|
T24 |
8 |
|
T7 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T1 |
10 |
|
T24 |
12 |
|
T7 |
10 |
| auto[1] |
868 |
1 |
|
|
T1 |
10 |
|
T24 |
8 |
|
T7 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T1 |
9 |
|
T24 |
8 |
|
T7 |
8 |
| auto[1] |
937 |
1 |
|
|
T1 |
11 |
|
T24 |
12 |
|
T7 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T1 |
13 |
|
T24 |
10 |
|
T7 |
13 |
| auto[1] |
861 |
1 |
|
|
T1 |
7 |
|
T24 |
10 |
|
T7 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T1 |
8 |
|
T24 |
13 |
|
T7 |
8 |
| auto[1] |
858 |
1 |
|
|
T1 |
12 |
|
T24 |
7 |
|
T7 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T1 |
11 |
|
T24 |
12 |
|
T7 |
10 |
| auto[1] |
876 |
1 |
|
|
T1 |
9 |
|
T24 |
8 |
|
T7 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T1 |
5 |
|
T24 |
9 |
|
T7 |
11 |
| auto[1] |
877 |
1 |
|
|
T1 |
15 |
|
T24 |
11 |
|
T7 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T1 |
4 |
|
T24 |
3 |
|
T7 |
2 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T1 |
8 |
|
T24 |
4 |
|
T7 |
4 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T1 |
2 |
|
T24 |
7 |
|
T7 |
4 |
| auto[1] |
auto[1] |
473 |
1 |
|
|
T1 |
6 |
|
T24 |
6 |
|
T7 |
10 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
454 |
1 |
|
|
T1 |
7 |
|
T24 |
5 |
|
T7 |
3 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T1 |
5 |
|
T24 |
7 |
|
T7 |
2 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T1 |
5 |
|
T24 |
4 |
|
T7 |
6 |
| auto[1] |
auto[1] |
461 |
1 |
|
|
T1 |
3 |
|
T24 |
4 |
|
T7 |
9 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
405 |
1 |
|
|
T1 |
6 |
|
T24 |
4 |
|
T7 |
5 |
| auto[0] |
auto[1] |
466 |
1 |
|
|
T1 |
7 |
|
T24 |
7 |
|
T7 |
6 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T1 |
3 |
|
T24 |
7 |
|
T7 |
5 |
| auto[1] |
auto[1] |
462 |
1 |
|
|
T1 |
4 |
|
T24 |
2 |
|
T7 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T1 |
6 |
|
T24 |
4 |
|
T7 |
5 |
| auto[0] |
auto[1] |
464 |
1 |
|
|
T1 |
5 |
|
T24 |
8 |
|
T7 |
4 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T1 |
5 |
|
T24 |
6 |
|
T7 |
7 |
| auto[1] |
auto[1] |
442 |
1 |
|
|
T1 |
4 |
|
T24 |
2 |
|
T7 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
476 |
1 |
|
|
T1 |
8 |
|
T24 |
6 |
|
T7 |
7 |
| auto[0] |
auto[1] |
416 |
1 |
|
|
T1 |
2 |
|
T24 |
6 |
|
T7 |
3 |
| auto[1] |
auto[0] |
441 |
1 |
|
|
T1 |
4 |
|
T24 |
4 |
|
T7 |
4 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T1 |
6 |
|
T24 |
4 |
|
T7 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T1 |
6 |
|
T24 |
4 |
|
T7 |
7 |
| auto[0] |
auto[1] |
412 |
1 |
|
|
T1 |
3 |
|
T24 |
4 |
|
T7 |
1 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T1 |
3 |
|
T24 |
6 |
|
T7 |
6 |
| auto[1] |
auto[1] |
492 |
1 |
|
|
T1 |
8 |
|
T24 |
6 |
|
T7 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T1 |
7 |
|
T24 |
4 |
|
T7 |
5 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T1 |
1 |
|
T24 |
9 |
|
T7 |
3 |
| auto[1] |
auto[0] |
395 |
1 |
|
|
T1 |
8 |
|
T24 |
3 |
|
T7 |
7 |
| auto[1] |
auto[1] |
463 |
1 |
|
|
T1 |
4 |
|
T24 |
4 |
|
T7 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T1 |
8 |
|
T24 |
6 |
|
T7 |
5 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T1 |
3 |
|
T24 |
6 |
|
T7 |
5 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T1 |
6 |
|
T24 |
6 |
|
T7 |
5 |
| auto[1] |
auto[1] |
454 |
1 |
|
|
T1 |
3 |
|
T24 |
2 |
|
T7 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
447 |
1 |
|
|
T1 |
6 |
|
T24 |
4 |
|
T7 |
4 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T1 |
5 |
|
T24 |
6 |
|
T7 |
3 |
| auto[1] |
auto[0] |
466 |
1 |
|
|
T1 |
7 |
|
T24 |
5 |
|
T7 |
9 |
| auto[1] |
auto[1] |
422 |
1 |
|
|
T1 |
2 |
|
T24 |
5 |
|
T7 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
894 |
1 |
|
|
T1 |
9 |
|
T24 |
9 |
|
T7 |
9 |
| auto[1] |
auto[1] |
866 |
1 |
|
|
T1 |
11 |
|
T24 |
11 |
|
T7 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T1 |
8 |
|
T24 |
8 |
|
T7 |
5 |
| auto[0] |
auto[1] |
473 |
1 |
|
|
T1 |
5 |
|
T24 |
2 |
|
T7 |
8 |
| auto[1] |
auto[0] |
428 |
1 |
|
|
T1 |
3 |
|
T24 |
4 |
|
T7 |
4 |
| auto[1] |
auto[1] |
433 |
1 |
|
|
T1 |
4 |
|
T24 |
6 |
|
T7 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
883 |
1 |
|
|
T1 |
5 |
|
T24 |
9 |
|
T7 |
11 |
| auto[1] |
auto[1] |
877 |
1 |
|
|
T1 |
15 |
|
T24 |
11 |
|
T7 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T7 |
8 |
|
T31 |
8 |
|
T36 |
8 |
| auto[1] |
72 |
1 |
|
|
T7 |
12 |
|
T31 |
12 |
|
T36 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T7 |
11 |
|
T31 |
9 |
|
T36 |
9 |
| auto[1] |
77 |
1 |
|
|
T7 |
9 |
|
T31 |
11 |
|
T36 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T7 |
12 |
|
T31 |
11 |
|
T36 |
10 |
| auto[1] |
85 |
1 |
|
|
T7 |
8 |
|
T31 |
9 |
|
T36 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T7 |
7 |
|
T31 |
10 |
|
T36 |
9 |
| auto[1] |
84 |
1 |
|
|
T7 |
13 |
|
T31 |
10 |
|
T36 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T7 |
7 |
|
T31 |
9 |
|
T36 |
11 |
| auto[1] |
76 |
1 |
|
|
T7 |
13 |
|
T31 |
11 |
|
T36 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T7 |
5 |
|
T31 |
6 |
|
T36 |
8 |
| auto[1] |
90 |
1 |
|
|
T7 |
15 |
|
T31 |
14 |
|
T36 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T7 |
10 |
|
T31 |
12 |
|
T36 |
11 |
| auto[1] |
72 |
1 |
|
|
T7 |
10 |
|
T31 |
8 |
|
T36 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73 |
1 |
|
|
T7 |
9 |
|
T31 |
8 |
|
T36 |
13 |
| auto[1] |
87 |
1 |
|
|
T7 |
11 |
|
T31 |
12 |
|
T36 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T7 |
13 |
|
T31 |
13 |
|
T36 |
4 |
| auto[1] |
89 |
1 |
|
|
T7 |
7 |
|
T31 |
7 |
|
T36 |
16 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67 |
1 |
|
|
T7 |
9 |
|
T31 |
7 |
|
T36 |
11 |
| auto[1] |
93 |
1 |
|
|
T7 |
11 |
|
T31 |
13 |
|
T36 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T7 |
7 |
|
T31 |
10 |
|
T36 |
7 |
| auto[1] |
89 |
1 |
|
|
T7 |
13 |
|
T31 |
10 |
|
T36 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T7 |
9 |
|
T31 |
12 |
|
T36 |
10 |
| auto[1] |
77 |
1 |
|
|
T7 |
11 |
|
T31 |
8 |
|
T36 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T7 |
10 |
|
T31 |
6 |
|
T36 |
13 |
| auto[1] |
84 |
1 |
|
|
T7 |
10 |
|
T31 |
14 |
|
T36 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T7 |
11 |
|
T31 |
9 |
|
T36 |
9 |
| auto[1] |
77 |
1 |
|
|
T7 |
9 |
|
T31 |
11 |
|
T36 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T7 |
11 |
|
T31 |
9 |
|
T36 |
8 |
| auto[1] |
80 |
1 |
|
|
T7 |
9 |
|
T31 |
11 |
|
T36 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T7 |
14 |
|
T31 |
14 |
|
T36 |
11 |
| auto[1] |
63 |
1 |
|
|
T7 |
6 |
|
T31 |
6 |
|
T36 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T7 |
9 |
|
T31 |
15 |
|
T36 |
10 |
| auto[1] |
77 |
1 |
|
|
T7 |
11 |
|
T31 |
5 |
|
T36 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T7 |
13 |
|
T31 |
6 |
|
T36 |
11 |
| auto[1] |
81 |
1 |
|
|
T7 |
7 |
|
T31 |
14 |
|
T36 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T7 |
10 |
|
T31 |
12 |
|
T36 |
9 |
| auto[1] |
83 |
1 |
|
|
T7 |
10 |
|
T31 |
8 |
|
T36 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T7 |
11 |
|
T31 |
10 |
|
T36 |
11 |
| auto[1] |
76 |
1 |
|
|
T7 |
9 |
|
T31 |
10 |
|
T36 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T7 |
8 |
|
T31 |
15 |
|
T36 |
12 |
| auto[1] |
75 |
1 |
|
|
T7 |
12 |
|
T31 |
5 |
|
T36 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T7 |
10 |
|
T31 |
6 |
|
T36 |
14 |
| auto[1] |
79 |
1 |
|
|
T7 |
10 |
|
T31 |
14 |
|
T36 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T7 |
10 |
|
T31 |
13 |
|
T36 |
12 |
| auto[1] |
65 |
1 |
|
|
T7 |
10 |
|
T31 |
7 |
|
T36 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T7 |
9 |
|
T31 |
12 |
|
T36 |
10 |
| auto[1] |
77 |
1 |
|
|
T7 |
11 |
|
T31 |
8 |
|
T36 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
31 |
1 |
|
|
T7 |
6 |
|
T31 |
5 |
|
T36 |
3 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T7 |
5 |
|
T31 |
4 |
|
T36 |
5 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T7 |
6 |
|
T31 |
6 |
|
T36 |
7 |
| auto[1] |
auto[1] |
36 |
1 |
|
|
T7 |
3 |
|
T31 |
5 |
|
T36 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
40 |
1 |
|
|
T7 |
5 |
|
T31 |
7 |
|
T36 |
4 |
| auto[0] |
auto[1] |
57 |
1 |
|
|
T7 |
9 |
|
T31 |
7 |
|
T36 |
7 |
| auto[1] |
auto[0] |
36 |
1 |
|
|
T7 |
2 |
|
T31 |
3 |
|
T36 |
5 |
| auto[1] |
auto[1] |
27 |
1 |
|
|
T7 |
4 |
|
T31 |
3 |
|
T36 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T7 |
4 |
|
T31 |
8 |
|
T36 |
4 |
| auto[0] |
auto[1] |
41 |
1 |
|
|
T7 |
5 |
|
T31 |
7 |
|
T36 |
6 |
| auto[1] |
auto[0] |
42 |
1 |
|
|
T7 |
3 |
|
T31 |
1 |
|
T36 |
7 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T7 |
8 |
|
T31 |
4 |
|
T36 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
33 |
1 |
|
|
T7 |
5 |
|
T31 |
2 |
|
T36 |
3 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T7 |
8 |
|
T31 |
4 |
|
T36 |
8 |
| auto[1] |
auto[0] |
37 |
1 |
|
|
T31 |
4 |
|
T36 |
5 |
|
T38 |
4 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T7 |
7 |
|
T31 |
10 |
|
T36 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T7 |
3 |
|
T31 |
8 |
|
T36 |
4 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T7 |
7 |
|
T31 |
4 |
|
T36 |
5 |
| auto[1] |
auto[0] |
46 |
1 |
|
|
T7 |
7 |
|
T31 |
4 |
|
T36 |
7 |
| auto[1] |
auto[1] |
37 |
1 |
|
|
T7 |
3 |
|
T31 |
4 |
|
T36 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
38 |
1 |
|
|
T7 |
3 |
|
T31 |
5 |
|
T36 |
6 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T7 |
8 |
|
T31 |
5 |
|
T36 |
5 |
| auto[1] |
auto[0] |
35 |
1 |
|
|
T7 |
6 |
|
T31 |
3 |
|
T36 |
7 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T7 |
3 |
|
T31 |
7 |
|
T36 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T7 |
4 |
|
T31 |
3 |
|
T36 |
9 |
| auto[0] |
auto[1] |
39 |
1 |
|
|
T7 |
6 |
|
T31 |
3 |
|
T36 |
5 |
| auto[1] |
auto[0] |
25 |
1 |
|
|
T7 |
5 |
|
T31 |
4 |
|
T36 |
2 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T7 |
5 |
|
T31 |
10 |
|
T36 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T7 |
3 |
|
T31 |
8 |
|
T36 |
6 |
| auto[0] |
auto[1] |
44 |
1 |
|
|
T7 |
7 |
|
T31 |
5 |
|
T36 |
6 |
| auto[1] |
auto[0] |
20 |
1 |
|
|
T7 |
4 |
|
T31 |
2 |
|
T36 |
1 |
| auto[1] |
auto[1] |
45 |
1 |
|
|
T7 |
6 |
|
T31 |
5 |
|
T36 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T7 |
5 |
|
T31 |
1 |
|
T36 |
7 |
| auto[0] |
auto[1] |
37 |
1 |
|
|
T7 |
5 |
|
T31 |
5 |
|
T36 |
6 |
| auto[1] |
auto[0] |
49 |
1 |
|
|
T7 |
3 |
|
T31 |
7 |
|
T36 |
1 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T7 |
7 |
|
T31 |
7 |
|
T36 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T7 |
11 |
|
T31 |
9 |
|
T36 |
9 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T7 |
9 |
|
T31 |
11 |
|
T36 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T7 |
5 |
|
T31 |
9 |
|
T36 |
3 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T7 |
3 |
|
T31 |
6 |
|
T36 |
9 |
| auto[1] |
auto[0] |
32 |
1 |
|
|
T7 |
8 |
|
T31 |
4 |
|
T36 |
1 |
| auto[1] |
auto[1] |
43 |
1 |
|
|
T7 |
4 |
|
T31 |
1 |
|
T36 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T7 |
9 |
|
T31 |
12 |
|
T36 |
10 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T7 |
11 |
|
T31 |
8 |
|
T36 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T36 |
11 |
|
T134 |
12 |
|
T282 |
11 |
| auto[1] |
64 |
1 |
|
|
T36 |
9 |
|
T134 |
8 |
|
T282 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T36 |
12 |
|
T134 |
9 |
|
T282 |
11 |
| auto[1] |
60 |
1 |
|
|
T36 |
8 |
|
T134 |
11 |
|
T282 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T36 |
12 |
|
T134 |
11 |
|
T282 |
9 |
| auto[1] |
49 |
1 |
|
|
T36 |
8 |
|
T134 |
9 |
|
T282 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T36 |
9 |
|
T134 |
8 |
|
T282 |
8 |
| auto[1] |
63 |
1 |
|
|
T36 |
11 |
|
T134 |
12 |
|
T282 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T36 |
9 |
|
T134 |
8 |
|
T282 |
6 |
| auto[1] |
65 |
1 |
|
|
T36 |
11 |
|
T134 |
12 |
|
T282 |
14 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T36 |
10 |
|
T134 |
13 |
|
T282 |
7 |
| auto[1] |
63 |
1 |
|
|
T36 |
10 |
|
T134 |
7 |
|
T282 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T36 |
6 |
|
T134 |
9 |
|
T282 |
7 |
| auto[1] |
68 |
1 |
|
|
T36 |
14 |
|
T134 |
11 |
|
T282 |
13 |