Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T21 |
9 |
|
T22 |
13 |
|
T23 |
9 |
| auto[1] |
918 |
1 |
|
|
T21 |
11 |
|
T22 |
7 |
|
T23 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
929 |
1 |
|
|
T21 |
10 |
|
T22 |
12 |
|
T23 |
10 |
| auto[1] |
891 |
1 |
|
|
T21 |
10 |
|
T22 |
8 |
|
T23 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
929 |
1 |
|
|
T21 |
12 |
|
T22 |
5 |
|
T23 |
8 |
| auto[1] |
891 |
1 |
|
|
T21 |
8 |
|
T22 |
15 |
|
T23 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
896 |
1 |
|
|
T21 |
14 |
|
T22 |
10 |
|
T23 |
12 |
| auto[1] |
924 |
1 |
|
|
T21 |
6 |
|
T22 |
10 |
|
T23 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T21 |
12 |
|
T22 |
11 |
|
T23 |
12 |
| auto[1] |
914 |
1 |
|
|
T21 |
8 |
|
T22 |
9 |
|
T23 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
896 |
1 |
|
|
T21 |
5 |
|
T22 |
7 |
|
T23 |
13 |
| auto[1] |
924 |
1 |
|
|
T21 |
15 |
|
T22 |
13 |
|
T23 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
903 |
1 |
|
|
T21 |
7 |
|
T22 |
9 |
|
T23 |
13 |
| auto[1] |
917 |
1 |
|
|
T21 |
13 |
|
T22 |
11 |
|
T23 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T21 |
8 |
|
T22 |
14 |
|
T23 |
10 |
| auto[1] |
907 |
1 |
|
|
T21 |
12 |
|
T22 |
6 |
|
T23 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
916 |
1 |
|
|
T21 |
11 |
|
T22 |
6 |
|
T23 |
14 |
| auto[1] |
904 |
1 |
|
|
T21 |
9 |
|
T22 |
14 |
|
T23 |
6 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
908 |
1 |
|
|
T21 |
7 |
|
T22 |
11 |
|
T23 |
7 |
| auto[1] |
912 |
1 |
|
|
T21 |
13 |
|
T22 |
9 |
|
T23 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
951 |
1 |
|
|
T21 |
13 |
|
T22 |
10 |
|
T23 |
14 |
| auto[1] |
869 |
1 |
|
|
T21 |
7 |
|
T22 |
10 |
|
T23 |
6 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T23 |
10 |
| auto[1] |
942 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T23 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T21 |
9 |
|
T22 |
12 |
|
T23 |
14 |
| auto[1] |
911 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T23 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
929 |
1 |
|
|
T21 |
10 |
|
T22 |
12 |
|
T23 |
10 |
| auto[1] |
891 |
1 |
|
|
T21 |
10 |
|
T22 |
8 |
|
T23 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
942 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T23 |
12 |
| auto[1] |
878 |
1 |
|
|
T21 |
9 |
|
T22 |
12 |
|
T23 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
905 |
1 |
|
|
T21 |
11 |
|
T22 |
13 |
|
T23 |
12 |
| auto[1] |
915 |
1 |
|
|
T21 |
9 |
|
T22 |
7 |
|
T23 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
919 |
1 |
|
|
T21 |
9 |
|
T22 |
12 |
|
T23 |
13 |
| auto[1] |
901 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T23 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
963 |
1 |
|
|
T21 |
14 |
|
T22 |
14 |
|
T23 |
8 |
| auto[1] |
857 |
1 |
|
|
T21 |
6 |
|
T22 |
6 |
|
T23 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
913 |
1 |
|
|
T21 |
10 |
|
T22 |
7 |
|
T23 |
10 |
| auto[1] |
907 |
1 |
|
|
T21 |
10 |
|
T22 |
13 |
|
T23 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
865 |
1 |
|
|
T21 |
9 |
|
T22 |
8 |
|
T23 |
5 |
| auto[1] |
955 |
1 |
|
|
T21 |
11 |
|
T22 |
12 |
|
T23 |
15 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T21 |
8 |
|
T22 |
7 |
|
T23 |
11 |
| auto[1] |
942 |
1 |
|
|
T21 |
12 |
|
T22 |
13 |
|
T23 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T21 |
9 |
|
T22 |
13 |
|
T23 |
12 |
| auto[1] |
940 |
1 |
|
|
T21 |
11 |
|
T22 |
7 |
|
T23 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
915 |
1 |
|
|
T21 |
7 |
|
T22 |
8 |
|
T23 |
11 |
| auto[1] |
905 |
1 |
|
|
T21 |
13 |
|
T22 |
12 |
|
T23 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T23 |
10 |
| auto[1] |
942 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T23 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
480 |
1 |
|
|
T21 |
8 |
|
T22 |
2 |
|
T23 |
7 |
| auto[0] |
auto[1] |
462 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T23 |
5 |
| auto[1] |
auto[0] |
449 |
1 |
|
|
T21 |
4 |
|
T22 |
3 |
|
T23 |
1 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T21 |
5 |
|
T22 |
9 |
|
T23 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
445 |
1 |
|
|
T21 |
9 |
|
T22 |
7 |
|
T23 |
9 |
| auto[0] |
auto[1] |
460 |
1 |
|
|
T21 |
2 |
|
T22 |
6 |
|
T23 |
3 |
| auto[1] |
auto[0] |
451 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T23 |
3 |
| auto[1] |
auto[1] |
464 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T23 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T21 |
4 |
|
T22 |
7 |
|
T23 |
8 |
| auto[0] |
auto[1] |
477 |
1 |
|
|
T21 |
5 |
|
T22 |
5 |
|
T23 |
5 |
| auto[1] |
auto[0] |
464 |
1 |
|
|
T21 |
8 |
|
T22 |
4 |
|
T23 |
4 |
| auto[1] |
auto[1] |
437 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T23 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
459 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T23 |
6 |
| auto[0] |
auto[1] |
504 |
1 |
|
|
T21 |
11 |
|
T22 |
8 |
|
T23 |
2 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T21 |
2 |
|
T22 |
1 |
|
T23 |
7 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T23 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
456 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T23 |
5 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T21 |
5 |
|
T22 |
4 |
|
T23 |
5 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T21 |
2 |
|
T22 |
6 |
|
T23 |
8 |
| auto[1] |
auto[1] |
460 |
1 |
|
|
T21 |
8 |
|
T22 |
7 |
|
T23 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T21 |
5 |
|
T22 |
6 |
|
T23 |
1 |
| auto[0] |
auto[1] |
428 |
1 |
|
|
T21 |
4 |
|
T22 |
2 |
|
T23 |
4 |
| auto[1] |
auto[0] |
476 |
1 |
|
|
T21 |
3 |
|
T22 |
8 |
|
T23 |
9 |
| auto[1] |
auto[1] |
479 |
1 |
|
|
T21 |
8 |
|
T22 |
4 |
|
T23 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
449 |
1 |
|
|
T21 |
2 |
|
T22 |
8 |
|
T23 |
5 |
| auto[0] |
auto[1] |
431 |
1 |
|
|
T21 |
7 |
|
T22 |
5 |
|
T23 |
7 |
| auto[1] |
auto[0] |
459 |
1 |
|
|
T21 |
5 |
|
T22 |
3 |
|
T23 |
2 |
| auto[1] |
auto[1] |
481 |
1 |
|
|
T21 |
6 |
|
T22 |
4 |
|
T23 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
488 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T23 |
8 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T21 |
3 |
|
T22 |
3 |
|
T23 |
3 |
| auto[1] |
auto[0] |
463 |
1 |
|
|
T21 |
9 |
|
T22 |
5 |
|
T23 |
6 |
| auto[1] |
auto[1] |
442 |
1 |
|
|
T21 |
4 |
|
T22 |
7 |
|
T23 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
465 |
1 |
|
|
T21 |
5 |
|
T22 |
8 |
|
T23 |
5 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T21 |
4 |
|
T22 |
4 |
|
T23 |
9 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T21 |
4 |
|
T22 |
5 |
|
T23 |
4 |
| auto[1] |
auto[1] |
474 |
1 |
|
|
T21 |
7 |
|
T22 |
3 |
|
T23 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
929 |
1 |
|
|
T21 |
10 |
|
T22 |
12 |
|
T23 |
10 |
| auto[1] |
auto[1] |
891 |
1 |
|
|
T21 |
10 |
|
T22 |
8 |
|
T23 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T21 |
5 |
|
T22 |
1 |
|
T23 |
7 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T23 |
4 |
| auto[1] |
auto[0] |
483 |
1 |
|
|
T21 |
6 |
|
T22 |
5 |
|
T23 |
7 |
| auto[1] |
auto[1] |
459 |
1 |
|
|
T21 |
6 |
|
T22 |
8 |
|
T23 |
2 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
878 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T23 |
10 |
| auto[1] |
auto[1] |
942 |
1 |
|
|
T21 |
10 |
|
T22 |
10 |
|
T23 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T22 |
11 |
|
T35 |
10 |
|
T75 |
12 |
| auto[1] |
158 |
1 |
|
|
T22 |
9 |
|
T35 |
10 |
|
T75 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T22 |
10 |
|
T35 |
11 |
|
T75 |
14 |
| auto[1] |
150 |
1 |
|
|
T22 |
10 |
|
T35 |
9 |
|
T75 |
6 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T22 |
10 |
|
T35 |
12 |
|
T75 |
8 |
| auto[1] |
143 |
1 |
|
|
T22 |
10 |
|
T35 |
8 |
|
T75 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T22 |
8 |
|
T35 |
11 |
|
T75 |
12 |
| auto[1] |
151 |
1 |
|
|
T22 |
12 |
|
T35 |
9 |
|
T75 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T22 |
13 |
|
T35 |
8 |
|
T75 |
9 |
| auto[1] |
150 |
1 |
|
|
T22 |
7 |
|
T35 |
12 |
|
T75 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T22 |
8 |
|
T35 |
12 |
|
T75 |
12 |
| auto[1] |
139 |
1 |
|
|
T22 |
12 |
|
T35 |
8 |
|
T75 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T22 |
7 |
|
T35 |
8 |
|
T75 |
15 |
| auto[1] |
138 |
1 |
|
|
T22 |
13 |
|
T35 |
12 |
|
T75 |
5 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T22 |
10 |
|
T35 |
11 |
|
T75 |
11 |
| auto[1] |
151 |
1 |
|
|
T22 |
10 |
|
T35 |
9 |
|
T75 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T22 |
12 |
|
T35 |
11 |
|
T75 |
8 |
| auto[1] |
146 |
1 |
|
|
T22 |
8 |
|
T35 |
9 |
|
T75 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T22 |
14 |
|
T35 |
6 |
|
T75 |
7 |
| auto[1] |
151 |
1 |
|
|
T22 |
6 |
|
T35 |
14 |
|
T75 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T22 |
7 |
|
T35 |
10 |
|
T75 |
11 |
| auto[1] |
153 |
1 |
|
|
T22 |
13 |
|
T35 |
10 |
|
T75 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T22 |
9 |
|
T35 |
12 |
|
T75 |
11 |
| auto[1] |
150 |
1 |
|
|
T22 |
11 |
|
T35 |
8 |
|
T75 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T22 |
13 |
|
T35 |
9 |
|
T75 |
9 |
| auto[1] |
152 |
1 |
|
|
T22 |
7 |
|
T35 |
11 |
|
T75 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T22 |
10 |
|
T35 |
11 |
|
T75 |
14 |
| auto[1] |
150 |
1 |
|
|
T22 |
10 |
|
T35 |
9 |
|
T75 |
6 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T22 |
11 |
|
T35 |
9 |
|
T75 |
12 |
| auto[1] |
147 |
1 |
|
|
T22 |
9 |
|
T35 |
11 |
|
T75 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T22 |
11 |
|
T35 |
8 |
|
T75 |
12 |
| auto[1] |
163 |
1 |
|
|
T22 |
9 |
|
T35 |
12 |
|
T75 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T22 |
8 |
|
T35 |
8 |
|
T75 |
13 |
| auto[1] |
154 |
1 |
|
|
T22 |
12 |
|
T35 |
12 |
|
T75 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T22 |
9 |
|
T35 |
14 |
|
T75 |
10 |
| auto[1] |
143 |
1 |
|
|
T22 |
11 |
|
T35 |
6 |
|
T75 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T22 |
12 |
|
T35 |
9 |
|
T75 |
13 |
| auto[1] |
151 |
1 |
|
|
T22 |
8 |
|
T35 |
11 |
|
T75 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
166 |
1 |
|
|
T22 |
15 |
|
T35 |
10 |
|
T75 |
11 |
| auto[1] |
134 |
1 |
|
|
T22 |
5 |
|
T35 |
10 |
|
T75 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T22 |
10 |
|
T35 |
9 |
|
T75 |
10 |
| auto[1] |
138 |
1 |
|
|
T22 |
10 |
|
T35 |
11 |
|
T75 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T22 |
9 |
|
T35 |
11 |
|
T75 |
11 |
| auto[1] |
151 |
1 |
|
|
T22 |
11 |
|
T35 |
9 |
|
T75 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T22 |
10 |
|
T35 |
9 |
|
T75 |
7 |
| auto[1] |
153 |
1 |
|
|
T22 |
10 |
|
T35 |
11 |
|
T75 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T22 |
9 |
|
T35 |
12 |
|
T75 |
11 |
| auto[1] |
150 |
1 |
|
|
T22 |
11 |
|
T35 |
8 |
|
T75 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
79 |
1 |
|
|
T22 |
6 |
|
T35 |
7 |
|
T75 |
7 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T22 |
5 |
|
T35 |
2 |
|
T75 |
5 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T22 |
4 |
|
T35 |
5 |
|
T75 |
1 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T22 |
5 |
|
T35 |
6 |
|
T75 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T22 |
5 |
|
T35 |
6 |
|
T75 |
9 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T22 |
6 |
|
T35 |
2 |
|
T75 |
3 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T22 |
3 |
|
T35 |
5 |
|
T75 |
3 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T22 |
6 |
|
T35 |
7 |
|
T75 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T22 |
6 |
|
T35 |
3 |
|
T75 |
7 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T22 |
2 |
|
T35 |
5 |
|
T75 |
6 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T22 |
7 |
|
T35 |
5 |
|
T75 |
2 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T22 |
5 |
|
T35 |
7 |
|
T75 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
87 |
1 |
|
|
T22 |
4 |
|
T35 |
8 |
|
T75 |
7 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T22 |
5 |
|
T35 |
6 |
|
T75 |
3 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T22 |
4 |
|
T35 |
4 |
|
T75 |
5 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T22 |
7 |
|
T35 |
2 |
|
T75 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T22 |
5 |
|
T35 |
2 |
|
T75 |
11 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T22 |
7 |
|
T35 |
7 |
|
T75 |
2 |
| auto[1] |
auto[0] |
81 |
1 |
|
|
T22 |
2 |
|
T35 |
6 |
|
T75 |
4 |
| auto[1] |
auto[1] |
70 |
1 |
|
|
T22 |
6 |
|
T35 |
5 |
|
T75 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T22 |
8 |
|
T35 |
4 |
|
T75 |
8 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T22 |
7 |
|
T35 |
6 |
|
T75 |
3 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T22 |
2 |
|
T35 |
7 |
|
T75 |
3 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T22 |
3 |
|
T35 |
3 |
|
T75 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T22 |
7 |
|
T35 |
3 |
|
T75 |
3 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T22 |
2 |
|
T35 |
8 |
|
T75 |
8 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T22 |
7 |
|
T35 |
3 |
|
T75 |
4 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T22 |
4 |
|
T35 |
6 |
|
T75 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T22 |
4 |
|
T35 |
4 |
|
T75 |
3 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T22 |
6 |
|
T35 |
5 |
|
T75 |
4 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T22 |
3 |
|
T35 |
6 |
|
T75 |
8 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T22 |
7 |
|
T35 |
5 |
|
T75 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
68 |
1 |
|
|
T22 |
6 |
|
T35 |
2 |
|
T75 |
6 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T22 |
7 |
|
T35 |
7 |
|
T75 |
3 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T22 |
5 |
|
T35 |
8 |
|
T75 |
6 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T22 |
2 |
|
T35 |
3 |
|
T75 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
150 |
1 |
|
|
T22 |
10 |
|
T35 |
11 |
|
T75 |
14 |
| auto[1] |
auto[1] |
150 |
1 |
|
|
T22 |
10 |
|
T35 |
9 |
|
T75 |
6 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
89 |
1 |
|
|
T22 |
4 |
|
T35 |
6 |
|
T75 |
4 |
| auto[0] |
auto[1] |
73 |
1 |
|
|
T22 |
6 |
|
T35 |
3 |
|
T75 |
6 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T22 |
8 |
|
T35 |
5 |
|
T75 |
4 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T22 |
2 |
|
T35 |
6 |
|
T75 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
150 |
1 |
|
|
T22 |
9 |
|
T35 |
12 |
|
T75 |
11 |
| auto[1] |
auto[1] |
150 |
1 |
|
|
T22 |
11 |
|
T35 |
8 |
|
T75 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T35 |
5 |
|
T75 |
10 |
|
T308 |
13 |
| auto[1] |
81 |
1 |
|
|
T35 |
15 |
|
T75 |
10 |
|
T308 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T35 |
8 |
|
T75 |
12 |
|
T308 |
9 |
| auto[1] |
81 |
1 |
|
|
T35 |
12 |
|
T75 |
8 |
|
T308 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T35 |
9 |
|
T75 |
11 |
|
T308 |
8 |
| auto[1] |
83 |
1 |
|
|
T35 |
11 |
|
T75 |
9 |
|
T308 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T35 |
10 |
|
T75 |
8 |
|
T308 |
8 |
| auto[1] |
81 |
1 |
|
|
T35 |
10 |
|
T75 |
12 |
|
T308 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T35 |
12 |
|
T75 |
7 |
|
T308 |
11 |
| auto[1] |
72 |
1 |
|
|
T35 |
8 |
|
T75 |
13 |
|
T308 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T35 |
6 |
|
T75 |
8 |
|
T308 |
6 |
| auto[1] |
86 |
1 |
|
|
T35 |
14 |
|
T75 |
12 |
|
T308 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T35 |
11 |
|
T75 |
11 |
|
T308 |
9 |
| auto[1] |
72 |
1 |
|
|
T35 |
9 |
|
T75 |
9 |
|
T308 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T35 |
10 |
|
T75 |
12 |
|
T308 |
10 |
| auto[1] |
73 |
1 |
|
|
T35 |
10 |
|
T75 |
8 |
|
T308 |
10 |