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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.17 99.42 96.73 100.00 98.08 98.89 99.71 94.38


Total test records in report: 918
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T792 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3289145446 Aug 01 05:23:54 PM PDT 24 Aug 01 05:23:58 PM PDT 24 2542403163 ps
T168 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2756173197 Aug 01 05:25:36 PM PDT 24 Aug 01 05:25:39 PM PDT 24 4595620974 ps
T358 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.4085631542 Aug 01 05:26:51 PM PDT 24 Aug 01 05:30:30 PM PDT 24 90786052349 ps
T27 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3243046076 Aug 01 05:22:20 PM PDT 24 Aug 01 05:22:29 PM PDT 24 2460488861 ps
T28 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3425977858 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:33 PM PDT 24 4981923109 ps
T793 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3889679036 Aug 01 05:22:44 PM PDT 24 Aug 01 05:22:47 PM PDT 24 2017321905 ps
T76 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3282811905 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:30 PM PDT 24 2491472582 ps
T794 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1514859636 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2076297704 ps
T77 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.737787812 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2126944645 ps
T17 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1302550635 Aug 01 05:22:20 PM PDT 24 Aug 01 05:22:22 PM PDT 24 4954962891 ps
T795 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1890703789 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:24 PM PDT 24 2043888458 ps
T796 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3326818107 Aug 01 05:22:41 PM PDT 24 Aug 01 05:22:44 PM PDT 24 2016267117 ps
T29 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.4012112283 Aug 01 05:22:27 PM PDT 24 Aug 01 05:23:27 PM PDT 24 22228056650 ps
T84 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3511436163 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2053992010 ps
T96 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4222056662 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:29 PM PDT 24 2067898927 ps
T797 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3573483287 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2013037354 ps
T798 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3375847017 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2009538647 ps
T799 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1054898357 Aug 01 05:22:41 PM PDT 24 Aug 01 05:22:47 PM PDT 24 2016615154 ps
T327 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.269112607 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:24 PM PDT 24 2664406344 ps
T18 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4195387657 Aug 01 05:22:27 PM PDT 24 Aug 01 05:22:40 PM PDT 24 7136291732 ps
T800 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.4216458654 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2019486268 ps
T801 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3667711355 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:30 PM PDT 24 2026490106 ps
T334 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.596039668 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2783041723 ps
T85 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2132453810 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2062975343 ps
T802 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.849026643 Aug 01 05:22:07 PM PDT 24 Aug 01 05:22:13 PM PDT 24 2014904513 ps
T78 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.753798758 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:34 PM PDT 24 44597408930 ps
T83 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1930904840 Aug 01 05:22:31 PM PDT 24 Aug 01 05:22:38 PM PDT 24 2019217496 ps
T19 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1928677724 Aug 01 05:22:30 PM PDT 24 Aug 01 05:23:07 PM PDT 24 9239871376 ps
T81 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3566518606 Aug 01 05:22:20 PM PDT 24 Aug 01 05:23:16 PM PDT 24 22219734735 ps
T344 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2762755692 Aug 01 05:22:32 PM PDT 24 Aug 01 05:22:37 PM PDT 24 2059654301 ps
T335 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2590111921 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2115817441 ps
T92 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2499596153 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2200762750 ps
T803 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1361422770 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:25 PM PDT 24 2634929766 ps
T380 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3707840134 Aug 01 05:22:25 PM PDT 24 Aug 01 05:23:25 PM PDT 24 42414616083 ps
T804 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.153300599 Aug 01 05:22:40 PM PDT 24 Aug 01 05:22:46 PM PDT 24 2015970771 ps
T345 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2700992294 Aug 01 05:22:32 PM PDT 24 Aug 01 05:22:42 PM PDT 24 7511746556 ps
T346 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2708637186 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2048322906 ps
T336 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2215968787 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:34 PM PDT 24 2027730153 ps
T805 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4099630969 Aug 01 05:22:40 PM PDT 24 Aug 01 05:22:45 PM PDT 24 2013368710 ps
T806 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4161305873 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:33 PM PDT 24 7597615411 ps
T94 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1390272942 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2087112313 ps
T337 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1877365736 Aug 01 05:22:24 PM PDT 24 Aug 01 05:23:21 PM PDT 24 20562822095 ps
T807 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1556694845 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:29 PM PDT 24 2077104175 ps
T808 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2561488160 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:35 PM PDT 24 2013312917 ps
T98 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.239247171 Aug 01 05:22:21 PM PDT 24 Aug 01 05:23:04 PM PDT 24 42747489405 ps
T809 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3334176255 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:29 PM PDT 24 2021016374 ps
T810 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.789108215 Aug 01 05:22:36 PM PDT 24 Aug 01 05:22:38 PM PDT 24 2029363701 ps
T88 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4208202925 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2054437069 ps
T811 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.967294653 Aug 01 05:22:39 PM PDT 24 Aug 01 05:22:42 PM PDT 24 2019652327 ps
T87 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1981193454 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:33 PM PDT 24 2035178359 ps
T338 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1556820346 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:25 PM PDT 24 4065492656 ps
T812 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.370046249 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:25 PM PDT 24 2182974282 ps
T813 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2118302367 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:25 PM PDT 24 2080028469 ps
T814 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2611370817 Aug 01 05:22:07 PM PDT 24 Aug 01 05:22:13 PM PDT 24 2063241421 ps
T815 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2382189862 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:26 PM PDT 24 5296502303 ps
T93 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3575381589 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:26 PM PDT 24 2166823728 ps
T95 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.2003718188 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:33 PM PDT 24 2061588888 ps
T816 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3846577051 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:42 PM PDT 24 9661296817 ps
T817 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2291089628 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2021707178 ps
T818 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.961118818 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:34 PM PDT 24 2012474246 ps
T819 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.309672506 Aug 01 05:22:43 PM PDT 24 Aug 01 05:22:45 PM PDT 24 2040695248 ps
T820 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.639744938 Aug 01 05:22:39 PM PDT 24 Aug 01 05:22:41 PM PDT 24 2042841041 ps
T821 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4151227643 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2104931657 ps
T822 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1843026453 Aug 01 05:22:38 PM PDT 24 Aug 01 05:22:43 PM PDT 24 2014654757 ps
T823 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3965185223 Aug 01 05:22:46 PM PDT 24 Aug 01 05:22:48 PM PDT 24 2032135501 ps
T824 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1403233180 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2043665055 ps
T825 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2447431269 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:56 PM PDT 24 22294314797 ps
T97 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.838355309 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2278419654 ps
T826 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4115674778 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:42 PM PDT 24 4889220624 ps
T827 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.18225810 Aug 01 05:22:22 PM PDT 24 Aug 01 05:23:35 PM PDT 24 42579436036 ps
T828 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1092727985 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:35 PM PDT 24 4413081842 ps
T829 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.948153647 Aug 01 05:22:37 PM PDT 24 Aug 01 05:22:43 PM PDT 24 2013232278 ps
T339 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.127993890 Aug 01 05:22:29 PM PDT 24 Aug 01 05:23:10 PM PDT 24 54554811080 ps
T830 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1794464474 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:35 PM PDT 24 2030895927 ps
T831 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1085147469 Aug 01 05:22:20 PM PDT 24 Aug 01 05:22:23 PM PDT 24 2141265610 ps
T340 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3120947623 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:26 PM PDT 24 6065805413 ps
T832 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3716657743 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:26 PM PDT 24 2098784190 ps
T833 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.714724309 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2084452363 ps
T834 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.850287140 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:58 PM PDT 24 22229114151 ps
T379 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1671583446 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:55 PM PDT 24 42507990576 ps
T835 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3918644013 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:26 PM PDT 24 2060136200 ps
T836 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3021952091 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:30 PM PDT 24 2109405923 ps
T837 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3433452092 Aug 01 05:22:39 PM PDT 24 Aug 01 05:22:45 PM PDT 24 2014338418 ps
T838 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1874710677 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2016159952 ps
T839 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.951557648 Aug 01 05:22:49 PM PDT 24 Aug 01 05:22:55 PM PDT 24 2012957637 ps
T840 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4000441423 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:28 PM PDT 24 4956206719 ps
T841 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1510396290 Aug 01 05:22:37 PM PDT 24 Aug 01 05:22:38 PM PDT 24 2047861844 ps
T842 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2226748525 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2026601931 ps
T91 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3431280909 Aug 01 05:22:04 PM PDT 24 Aug 01 05:22:09 PM PDT 24 2231195625 ps
T843 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2079150536 Aug 01 05:22:40 PM PDT 24 Aug 01 05:22:44 PM PDT 24 2020556641 ps
T844 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1398953642 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:24 PM PDT 24 4996607794 ps
T845 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2015960049 Aug 01 05:22:05 PM PDT 24 Aug 01 05:22:37 PM PDT 24 22312540207 ps
T846 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3214839227 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:25 PM PDT 24 2082801000 ps
T847 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1187833813 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:33 PM PDT 24 22348270540 ps
T848 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3304002867 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2032432144 ps
T849 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3902645024 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:48 PM PDT 24 9341738791 ps
T850 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3915313051 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:38 PM PDT 24 22276043024 ps
T341 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3292172532 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:35 PM PDT 24 2053801176 ps
T851 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3276447817 Aug 01 05:22:33 PM PDT 24 Aug 01 05:22:36 PM PDT 24 2094509702 ps
T852 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.805477569 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2038210080 ps
T853 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1644105804 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:34 PM PDT 24 2024668299 ps
T854 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.4053869255 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2405334896 ps
T342 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3105496630 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:41 PM PDT 24 2730702117 ps
T855 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3282609498 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:34 PM PDT 24 5411767811 ps
T856 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3699476984 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2061235579 ps
T857 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1232590567 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2035788884 ps
T858 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2794292667 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2036138378 ps
T343 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1040286965 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:36 PM PDT 24 3130466351 ps
T859 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2704934780 Aug 01 05:22:31 PM PDT 24 Aug 01 05:22:38 PM PDT 24 2080855893 ps
T860 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2127680010 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:33 PM PDT 24 2043658641 ps
T861 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2575418942 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:50 PM PDT 24 9708711074 ps
T862 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.790197188 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:35 PM PDT 24 4010573967 ps
T863 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.929524996 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2167936357 ps
T864 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.21108582 Aug 01 05:22:35 PM PDT 24 Aug 01 05:22:38 PM PDT 24 2026189629 ps
T865 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1028151035 Aug 01 05:22:25 PM PDT 24 Aug 01 05:23:35 PM PDT 24 42490326986 ps
T866 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2417882473 Aug 01 05:22:19 PM PDT 24 Aug 01 05:22:22 PM PDT 24 2080292930 ps
T867 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1379269236 Aug 01 05:22:27 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2014891842 ps
T868 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.363883001 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:24 PM PDT 24 2070215112 ps
T869 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.935545492 Aug 01 05:22:22 PM PDT 24 Aug 01 05:22:50 PM PDT 24 42810815524 ps
T870 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1163294277 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2033395558 ps
T871 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4117666071 Aug 01 05:22:37 PM PDT 24 Aug 01 05:22:43 PM PDT 24 2011624171 ps
T872 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2243167396 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2105912868 ps
T873 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.491502104 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:37 PM PDT 24 9761758031 ps
T874 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2000752096 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:33 PM PDT 24 2040781999 ps
T875 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3186421724 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:27 PM PDT 24 2034874738 ps
T876 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1373611857 Aug 01 05:22:07 PM PDT 24 Aug 01 05:22:23 PM PDT 24 6038015422 ps
T877 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1810372771 Aug 01 05:22:27 PM PDT 24 Aug 01 05:22:31 PM PDT 24 5406422395 ps
T878 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.33878080 Aug 01 05:22:46 PM PDT 24 Aug 01 05:22:52 PM PDT 24 2012412964 ps
T879 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1837342820 Aug 01 05:22:22 PM PDT 24 Aug 01 05:24:25 PM PDT 24 38347629055 ps
T880 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1980678609 Aug 01 05:22:19 PM PDT 24 Aug 01 05:22:24 PM PDT 24 2555914223 ps
T881 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1094095655 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:30 PM PDT 24 2053432930 ps
T882 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3143642805 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:32 PM PDT 24 2032504135 ps
T883 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3379739687 Aug 01 05:22:49 PM PDT 24 Aug 01 05:22:51 PM PDT 24 2036618108 ps
T884 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3720488197 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2053703364 ps
T885 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1954106049 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:46 PM PDT 24 10649635841 ps
T886 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2807273300 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:47 PM PDT 24 22238404023 ps
T887 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2070950388 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2049036369 ps
T888 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.734952856 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:35 PM PDT 24 2050360759 ps
T889 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1444229385 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:25 PM PDT 24 2070914707 ps
T890 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2831198045 Aug 01 05:22:42 PM PDT 24 Aug 01 05:22:45 PM PDT 24 2019729145 ps
T891 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.115240188 Aug 01 05:22:23 PM PDT 24 Aug 01 05:22:25 PM PDT 24 2046086832 ps
T892 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1691462348 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:29 PM PDT 24 2032790959 ps
T893 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2181222692 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:24 PM PDT 24 2020544953 ps
T894 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.40198380 Aug 01 05:22:35 PM PDT 24 Aug 01 05:22:41 PM PDT 24 2014712920 ps
T895 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4187982981 Aug 01 05:22:28 PM PDT 24 Aug 01 05:23:55 PM PDT 24 38310743987 ps
T896 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1229462770 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:29 PM PDT 24 2064564066 ps
T897 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3161484746 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:33 PM PDT 24 9069385935 ps
T898 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.342897824 Aug 01 05:22:33 PM PDT 24 Aug 01 05:22:38 PM PDT 24 2240114677 ps
T899 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2901529575 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:31 PM PDT 24 2099134914 ps
T900 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2613684366 Aug 01 05:22:36 PM PDT 24 Aug 01 05:22:39 PM PDT 24 2020202321 ps
T901 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1914811560 Aug 01 05:22:30 PM PDT 24 Aug 01 05:24:15 PM PDT 24 42373875219 ps
T902 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2415956370 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:39 PM PDT 24 22527606369 ps
T903 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3399777129 Aug 01 05:22:25 PM PDT 24 Aug 01 05:23:20 PM PDT 24 42577095889 ps
T904 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.7068711 Aug 01 05:22:24 PM PDT 24 Aug 01 05:22:43 PM PDT 24 10180301533 ps
T905 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3086477929 Aug 01 05:22:39 PM PDT 24 Aug 01 05:22:44 PM PDT 24 2015994132 ps
T906 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3428672671 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:28 PM PDT 24 2530720197 ps
T907 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.353710425 Aug 01 05:22:32 PM PDT 24 Aug 01 05:22:38 PM PDT 24 2045832007 ps
T908 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3910434068 Aug 01 05:22:28 PM PDT 24 Aug 01 05:22:56 PM PDT 24 22529352081 ps
T909 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2372455046 Aug 01 05:22:29 PM PDT 24 Aug 01 05:22:33 PM PDT 24 2058788978 ps
T910 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.712976541 Aug 01 05:22:30 PM PDT 24 Aug 01 05:22:33 PM PDT 24 2110382793 ps
T911 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3210496864 Aug 01 05:22:26 PM PDT 24 Aug 01 05:22:29 PM PDT 24 2113633026 ps
T912 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4247918097 Aug 01 05:22:36 PM PDT 24 Aug 01 05:22:39 PM PDT 24 2025624584 ps
T913 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3834474011 Aug 01 05:22:40 PM PDT 24 Aug 01 05:22:42 PM PDT 24 2036278776 ps
T914 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2204719817 Aug 01 05:22:38 PM PDT 24 Aug 01 05:22:40 PM PDT 24 2046700290 ps
T915 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3681770150 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:28 PM PDT 24 4362294671 ps
T916 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2375916277 Aug 01 05:22:21 PM PDT 24 Aug 01 05:22:25 PM PDT 24 6114428555 ps
T917 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2012558258 Aug 01 05:22:24 PM PDT 24 Aug 01 05:23:08 PM PDT 24 22232086939 ps
T918 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2435285299 Aug 01 05:22:25 PM PDT 24 Aug 01 05:22:30 PM PDT 24 2262085144 ps

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3070543096
Short name T5
Test name
Test status
Simulation time 41908349176 ps
CPU time 52.6 seconds
Started Aug 01 05:25:21 PM PDT 24
Finished Aug 01 05:26:13 PM PDT 24
Peak memory 201108 kb
Host smart-0c404faf-4a4b-422a-aaf6-74fac25697d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070543096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3070543096
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.644409860
Short name T45
Test name
Test status
Simulation time 351428863636 ps
CPU time 73.26 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:25:52 PM PDT 24
Peak memory 209444 kb
Host smart-36bf9508-c41c-456a-9b6a-8f1fbf0430e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644409860 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.644409860
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.663815264
Short name T22
Test name
Test status
Simulation time 99259198220 ps
CPU time 46.2 seconds
Started Aug 01 05:26:32 PM PDT 24
Finished Aug 01 05:27:19 PM PDT 24
Peak memory 209440 kb
Host smart-6258e945-4802-403e-bf36-e21bde1bc227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663815264 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.663815264
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.651226056
Short name T12
Test name
Test status
Simulation time 105147259330 ps
CPU time 70.13 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:25:50 PM PDT 24
Peak memory 200908 kb
Host smart-63e8772a-7335-4021-88df-c7921b568f5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651226056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_combo_detect.651226056
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.93048020
Short name T35
Test name
Test status
Simulation time 89874916973 ps
CPU time 106.95 seconds
Started Aug 01 05:25:25 PM PDT 24
Finished Aug 01 05:27:12 PM PDT 24
Peak memory 217628 kb
Host smart-2a5909cc-ca51-4541-a96c-1fd300e430b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93048020 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.93048020
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1431954737
Short name T102
Test name
Test status
Simulation time 35195225436 ps
CPU time 5.49 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:23:59 PM PDT 24
Peak memory 200788 kb
Host smart-2395dae7-6602-459b-ab8c-05d1669b5151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431954737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1431954737
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3760672201
Short name T257
Test name
Test status
Simulation time 108039798877 ps
CPU time 83.5 seconds
Started Aug 01 05:25:07 PM PDT 24
Finished Aug 01 05:26:31 PM PDT 24
Peak memory 213620 kb
Host smart-4c379e7d-d974-4b0b-bc86-0024684189b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760672201 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3760672201
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3470825297
Short name T1
Test name
Test status
Simulation time 69230523438 ps
CPU time 46.16 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 201128 kb
Host smart-f55a2ca1-5cce-4135-bf75-c0074bbd22f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470825297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.3470825297
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.601429139
Short name T75
Test name
Test status
Simulation time 67789461454 ps
CPU time 12.25 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:58 PM PDT 24
Peak memory 201196 kb
Host smart-65aba26f-55d2-43e0-bc22-397f3f824787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601429139 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.601429139
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.753798758
Short name T78
Test name
Test status
Simulation time 44597408930 ps
CPU time 12.64 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:34 PM PDT 24
Peak memory 201740 kb
Host smart-16d92fbd-28a3-400e-9801-2081f6bdcb0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753798758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_tl_intg_err.753798758
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.4195882576
Short name T183
Test name
Test status
Simulation time 62859254239 ps
CPU time 145.55 seconds
Started Aug 01 05:24:49 PM PDT 24
Finished Aug 01 05:27:14 PM PDT 24
Peak memory 209392 kb
Host smart-d05fca8d-bf4a-4ea6-8322-c978362fb253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195882576 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.4195882576
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1839912147
Short name T172
Test name
Test status
Simulation time 125928407346 ps
CPU time 153.49 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:26:28 PM PDT 24
Peak memory 201072 kb
Host smart-5e95686f-3c9c-40de-98e1-1e6c020351b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839912147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1839912147
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3483464290
Short name T54
Test name
Test status
Simulation time 39575023113 ps
CPU time 21.14 seconds
Started Aug 01 05:23:53 PM PDT 24
Finished Aug 01 05:24:14 PM PDT 24
Peak memory 200792 kb
Host smart-8d21c60f-5776-495f-9c8c-d8d5c6a359ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483464290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3483464290
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2052532922
Short name T4
Test name
Test status
Simulation time 160901885003 ps
CPU time 219.16 seconds
Started Aug 01 05:26:45 PM PDT 24
Finished Aug 01 05:30:24 PM PDT 24
Peak memory 201092 kb
Host smart-52d2055a-b270-4228-9f09-97bb25e8e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052532922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2052532922
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3463816247
Short name T51
Test name
Test status
Simulation time 22010015103 ps
CPU time 53.99 seconds
Started Aug 01 05:23:53 PM PDT 24
Finished Aug 01 05:24:47 PM PDT 24
Peak memory 220200 kb
Host smart-b3cfe28f-56f5-4165-819b-ec7d5797fef3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463816247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3463816247
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1417868077
Short name T161
Test name
Test status
Simulation time 58376587757 ps
CPU time 147.13 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:29:07 PM PDT 24
Peak memory 217452 kb
Host smart-f105e5bb-ae3b-482d-8496-79d1f6ab99d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417868077 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.1417868077
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4280700903
Short name T2
Test name
Test status
Simulation time 27621509762 ps
CPU time 72.41 seconds
Started Aug 01 05:25:23 PM PDT 24
Finished Aug 01 05:26:35 PM PDT 24
Peak memory 209424 kb
Host smart-a3aedf0f-6d04-4ffa-b7fb-18369ee44101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280700903 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.4280700903
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2191462927
Short name T284
Test name
Test status
Simulation time 41886102701 ps
CPU time 98.47 seconds
Started Aug 01 05:24:52 PM PDT 24
Finished Aug 01 05:26:30 PM PDT 24
Peak memory 201008 kb
Host smart-7658f25a-5350-4dcd-bb2d-4b989e26d6ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191462927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2191462927
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1553241190
Short name T213
Test name
Test status
Simulation time 3852988512 ps
CPU time 3 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200736 kb
Host smart-de649116-7339-4b01-8ab6-5dd2ba5f49c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553241190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1553241190
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1616999179
Short name T169
Test name
Test status
Simulation time 170298394963 ps
CPU time 108.34 seconds
Started Aug 01 05:26:25 PM PDT 24
Finished Aug 01 05:28:14 PM PDT 24
Peak memory 201076 kb
Host smart-6a97d960-229d-43ed-a7d6-46150b70ef18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616999179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1616999179
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.412267289
Short name T268
Test name
Test status
Simulation time 124109044289 ps
CPU time 82.33 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:26:56 PM PDT 24
Peak memory 201068 kb
Host smart-944ebcbf-2ee7-4514-9fb9-4d3dc6557ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412267289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_wi
th_pre_cond.412267289
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2702501371
Short name T125
Test name
Test status
Simulation time 53147991802 ps
CPU time 116.88 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:27:54 PM PDT 24
Peak memory 209404 kb
Host smart-7a4b929b-c5e5-4cfb-8e0f-40aa8e6952f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702501371 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2702501371
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3938067589
Short name T47
Test name
Test status
Simulation time 39635820877 ps
CPU time 87.18 seconds
Started Aug 01 05:26:04 PM PDT 24
Finished Aug 01 05:27:32 PM PDT 24
Peak memory 209412 kb
Host smart-891f839a-b234-44c6-bfc6-b07e2cd0b790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938067589 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3938067589
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2132453810
Short name T85
Test name
Test status
Simulation time 2062975343 ps
CPU time 6.39 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201412 kb
Host smart-87e14c16-abe7-4336-9dd6-43adafabf297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132453810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.2132453810
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3282811905
Short name T76
Test name
Test status
Simulation time 2491472582 ps
CPU time 4.31 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:30 PM PDT 24
Peak memory 209892 kb
Host smart-b55d0b60-6af8-43cd-bd45-6a4d108b8440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282811905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.3282811905
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.873293042
Short name T187
Test name
Test status
Simulation time 129796820290 ps
CPU time 92.01 seconds
Started Aug 01 05:23:53 PM PDT 24
Finished Aug 01 05:25:25 PM PDT 24
Peak memory 209516 kb
Host smart-65e19dbd-7268-4e0d-a3f9-677273d81ae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873293042 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.873293042
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1640393348
Short name T118
Test name
Test status
Simulation time 102461343904 ps
CPU time 250.47 seconds
Started Aug 01 05:24:30 PM PDT 24
Finished Aug 01 05:28:41 PM PDT 24
Peak memory 201052 kb
Host smart-30ca32de-58d7-4b84-87e4-8b253d3034a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640393348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.1640393348
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3928011116
Short name T178
Test name
Test status
Simulation time 94374446863 ps
CPU time 67.45 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:26:52 PM PDT 24
Peak memory 217176 kb
Host smart-ca2d3226-3d89-4f20-8aa9-b76209d90f31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928011116 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3928011116
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2762755692
Short name T344
Test name
Test status
Simulation time 2059654301 ps
CPU time 4.83 seconds
Started Aug 01 05:22:32 PM PDT 24
Finished Aug 01 05:22:37 PM PDT 24
Peak memory 201336 kb
Host smart-39b644c7-353b-4538-a97b-9c96bd2f71b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762755692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.2762755692
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1046083933
Short name T280
Test name
Test status
Simulation time 49529261798 ps
CPU time 32.1 seconds
Started Aug 01 05:26:45 PM PDT 24
Finished Aug 01 05:27:17 PM PDT 24
Peak memory 201128 kb
Host smart-bbb9163b-2740-45f9-a13a-1efe469dbeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046083933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.1046083933
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3552042938
Short name T224
Test name
Test status
Simulation time 125723698674 ps
CPU time 30.52 seconds
Started Aug 01 05:24:04 PM PDT 24
Finished Aug 01 05:24:35 PM PDT 24
Peak memory 217572 kb
Host smart-104a5ba9-022e-4175-906e-2a7c901351b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552042938 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.3552042938
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.2823924304
Short name T217
Test name
Test status
Simulation time 2029941233 ps
CPU time 1.81 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:38 PM PDT 24
Peak memory 200792 kb
Host smart-df73b8ff-e45e-43da-8e67-80d13a03181a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823924304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.2823924304
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3521210456
Short name T423
Test name
Test status
Simulation time 6562252937 ps
CPU time 1.85 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:48 PM PDT 24
Peak memory 200860 kb
Host smart-a66b7bf0-19b9-4ed7-922d-b695b0bf0866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521210456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.3521210456
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3614283225
Short name T303
Test name
Test status
Simulation time 172965714129 ps
CPU time 102.27 seconds
Started Aug 01 05:25:59 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 201096 kb
Host smart-073481a1-77e0-4cc6-b96d-d5426bf9f134
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614283225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.3614283225
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.4131198753
Short name T158
Test name
Test status
Simulation time 68725731088 ps
CPU time 166.61 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:27:16 PM PDT 24
Peak memory 200820 kb
Host smart-98b041fa-ddcd-4f5b-8be6-6137b78664a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131198753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.4131198753
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1106311111
Short name T353
Test name
Test status
Simulation time 85454682796 ps
CPU time 106.3 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:27:43 PM PDT 24
Peak memory 201072 kb
Host smart-710f7a46-3c08-4ff3-8f3c-73cf7f5d9844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106311111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.1106311111
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2981256290
Short name T124
Test name
Test status
Simulation time 119806922350 ps
CPU time 148.9 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:26:56 PM PDT 24
Peak memory 210928 kb
Host smart-573ca919-68c8-4f84-b61f-66cb24a79d71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981256290 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2981256290
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3566518606
Short name T81
Test name
Test status
Simulation time 22219734735 ps
CPU time 55.56 seconds
Started Aug 01 05:22:20 PM PDT 24
Finished Aug 01 05:23:16 PM PDT 24
Peak memory 201580 kb
Host smart-73f0e00e-c32d-456d-aabe-d2997ea6d62f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566518606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3566518606
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1525215805
Short name T289
Test name
Test status
Simulation time 250594576870 ps
CPU time 304.75 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:29:41 PM PDT 24
Peak memory 200864 kb
Host smart-ef444044-7780-48ed-bb9c-264eaffe9960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525215805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1
525215805
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.1807207053
Short name T136
Test name
Test status
Simulation time 78170428375 ps
CPU time 205.37 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:27:29 PM PDT 24
Peak memory 200952 kb
Host smart-c5928c2b-3378-4fa5-977c-16abde6d132a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807207053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.1807207053
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4199720922
Short name T360
Test name
Test status
Simulation time 66489407853 ps
CPU time 163.73 seconds
Started Aug 01 05:26:41 PM PDT 24
Finished Aug 01 05:29:25 PM PDT 24
Peak memory 201184 kb
Host smart-127f7b26-9e58-47e9-8073-f6955589ea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199720922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.4199720922
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.596039668
Short name T334
Test name
Test status
Simulation time 2783041723 ps
CPU time 7.09 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201592 kb
Host smart-05f2a45a-a77b-420b-96a3-9648ad882c82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596039668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_aliasing.596039668
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.4053869255
Short name T854
Test name
Test status
Simulation time 2405334896 ps
CPU time 4.04 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 209936 kb
Host smart-1d1055c1-9d35-4fd6-835b-3acd1debce34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053869255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.4053869255
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.1103571148
Short name T34
Test name
Test status
Simulation time 3398921158 ps
CPU time 7.89 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:26:03 PM PDT 24
Peak memory 200780 kb
Host smart-a9f40a31-c972-4022-a060-d499dd09969a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103571148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.1103571148
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3063976589
Short name T307
Test name
Test status
Simulation time 66065775346 ps
CPU time 177 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:29:34 PM PDT 24
Peak memory 200968 kb
Host smart-a4bb1942-3eee-449f-be1a-4d3ec95c5feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063976589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.3063976589
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2690786386
Short name T199
Test name
Test status
Simulation time 14852713837 ps
CPU time 10.49 seconds
Started Aug 01 05:25:38 PM PDT 24
Finished Aug 01 05:25:49 PM PDT 24
Peak memory 200860 kb
Host smart-55353728-7ff7-47eb-b48e-08a760ce9050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690786386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2690786386
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.3835285236
Short name T173
Test name
Test status
Simulation time 3103202300 ps
CPU time 3.85 seconds
Started Aug 01 05:25:40 PM PDT 24
Finished Aug 01 05:25:44 PM PDT 24
Peak memory 200892 kb
Host smart-daaf3de8-b298-47a1-a045-dd490fd3a48c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835285236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.3835285236
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1230344366
Short name T279
Test name
Test status
Simulation time 134709020927 ps
CPU time 81.6 seconds
Started Aug 01 05:24:07 PM PDT 24
Finished Aug 01 05:25:29 PM PDT 24
Peak memory 201040 kb
Host smart-dff77587-b952-4f3d-9873-04e7aced6f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230344366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.1230344366
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.4261343389
Short name T324
Test name
Test status
Simulation time 167437958422 ps
CPU time 110.8 seconds
Started Aug 01 05:25:37 PM PDT 24
Finished Aug 01 05:27:28 PM PDT 24
Peak memory 212908 kb
Host smart-5726750b-969d-4c9c-b283-bd3bbe097719
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261343389 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.4261343389
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2885894865
Short name T359
Test name
Test status
Simulation time 121296344851 ps
CPU time 76.56 seconds
Started Aug 01 05:24:08 PM PDT 24
Finished Aug 01 05:25:24 PM PDT 24
Peak memory 201108 kb
Host smart-784069c4-3360-4bf8-9993-9c5e267629bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885894865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.2885894865
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.825808542
Short name T214
Test name
Test status
Simulation time 97370932200 ps
CPU time 62.15 seconds
Started Aug 01 05:26:50 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 201148 kb
Host smart-8e72839e-53e6-428f-adbd-a723ea9719d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825808542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_wi
th_pre_cond.825808542
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3686201629
Short name T365
Test name
Test status
Simulation time 72603584809 ps
CPU time 174.02 seconds
Started Aug 01 05:26:51 PM PDT 24
Finished Aug 01 05:29:46 PM PDT 24
Peak memory 201028 kb
Host smart-33d82e58-f025-41ac-9f24-a4e986456523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686201629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.3686201629
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4161305873
Short name T806
Test name
Test status
Simulation time 7597615411 ps
CPU time 3.43 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201540 kb
Host smart-d6007288-3b42-4f10-9529-e3796564eaef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161305873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.4161305873
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2012510695
Short name T384
Test name
Test status
Simulation time 66326991968 ps
CPU time 32.37 seconds
Started Aug 01 05:23:52 PM PDT 24
Finished Aug 01 05:24:24 PM PDT 24
Peak memory 200988 kb
Host smart-69e592b5-3aff-405b-9bac-de49f9e732e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012510695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2012510695
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2777940080
Short name T119
Test name
Test status
Simulation time 138075890593 ps
CPU time 72.22 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:25:51 PM PDT 24
Peak memory 201156 kb
Host smart-aef2086d-25fb-42f8-a98e-4344d49878c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777940080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.2777940080
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1241163992
Short name T369
Test name
Test status
Simulation time 42881863890 ps
CPU time 16.58 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:25:04 PM PDT 24
Peak memory 201068 kb
Host smart-3e8c796b-fffe-45a9-947b-00f8ed85d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241163992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.1241163992
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.83402075
Short name T390
Test name
Test status
Simulation time 3811612414686 ps
CPU time 146.25 seconds
Started Aug 01 05:24:58 PM PDT 24
Finished Aug 01 05:27:25 PM PDT 24
Peak memory 200068 kb
Host smart-fee672d8-8c6c-41b7-b0a1-1691f1d78593
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83402075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_ultra_low_pwr.83402075
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.288689664
Short name T702
Test name
Test status
Simulation time 106166764628 ps
CPU time 265.25 seconds
Started Aug 01 05:25:21 PM PDT 24
Finished Aug 01 05:29:46 PM PDT 24
Peak memory 200948 kb
Host smart-62742161-0169-4ca4-84bc-3276326022a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288689664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_combo_detect.288689664
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1880153715
Short name T382
Test name
Test status
Simulation time 172772395192 ps
CPU time 232.86 seconds
Started Aug 01 05:26:32 PM PDT 24
Finished Aug 01 05:30:25 PM PDT 24
Peak memory 201096 kb
Host smart-c3afea5e-5e8c-4de7-b871-07829f1a14df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880153715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1880153715
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.585167239
Short name T163
Test name
Test status
Simulation time 548895640391 ps
CPU time 59.97 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:27:37 PM PDT 24
Peak memory 217636 kb
Host smart-1aa1ecb6-14f4-45dd-9f27-af5c3d64024f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585167239 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.585167239
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.75485515
Short name T373
Test name
Test status
Simulation time 61040204601 ps
CPU time 78.12 seconds
Started Aug 01 05:26:43 PM PDT 24
Finished Aug 01 05:28:02 PM PDT 24
Peak memory 201188 kb
Host smart-4986803a-b699-4e50-a67f-73043b400253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75485515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_wit
h_pre_cond.75485515
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.4085631542
Short name T358
Test name
Test status
Simulation time 90786052349 ps
CPU time 218.83 seconds
Started Aug 01 05:26:51 PM PDT 24
Finished Aug 01 05:30:30 PM PDT 24
Peak memory 201060 kb
Host smart-59b2bf4b-dab0-4d1c-b69c-567c4f469b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085631542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.4085631542
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1289339563
Short name T362
Test name
Test status
Simulation time 176698072061 ps
CPU time 104.19 seconds
Started Aug 01 05:26:44 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 201156 kb
Host smart-068dd4bc-fa0a-4518-bdbe-04dd071a0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289339563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.1289339563
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3258052620
Short name T52
Test name
Test status
Simulation time 53218031169 ps
CPU time 45.72 seconds
Started Aug 01 05:26:50 PM PDT 24
Finished Aug 01 05:27:36 PM PDT 24
Peak memory 201084 kb
Host smart-d9f3d623-1c68-42a7-84ba-60be9502b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258052620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.3258052620
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1271923243
Short name T55
Test name
Test status
Simulation time 48612281062 ps
CPU time 135.58 seconds
Started Aug 01 05:26:49 PM PDT 24
Finished Aug 01 05:29:04 PM PDT 24
Peak memory 201128 kb
Host smart-fcced644-aa73-4e47-be23-08770ec0d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271923243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1271923243
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1361422770
Short name T803
Test name
Test status
Simulation time 2634929766 ps
CPU time 3.2 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201628 kb
Host smart-9941f425-a962-4ac5-b982-b3ca018a9a3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361422770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.1361422770
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4187982981
Short name T895
Test name
Test status
Simulation time 38310743987 ps
CPU time 87.38 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:23:55 PM PDT 24
Peak memory 201612 kb
Host smart-490d5645-7ab3-4d00-97fa-cdf3c6ba5faa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187982981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.4187982981
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1373611857
Short name T876
Test name
Test status
Simulation time 6038015422 ps
CPU time 16.32 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:23 PM PDT 24
Peak memory 201364 kb
Host smart-2f4f107a-9dbf-4890-8ad3-c93d7afcc4bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373611857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.1373611857
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3716657743
Short name T832
Test name
Test status
Simulation time 2098784190 ps
CPU time 4.75 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:26 PM PDT 24
Peak memory 201552 kb
Host smart-e4236359-6dcb-4c18-9fb3-a85b2c824a10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716657743 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3716657743
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2611370817
Short name T814
Test name
Test status
Simulation time 2063241421 ps
CPU time 5.63 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:13 PM PDT 24
Peak memory 201316 kb
Host smart-19d9f5f1-db9e-4d29-9237-946569d5be9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611370817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.2611370817
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.849026643
Short name T802
Test name
Test status
Simulation time 2014904513 ps
CPU time 5.73 seconds
Started Aug 01 05:22:07 PM PDT 24
Finished Aug 01 05:22:13 PM PDT 24
Peak memory 201048 kb
Host smart-400a7a03-1c52-4c1d-9060-bed25f3f57b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849026643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test
.849026643
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1810372771
Short name T877
Test name
Test status
Simulation time 5406422395 ps
CPU time 4.27 seconds
Started Aug 01 05:22:27 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201620 kb
Host smart-798bb52e-c63f-4817-a481-454dfe164473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810372771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.1810372771
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3431280909
Short name T91
Test name
Test status
Simulation time 2231195625 ps
CPU time 4.8 seconds
Started Aug 01 05:22:04 PM PDT 24
Finished Aug 01 05:22:09 PM PDT 24
Peak memory 201696 kb
Host smart-e053c17c-6b10-4b2a-b7fb-fb11457efd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431280909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.3431280909
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2015960049
Short name T845
Test name
Test status
Simulation time 22312540207 ps
CPU time 31.16 seconds
Started Aug 01 05:22:05 PM PDT 24
Finished Aug 01 05:22:37 PM PDT 24
Peak memory 201544 kb
Host smart-f857e005-9fe0-42e9-9a46-9cec7bb48dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015960049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.2015960049
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3105496630
Short name T342
Test name
Test status
Simulation time 2730702117 ps
CPU time 11.14 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:41 PM PDT 24
Peak memory 201556 kb
Host smart-644e7bc6-5314-4c59-91e6-4474b1494149
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105496630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3105496630
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1877365736
Short name T337
Test name
Test status
Simulation time 20562822095 ps
CPU time 56.76 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:23:21 PM PDT 24
Peak memory 201496 kb
Host smart-75cbbec3-cfa5-464d-baea-e0ec3c55ee74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877365736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.1877365736
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1556820346
Short name T338
Test name
Test status
Simulation time 4065492656 ps
CPU time 2.27 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201332 kb
Host smart-a3ec33fc-9d1f-4f9d-8a64-1f76c2d894c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556820346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.1556820346
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.363883001
Short name T868
Test name
Test status
Simulation time 2070215112 ps
CPU time 2.82 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:24 PM PDT 24
Peak memory 201364 kb
Host smart-bce7ee9f-31a1-494c-941f-60d09c0bcfb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363883001 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.363883001
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2070950388
Short name T887
Test name
Test status
Simulation time 2049036369 ps
CPU time 2.88 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201364 kb
Host smart-f922a2b2-2c4d-4f67-b1e9-19529f815a51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070950388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2070950388
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1691462348
Short name T892
Test name
Test status
Simulation time 2032790959 ps
CPU time 2.99 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 201108 kb
Host smart-21ac94a0-d371-420d-9a9e-e7a2be19c2c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691462348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1691462348
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2415956370
Short name T902
Test name
Test status
Simulation time 22527606369 ps
CPU time 14.65 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:39 PM PDT 24
Peak memory 201724 kb
Host smart-08b12bac-0ad2-4315-b148-78165b663045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415956370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.2415956370
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2243167396
Short name T872
Test name
Test status
Simulation time 2105912868 ps
CPU time 2.26 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201468 kb
Host smart-9784d9b8-96af-492c-b343-124aec1db0b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243167396 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2243167396
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2215968787
Short name T336
Test name
Test status
Simulation time 2027730153 ps
CPU time 5.53 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:34 PM PDT 24
Peak memory 201300 kb
Host smart-c05e6f47-e893-4973-aa63-1c609bc83ba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215968787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.2215968787
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3334176255
Short name T809
Test name
Test status
Simulation time 2021016374 ps
CPU time 3.26 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 201060 kb
Host smart-a72c3790-2719-4ae6-8f24-b9e835a990ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334176255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3334176255
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1092727985
Short name T828
Test name
Test status
Simulation time 4413081842 ps
CPU time 6.06 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:35 PM PDT 24
Peak memory 201492 kb
Host smart-0e7cb0fb-42c5-4f04-80ae-afd7e2d277b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092727985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1092727985
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3428672671
Short name T906
Test name
Test status
Simulation time 2530720197 ps
CPU time 2.64 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201596 kb
Host smart-c891a319-c770-40c7-8886-f1014001b592
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428672671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.3428672671
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.4012112283
Short name T29
Test name
Test status
Simulation time 22228056650 ps
CPU time 59.18 seconds
Started Aug 01 05:22:27 PM PDT 24
Finished Aug 01 05:23:27 PM PDT 24
Peak memory 201628 kb
Host smart-17526201-fed0-4c46-9428-9f214ad3cc86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012112283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.4012112283
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3210496864
Short name T911
Test name
Test status
Simulation time 2113633026 ps
CPU time 3.67 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 209772 kb
Host smart-fe799ecd-d8b3-4a87-ae60-9eaabcd18a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210496864 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3210496864
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1232590567
Short name T857
Test name
Test status
Simulation time 2035788884 ps
CPU time 6.02 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201452 kb
Host smart-c1634dcd-efa2-4df5-9509-a53723bbe62a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232590567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1232590567
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2561488160
Short name T808
Test name
Test status
Simulation time 2013312917 ps
CPU time 5.6 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:35 PM PDT 24
Peak memory 200920 kb
Host smart-e9de69aa-1b10-4a32-b04e-3cbb58799c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561488160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.2561488160
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.7068711
Short name T904
Test name
Test status
Simulation time 10180301533 ps
CPU time 18.81 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:43 PM PDT 24
Peak memory 201796 kb
Host smart-3faafc79-3842-4cb7-874c-ff3a91451695
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7068711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=s
ysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
ysrst_ctrl_same_csr_outstanding.7068711
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2435285299
Short name T918
Test name
Test status
Simulation time 2262085144 ps
CPU time 4.53 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:30 PM PDT 24
Peak memory 201656 kb
Host smart-3bbb2dd4-1d4d-41ef-8085-766b5b354911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435285299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2435285299
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2807273300
Short name T886
Test name
Test status
Simulation time 22238404023 ps
CPU time 17.22 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:47 PM PDT 24
Peak memory 201584 kb
Host smart-14c16b2f-6568-4922-811c-cd971c8b584a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807273300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.2807273300
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3186421724
Short name T875
Test name
Test status
Simulation time 2034874738 ps
CPU time 5.46 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201464 kb
Host smart-5c10333e-df6d-4b4f-ad89-75528a5f0691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186421724 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3186421724
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1163294277
Short name T870
Test name
Test status
Simulation time 2033395558 ps
CPU time 5.73 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201356 kb
Host smart-2501ceba-5d72-46f0-95a3-e7fb39cbdc8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163294277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.1163294277
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1874710677
Short name T838
Test name
Test status
Simulation time 2016159952 ps
CPU time 5.24 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201100 kb
Host smart-937bc2da-bf29-406e-aacc-7e64d23bcfed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874710677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.1874710677
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4000441423
Short name T840
Test name
Test status
Simulation time 4956206719 ps
CPU time 5.26 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201504 kb
Host smart-51cfa8b4-44b5-4a67-8c5f-d38cd82e3314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000441423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.4000441423
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2499596153
Short name T92
Test name
Test status
Simulation time 2200762750 ps
CPU time 2.92 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201780 kb
Host smart-6eb15580-9e50-4b03-a768-31844fea30dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499596153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2499596153
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3910434068
Short name T908
Test name
Test status
Simulation time 22529352081 ps
CPU time 27.51 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:56 PM PDT 24
Peak memory 201612 kb
Host smart-96b759f4-0947-4df1-8c2d-6705769036af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910434068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3910434068
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.929524996
Short name T863
Test name
Test status
Simulation time 2167936357 ps
CPU time 2.39 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201432 kb
Host smart-8c9a754d-9d5f-45ca-8ecb-141b5e4e39d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929524996 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.929524996
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3699476984
Short name T856
Test name
Test status
Simulation time 2061235579 ps
CPU time 3.46 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201388 kb
Host smart-76e0fb77-2d8f-455e-a293-f5b15032cb1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699476984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.3699476984
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.714724309
Short name T833
Test name
Test status
Simulation time 2084452363 ps
CPU time 1.26 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201056 kb
Host smart-8a228d45-4fad-4513-8e60-1b26db009dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714724309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.714724309
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3681770150
Short name T915
Test name
Test status
Simulation time 4362294671 ps
CPU time 2.93 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201484 kb
Host smart-3e02c205-d83d-4dac-9134-edb40fad62d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681770150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3681770150
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1981193454
Short name T87
Test name
Test status
Simulation time 2035178359 ps
CPU time 6.59 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201640 kb
Host smart-d7f38228-11ee-4cc6-83a3-abf4e0629986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981193454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.1981193454
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1671583446
Short name T379
Test name
Test status
Simulation time 42507990576 ps
CPU time 31.95 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:55 PM PDT 24
Peak memory 201620 kb
Host smart-f064186a-2fd8-482c-8445-0da227589ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671583446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.1671583446
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3720488197
Short name T884
Test name
Test status
Simulation time 2053703364 ps
CPU time 6.09 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201400 kb
Host smart-69f40341-3e99-400a-9771-11f9ea02d0e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720488197 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3720488197
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3667711355
Short name T801
Test name
Test status
Simulation time 2026490106 ps
CPU time 1.89 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:30 PM PDT 24
Peak memory 201100 kb
Host smart-1720d01c-5ccf-4110-875c-22268a7b6f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667711355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3667711355
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4195387657
Short name T18
Test name
Test status
Simulation time 7136291732 ps
CPU time 12.99 seconds
Started Aug 01 05:22:27 PM PDT 24
Finished Aug 01 05:22:40 PM PDT 24
Peak memory 201596 kb
Host smart-6ad8208a-ec16-43ad-9265-87f8efc57969
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195387657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.4195387657
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2704934780
Short name T859
Test name
Test status
Simulation time 2080855893 ps
CPU time 7.01 seconds
Started Aug 01 05:22:31 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 201576 kb
Host smart-2d57a86c-995e-457f-b9ec-bb1e2567bd73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704934780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2704934780
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1028151035
Short name T865
Test name
Test status
Simulation time 42490326986 ps
CPU time 69.78 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:23:35 PM PDT 24
Peak memory 201728 kb
Host smart-dade2787-cf93-4f64-a280-d5e52a04e4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028151035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1028151035
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3276447817
Short name T851
Test name
Test status
Simulation time 2094509702 ps
CPU time 2.23 seconds
Started Aug 01 05:22:33 PM PDT 24
Finished Aug 01 05:22:36 PM PDT 24
Peak memory 201356 kb
Host smart-939618ae-1e70-4b60-9d22-1a40f3b4dc50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276447817 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3276447817
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1229462770
Short name T896
Test name
Test status
Simulation time 2064564066 ps
CPU time 2.1 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 201448 kb
Host smart-0f598e23-eb52-416c-9277-00a5e95233ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229462770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1229462770
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2794292667
Short name T858
Test name
Test status
Simulation time 2036138378 ps
CPU time 2.05 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201388 kb
Host smart-0c9264c8-f7bd-4247-adae-8066d6ef4fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794292667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.2794292667
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3425977858
Short name T28
Test name
Test status
Simulation time 4981923109 ps
CPU time 3.02 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201508 kb
Host smart-8d9b08d6-0a9e-4793-a326-dc0c1aa28d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425977858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.3425977858
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3575381589
Short name T93
Test name
Test status
Simulation time 2166823728 ps
CPU time 2.38 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:26 PM PDT 24
Peak memory 201740 kb
Host smart-959eac53-7ce7-4b62-98a2-0798c3252209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575381589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3575381589
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2447431269
Short name T825
Test name
Test status
Simulation time 22294314797 ps
CPU time 30.79 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:56 PM PDT 24
Peak memory 201600 kb
Host smart-dba95ae0-0c2c-4a2d-ae40-aeba816082de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447431269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.2447431269
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3021952091
Short name T836
Test name
Test status
Simulation time 2109405923 ps
CPU time 4.31 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:30 PM PDT 24
Peak memory 201412 kb
Host smart-65945a7a-6f90-46e9-80f0-b02cd90e2427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021952091 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3021952091
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3292172532
Short name T341
Test name
Test status
Simulation time 2053801176 ps
CPU time 6.02 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:35 PM PDT 24
Peak memory 201280 kb
Host smart-b70fa93a-8cd8-4b57-94d4-ce5b7f98d495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292172532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3292172532
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1379269236
Short name T867
Test name
Test status
Simulation time 2014891842 ps
CPU time 3.71 seconds
Started Aug 01 05:22:27 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201012 kb
Host smart-da2317fd-593c-4fe3-9bb9-96e4952857f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379269236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1379269236
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2700992294
Short name T345
Test name
Test status
Simulation time 7511746556 ps
CPU time 10.1 seconds
Started Aug 01 05:22:32 PM PDT 24
Finished Aug 01 05:22:42 PM PDT 24
Peak memory 200852 kb
Host smart-14a0a539-1795-4f18-a9f0-d87aab0b6157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700992294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2700992294
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1930904840
Short name T83
Test name
Test status
Simulation time 2019217496 ps
CPU time 6.38 seconds
Started Aug 01 05:22:31 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 201520 kb
Host smart-41bc4d90-aa5b-4181-a242-d59e2f08ca94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930904840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1930904840
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2012558258
Short name T917
Test name
Test status
Simulation time 22232086939 ps
CPU time 44.32 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:23:08 PM PDT 24
Peak memory 201580 kb
Host smart-6383d878-82bb-4920-83b1-c975241415e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012558258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.2012558258
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2372455046
Short name T909
Test name
Test status
Simulation time 2058788978 ps
CPU time 3.48 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201340 kb
Host smart-95f56bc0-4a48-4f61-b103-186724504410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372455046 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2372455046
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2127680010
Short name T860
Test name
Test status
Simulation time 2043658641 ps
CPU time 6.24 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201428 kb
Host smart-fb2938ca-3b31-424e-80ad-5143a989be4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127680010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.2127680010
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.961118818
Short name T818
Test name
Test status
Simulation time 2012474246 ps
CPU time 5.66 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:34 PM PDT 24
Peak memory 201040 kb
Host smart-8c7b894e-b322-4232-bb2d-d66008ea7c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961118818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_tes
t.961118818
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3282609498
Short name T855
Test name
Test status
Simulation time 5411767811 ps
CPU time 4.2 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:34 PM PDT 24
Peak memory 201592 kb
Host smart-e496bf70-191a-46c2-8690-a1b80fbaea8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282609498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.3282609498
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1794464474
Short name T830
Test name
Test status
Simulation time 2030895927 ps
CPU time 6.63 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:35 PM PDT 24
Peak memory 201576 kb
Host smart-a5213799-941c-4d49-872e-7112bbe38a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794464474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1794464474
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3707840134
Short name T380
Test name
Test status
Simulation time 42414616083 ps
CPU time 59.16 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:23:25 PM PDT 24
Peak memory 201720 kb
Host smart-5203e180-3d4c-4337-a95f-22286d7d23ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707840134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3707840134
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2901529575
Short name T899
Test name
Test status
Simulation time 2099134914 ps
CPU time 2.4 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201400 kb
Host smart-f64a4150-e7e9-474e-9bc7-01b0ab8057b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901529575 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2901529575
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.734952856
Short name T888
Test name
Test status
Simulation time 2050360759 ps
CPU time 6.1 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:22:35 PM PDT 24
Peak memory 201344 kb
Host smart-640b3607-a331-46cf-91d8-54bb8e0d2599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734952856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_r
w.734952856
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1514859636
Short name T794
Test name
Test status
Simulation time 2076297704 ps
CPU time 1.39 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201160 kb
Host smart-9ec03ac3-8d69-4920-9978-7bbc5eac122f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514859636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.1514859636
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1928677724
Short name T19
Test name
Test status
Simulation time 9239871376 ps
CPU time 37.14 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:23:07 PM PDT 24
Peak memory 201592 kb
Host smart-542c3c63-bd93-42ee-8edf-b52fb39925f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928677724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.1928677724
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.342897824
Short name T898
Test name
Test status
Simulation time 2240114677 ps
CPU time 4.89 seconds
Started Aug 01 05:22:33 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 201656 kb
Host smart-18af2d6a-09fb-4c1a-b7d1-ea7116d46ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342897824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_error
s.342897824
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1914811560
Short name T901
Test name
Test status
Simulation time 42373875219 ps
CPU time 104.88 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:24:15 PM PDT 24
Peak memory 201644 kb
Host smart-2fb46830-41a7-4bd8-85a0-1464996a86a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914811560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.1914811560
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.353710425
Short name T907
Test name
Test status
Simulation time 2045832007 ps
CPU time 5.87 seconds
Started Aug 01 05:22:32 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 200568 kb
Host smart-90844875-238f-4733-b171-a867c85b58d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353710425 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.353710425
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3511436163
Short name T84
Test name
Test status
Simulation time 2053992010 ps
CPU time 3.55 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201460 kb
Host smart-f0813681-3d6c-4624-b8ea-2e3431cbb2a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511436163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.3511436163
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1403233180
Short name T824
Test name
Test status
Simulation time 2043665055 ps
CPU time 1.81 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201080 kb
Host smart-b753da78-519a-4d07-af54-10e51cd46800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403233180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.1403233180
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1954106049
Short name T885
Test name
Test status
Simulation time 10649635841 ps
CPU time 18.43 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:46 PM PDT 24
Peak memory 201724 kb
Host smart-da7b0653-b6dc-4225-9086-a28db3b8687b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954106049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1954106049
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1644105804
Short name T853
Test name
Test status
Simulation time 2024668299 ps
CPU time 6.46 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:34 PM PDT 24
Peak memory 201636 kb
Host smart-f94174e0-ad14-4bf0-b865-7c92d3c41c15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644105804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.1644105804
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.850287140
Short name T834
Test name
Test status
Simulation time 22229114151 ps
CPU time 32.9 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:58 PM PDT 24
Peak memory 201536 kb
Host smart-1170be07-9dd0-473b-84fd-04efece11e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850287140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_tl_intg_err.850287140
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3161484746
Short name T897
Test name
Test status
Simulation time 9069385935 ps
CPU time 11.48 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201628 kb
Host smart-bd1c9d4d-1934-4a90-9e4f-f0d37626c422
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161484746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.3161484746
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2375916277
Short name T916
Test name
Test status
Simulation time 6114428555 ps
CPU time 3.81 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201368 kb
Host smart-04dae06c-e438-4a57-8c29-da1bfbce9c82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375916277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.2375916277
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1085147469
Short name T831
Test name
Test status
Simulation time 2141265610 ps
CPU time 3.01 seconds
Started Aug 01 05:22:20 PM PDT 24
Finished Aug 01 05:22:23 PM PDT 24
Peak memory 201344 kb
Host smart-4816531a-a101-4fd2-8f56-29bf05406b3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085147469 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1085147469
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2708637186
Short name T346
Test name
Test status
Simulation time 2048322906 ps
CPU time 5.72 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201416 kb
Host smart-fa9176e5-4afa-4eeb-ae28-388ff0467c73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708637186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.2708637186
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.115240188
Short name T891
Test name
Test status
Simulation time 2046086832 ps
CPU time 1.85 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201172 kb
Host smart-9e0a9b92-e2d5-45fe-89f0-3a4831002107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115240188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test
.115240188
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4115674778
Short name T826
Test name
Test status
Simulation time 4889220624 ps
CPU time 18.51 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:42 PM PDT 24
Peak memory 201676 kb
Host smart-e9bdccf5-29ad-42c1-8c01-f1195d31c5b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115674778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.4115674778
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.4208202925
Short name T88
Test name
Test status
Simulation time 2054437069 ps
CPU time 6.32 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201672 kb
Host smart-f6d7247b-16fd-4a2c-b02a-57e05960c5de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208202925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.4208202925
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3915313051
Short name T850
Test name
Test status
Simulation time 22276043024 ps
CPU time 16.8 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 201616 kb
Host smart-4d7dd07c-bdaa-4374-8780-c3dca6158eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915313051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.3915313051
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2291089628
Short name T817
Test name
Test status
Simulation time 2021707178 ps
CPU time 3.43 seconds
Started Aug 01 05:22:28 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201148 kb
Host smart-172f6140-4bde-40bb-b883-4aa7a903c806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291089628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2291089628
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3143642805
Short name T882
Test name
Test status
Simulation time 2032504135 ps
CPU time 1.9 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201104 kb
Host smart-adbbc951-70b8-4930-83ea-480e73db21a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143642805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.3143642805
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3375847017
Short name T798
Test name
Test status
Simulation time 2009538647 ps
CPU time 5.69 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:32 PM PDT 24
Peak memory 201104 kb
Host smart-e51f029c-b755-4cc8-b0b9-c98aae56c8d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375847017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.3375847017
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.40198380
Short name T894
Test name
Test status
Simulation time 2014712920 ps
CPU time 5.54 seconds
Started Aug 01 05:22:35 PM PDT 24
Finished Aug 01 05:22:41 PM PDT 24
Peak memory 201104 kb
Host smart-84999cd3-fb8d-4186-b47a-f7388e2bcaf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40198380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test
.40198380
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4247918097
Short name T912
Test name
Test status
Simulation time 2025624584 ps
CPU time 1.99 seconds
Started Aug 01 05:22:36 PM PDT 24
Finished Aug 01 05:22:39 PM PDT 24
Peak memory 201232 kb
Host smart-ae1786fe-bc9d-4c2d-93ab-00bd3cbe223a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247918097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.4247918097
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.21108582
Short name T864
Test name
Test status
Simulation time 2026189629 ps
CPU time 2.95 seconds
Started Aug 01 05:22:35 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 201072 kb
Host smart-6b66813d-30ac-45f0-a109-dc515a3ea487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test
.21108582
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.951557648
Short name T839
Test name
Test status
Simulation time 2012957637 ps
CPU time 5.87 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:22:55 PM PDT 24
Peak memory 201232 kb
Host smart-955dd6c3-8781-4754-adbd-0bda8529ac3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951557648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_tes
t.951557648
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4099630969
Short name T805
Test name
Test status
Simulation time 2013368710 ps
CPU time 4.88 seconds
Started Aug 01 05:22:40 PM PDT 24
Finished Aug 01 05:22:45 PM PDT 24
Peak memory 200388 kb
Host smart-ed673c07-e714-4d61-bb80-5a41085c73f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099630969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.4099630969
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1843026453
Short name T822
Test name
Test status
Simulation time 2014654757 ps
CPU time 5.56 seconds
Started Aug 01 05:22:38 PM PDT 24
Finished Aug 01 05:22:43 PM PDT 24
Peak memory 201096 kb
Host smart-818ef629-b867-4338-af42-ef4657222018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843026453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.1843026453
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1054898357
Short name T799
Test name
Test status
Simulation time 2016615154 ps
CPU time 5.47 seconds
Started Aug 01 05:22:41 PM PDT 24
Finished Aug 01 05:22:47 PM PDT 24
Peak memory 201352 kb
Host smart-a2adda68-bc8d-4666-a61d-123d5981ec5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054898357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.1054898357
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3243046076
Short name T27
Test name
Test status
Simulation time 2460488861 ps
CPU time 8.4 seconds
Started Aug 01 05:22:20 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 201620 kb
Host smart-933fa917-ad45-402f-a24d-c669b6fba075
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243046076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.3243046076
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1837342820
Short name T879
Test name
Test status
Simulation time 38347629055 ps
CPU time 122.99 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:24:25 PM PDT 24
Peak memory 201652 kb
Host smart-8c8732f0-0824-4497-890f-6f20f94a5f7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837342820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.1837342820
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3120947623
Short name T340
Test name
Test status
Simulation time 6065805413 ps
CPU time 4.55 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:26 PM PDT 24
Peak memory 201464 kb
Host smart-175d8a1c-2b9d-44cf-844a-0c7c6010ad50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120947623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.3120947623
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.370046249
Short name T812
Test name
Test status
Simulation time 2182974282 ps
CPU time 2.79 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201456 kb
Host smart-3ff18c02-e7bd-4e66-aebc-a3a9fb89e2b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370046249 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.370046249
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3918644013
Short name T835
Test name
Test status
Simulation time 2060136200 ps
CPU time 3.65 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:26 PM PDT 24
Peak memory 201396 kb
Host smart-619ed513-464b-4e90-82b5-2ccc5c282cc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918644013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.3918644013
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2181222692
Short name T893
Test name
Test status
Simulation time 2020544953 ps
CPU time 3.07 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:24 PM PDT 24
Peak memory 201232 kb
Host smart-f1e525de-99ca-41cd-adef-f487a59765de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181222692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.2181222692
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2575418942
Short name T861
Test name
Test status
Simulation time 9708711074 ps
CPU time 24.2 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:50 PM PDT 24
Peak memory 201628 kb
Host smart-6016e70b-9ad5-4029-8e06-41f53db0f858
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575418942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2575418942
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1187833813
Short name T847
Test name
Test status
Simulation time 22348270540 ps
CPU time 11.77 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201584 kb
Host smart-a60f251a-b31a-439b-a18f-5a23d6ec6632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187833813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.1187833813
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3965185223
Short name T823
Test name
Test status
Simulation time 2032135501 ps
CPU time 1.82 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:22:48 PM PDT 24
Peak memory 201196 kb
Host smart-b5d88e57-d271-4520-9ada-b690ba1f764f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965185223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3965185223
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1510396290
Short name T841
Test name
Test status
Simulation time 2047861844 ps
CPU time 1.42 seconds
Started Aug 01 05:22:37 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 201340 kb
Host smart-94d2ad59-b865-4366-8121-6931754a2201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510396290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.1510396290
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3086477929
Short name T905
Test name
Test status
Simulation time 2015994132 ps
CPU time 5.3 seconds
Started Aug 01 05:22:39 PM PDT 24
Finished Aug 01 05:22:44 PM PDT 24
Peak memory 201168 kb
Host smart-6086d156-7672-4b7c-b761-af00fa558d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086477929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3086477929
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4117666071
Short name T871
Test name
Test status
Simulation time 2011624171 ps
CPU time 5.79 seconds
Started Aug 01 05:22:37 PM PDT 24
Finished Aug 01 05:22:43 PM PDT 24
Peak memory 201152 kb
Host smart-e516ba1f-878e-469f-8dfc-45d63c63adea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117666071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.4117666071
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3834474011
Short name T913
Test name
Test status
Simulation time 2036278776 ps
CPU time 1.89 seconds
Started Aug 01 05:22:40 PM PDT 24
Finished Aug 01 05:22:42 PM PDT 24
Peak memory 201204 kb
Host smart-98c47590-c58a-47d3-b438-0fa99641ba9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834474011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.3834474011
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3326818107
Short name T796
Test name
Test status
Simulation time 2016267117 ps
CPU time 3.02 seconds
Started Aug 01 05:22:41 PM PDT 24
Finished Aug 01 05:22:44 PM PDT 24
Peak memory 201192 kb
Host smart-b46f9e38-e52b-4499-aa39-09044e15f21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326818107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.3326818107
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.639744938
Short name T820
Test name
Test status
Simulation time 2042841041 ps
CPU time 1.87 seconds
Started Aug 01 05:22:39 PM PDT 24
Finished Aug 01 05:22:41 PM PDT 24
Peak memory 201008 kb
Host smart-9cc4a705-0b1f-4207-ab6c-85b78610dcd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639744938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.639744938
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3433452092
Short name T837
Test name
Test status
Simulation time 2014338418 ps
CPU time 5.81 seconds
Started Aug 01 05:22:39 PM PDT 24
Finished Aug 01 05:22:45 PM PDT 24
Peak memory 201216 kb
Host smart-4c80de76-b8e6-4daa-b822-038ac0322769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433452092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.3433452092
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2079150536
Short name T843
Test name
Test status
Simulation time 2020556641 ps
CPU time 3.21 seconds
Started Aug 01 05:22:40 PM PDT 24
Finished Aug 01 05:22:44 PM PDT 24
Peak memory 201040 kb
Host smart-3ccf85a8-e1ba-47a9-855d-ab9a9766602b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079150536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.2079150536
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3889679036
Short name T793
Test name
Test status
Simulation time 2017321905 ps
CPU time 3.18 seconds
Started Aug 01 05:22:44 PM PDT 24
Finished Aug 01 05:22:47 PM PDT 24
Peak memory 201216 kb
Host smart-ff43baf2-2f56-45cf-80ed-859c1aa595a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889679036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.3889679036
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1040286965
Short name T343
Test name
Test status
Simulation time 3130466351 ps
CPU time 6.17 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:36 PM PDT 24
Peak memory 201556 kb
Host smart-d4b78dff-a247-43be-a808-66535defcf56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040286965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.1040286965
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.127993890
Short name T339
Test name
Test status
Simulation time 54554811080 ps
CPU time 40.31 seconds
Started Aug 01 05:22:29 PM PDT 24
Finished Aug 01 05:23:10 PM PDT 24
Peak memory 201624 kb
Host smart-b5ce7edf-878b-46b4-9874-bb29ded37274
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127993890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_bit_bash.127993890
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.790197188
Short name T862
Test name
Test status
Simulation time 4010573967 ps
CPU time 11.25 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:35 PM PDT 24
Peak memory 201320 kb
Host smart-c29b47bd-1c42-4c86-b513-95f3ea3bc34c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790197188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.790197188
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1390272942
Short name T94
Test name
Test status
Simulation time 2087112313 ps
CPU time 6.39 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201396 kb
Host smart-feb4fa12-d389-4187-8646-f65a18276fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390272942 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1390272942
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2417882473
Short name T866
Test name
Test status
Simulation time 2080292930 ps
CPU time 2.34 seconds
Started Aug 01 05:22:19 PM PDT 24
Finished Aug 01 05:22:22 PM PDT 24
Peak memory 201416 kb
Host smart-b17d2b31-aecb-48bd-bd58-2920fb8521b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417882473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2417882473
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.805477569
Short name T852
Test name
Test status
Simulation time 2038210080 ps
CPU time 1.8 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201072 kb
Host smart-31b607d0-7198-4a36-8670-f1b336bef9a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805477569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test
.805477569
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2382189862
Short name T815
Test name
Test status
Simulation time 5296502303 ps
CPU time 4.03 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:26 PM PDT 24
Peak memory 201680 kb
Host smart-3df43b12-6bab-4c51-b7fa-c285cf40e9e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382189862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2382189862
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2226748525
Short name T842
Test name
Test status
Simulation time 2026601931 ps
CPU time 6.76 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201748 kb
Host smart-ba545f14-3a5e-4729-aa76-388e013ea5b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226748525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.2226748525
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.18225810
Short name T827
Test name
Test status
Simulation time 42579436036 ps
CPU time 72.37 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:23:35 PM PDT 24
Peak memory 201696 kb
Host smart-47a5d0dd-661e-4b5e-801e-01757a68b0a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18225810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_tl_intg_err.18225810
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3379739687
Short name T883
Test name
Test status
Simulation time 2036618108 ps
CPU time 1.92 seconds
Started Aug 01 05:22:49 PM PDT 24
Finished Aug 01 05:22:51 PM PDT 24
Peak memory 201048 kb
Host smart-37699d1b-1823-41c4-a78b-c767a89a0160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379739687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.3379739687
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.153300599
Short name T804
Test name
Test status
Simulation time 2015970771 ps
CPU time 5.8 seconds
Started Aug 01 05:22:40 PM PDT 24
Finished Aug 01 05:22:46 PM PDT 24
Peak memory 201108 kb
Host smart-125bab71-81b0-4798-9073-e41d6ae2b037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153300599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_tes
t.153300599
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.948153647
Short name T829
Test name
Test status
Simulation time 2013232278 ps
CPU time 5.88 seconds
Started Aug 01 05:22:37 PM PDT 24
Finished Aug 01 05:22:43 PM PDT 24
Peak memory 201044 kb
Host smart-96c77c31-c781-4fcc-bb20-b0ce129705fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948153647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_tes
t.948153647
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.309672506
Short name T819
Test name
Test status
Simulation time 2040695248 ps
CPU time 2.01 seconds
Started Aug 01 05:22:43 PM PDT 24
Finished Aug 01 05:22:45 PM PDT 24
Peak memory 201088 kb
Host smart-4011c02f-38f3-4c64-a10a-adf9396dbdcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309672506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.309672506
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2831198045
Short name T890
Test name
Test status
Simulation time 2019729145 ps
CPU time 3.67 seconds
Started Aug 01 05:22:42 PM PDT 24
Finished Aug 01 05:22:45 PM PDT 24
Peak memory 201244 kb
Host smart-bb0ee4c1-07b7-491d-a707-57292d9764dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831198045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2831198045
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.967294653
Short name T811
Test name
Test status
Simulation time 2019652327 ps
CPU time 3.35 seconds
Started Aug 01 05:22:39 PM PDT 24
Finished Aug 01 05:22:42 PM PDT 24
Peak memory 201180 kb
Host smart-ff769f51-861e-4a29-85ce-f942b1d48758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967294653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_tes
t.967294653
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2204719817
Short name T914
Test name
Test status
Simulation time 2046700290 ps
CPU time 1.54 seconds
Started Aug 01 05:22:38 PM PDT 24
Finished Aug 01 05:22:40 PM PDT 24
Peak memory 201228 kb
Host smart-43f25d36-335d-4ebd-84cc-9e5f2f7c4d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204719817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.2204719817
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2613684366
Short name T900
Test name
Test status
Simulation time 2020202321 ps
CPU time 3.3 seconds
Started Aug 01 05:22:36 PM PDT 24
Finished Aug 01 05:22:39 PM PDT 24
Peak memory 201128 kb
Host smart-d0755090-c9b9-4d7c-b667-afa71f13509f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613684366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.2613684366
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.33878080
Short name T878
Test name
Test status
Simulation time 2012412964 ps
CPU time 6.18 seconds
Started Aug 01 05:22:46 PM PDT 24
Finished Aug 01 05:22:52 PM PDT 24
Peak memory 201348 kb
Host smart-c5aa9a87-69b5-4b5e-82f5-1adb16ff8df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33878080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test
.33878080
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.789108215
Short name T810
Test name
Test status
Simulation time 2029363701 ps
CPU time 1.78 seconds
Started Aug 01 05:22:36 PM PDT 24
Finished Aug 01 05:22:38 PM PDT 24
Peak memory 201068 kb
Host smart-c79888ce-672a-4aa3-98b1-9bd352e833a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789108215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_tes
t.789108215
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3214839227
Short name T846
Test name
Test status
Simulation time 2082801000 ps
CPU time 2.03 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201480 kb
Host smart-d6863657-142c-42a0-84e9-7cb7bb186d29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214839227 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3214839227
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1094095655
Short name T881
Test name
Test status
Simulation time 2053432930 ps
CPU time 5.54 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:30 PM PDT 24
Peak memory 201432 kb
Host smart-45acf9cf-e442-4462-88f2-4e7776d70be1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094095655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.1094095655
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3573483287
Short name T797
Test name
Test status
Simulation time 2013037354 ps
CPU time 5.32 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201172 kb
Host smart-c1845d3f-f4eb-4cf0-ba7e-06a465753e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573483287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.3573483287
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1398953642
Short name T844
Test name
Test status
Simulation time 4996607794 ps
CPU time 3.07 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:22:24 PM PDT 24
Peak memory 201584 kb
Host smart-3ab5dec6-a375-48b7-b1cf-9ceba518090a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398953642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1398953642
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2000752096
Short name T874
Test name
Test status
Simulation time 2040781999 ps
CPU time 7.39 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201588 kb
Host smart-4a19667b-bf6a-4435-b769-e8f63c19efcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000752096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2000752096
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3399777129
Short name T903
Test name
Test status
Simulation time 42577095889 ps
CPU time 54.56 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:23:20 PM PDT 24
Peak memory 201672 kb
Host smart-088aac60-38af-4510-84ff-c816c07c9340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399777129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3399777129
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4222056662
Short name T96
Test name
Test status
Simulation time 2067898927 ps
CPU time 3.25 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 201376 kb
Host smart-e92159de-3e29-4235-bcb3-802643f5e229
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222056662 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4222056662
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3304002867
Short name T848
Test name
Test status
Simulation time 2032432144 ps
CPU time 5.55 seconds
Started Aug 01 05:22:25 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201324 kb
Host smart-b20d69bd-51cc-496d-b4f3-4cf95f326352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304002867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.3304002867
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.4216458654
Short name T800
Test name
Test status
Simulation time 2019486268 ps
CPU time 3.68 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:28 PM PDT 24
Peak memory 201012 kb
Host smart-50073051-6921-416f-b42b-f59ce67c5fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216458654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.4216458654
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3902645024
Short name T849
Test name
Test status
Simulation time 9341738791 ps
CPU time 24.57 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:48 PM PDT 24
Peak memory 201516 kb
Host smart-b7032ac7-3d4a-480d-86c3-1b604ae28322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902645024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3902645024
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.2003718188
Short name T95
Test name
Test status
Simulation time 2061588888 ps
CPU time 6.97 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201580 kb
Host smart-69ca4a83-c901-442f-84f5-e659f4712981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003718188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.2003718188
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4151227643
Short name T821
Test name
Test status
Simulation time 2104931657 ps
CPU time 3.7 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201328 kb
Host smart-23803958-336a-41bb-8168-f3c52453a9cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151227643 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4151227643
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1556694845
Short name T807
Test name
Test status
Simulation time 2077104175 ps
CPU time 3.66 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:29 PM PDT 24
Peak memory 201352 kb
Host smart-732ff144-7d9f-4927-beb8-a4f9cde21735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556694845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.1556694845
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2118302367
Short name T813
Test name
Test status
Simulation time 2080028469 ps
CPU time 1.39 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201172 kb
Host smart-dd3e9db6-5527-42c6-8fc8-1241e3374348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118302367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.2118302367
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3846577051
Short name T816
Test name
Test status
Simulation time 9661296817 ps
CPU time 17.22 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:42 PM PDT 24
Peak memory 201692 kb
Host smart-8547fbbf-6309-410e-9206-95377769f84c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846577051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3846577051
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.838355309
Short name T97
Test name
Test status
Simulation time 2278419654 ps
CPU time 5.13 seconds
Started Aug 01 05:22:26 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201648 kb
Host smart-3e448913-a24b-444f-88c2-b7d54b10acd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838355309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors
.838355309
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.935545492
Short name T869
Test name
Test status
Simulation time 42810815524 ps
CPU time 28.57 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:50 PM PDT 24
Peak memory 201580 kb
Host smart-456259ce-a3ab-471f-a891-3ae4af829581
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935545492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_tl_intg_err.935545492
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.712976541
Short name T910
Test name
Test status
Simulation time 2110382793 ps
CPU time 2.55 seconds
Started Aug 01 05:22:30 PM PDT 24
Finished Aug 01 05:22:33 PM PDT 24
Peak memory 201596 kb
Host smart-898d199a-11b5-4669-b926-4564d8cd5332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712976541 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.712976541
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1444229385
Short name T889
Test name
Test status
Simulation time 2070914707 ps
CPU time 1.38 seconds
Started Aug 01 05:22:23 PM PDT 24
Finished Aug 01 05:22:25 PM PDT 24
Peak memory 201344 kb
Host smart-88e64b6d-168d-4fc1-a074-d65fccf69a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444229385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.1444229385
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1302550635
Short name T17
Test name
Test status
Simulation time 4954962891 ps
CPU time 1.94 seconds
Started Aug 01 05:22:20 PM PDT 24
Finished Aug 01 05:22:22 PM PDT 24
Peak memory 201572 kb
Host smart-06dac258-477e-45cd-9f5e-d3f739c60763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302550635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.1302550635
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.737787812
Short name T77
Test name
Test status
Simulation time 2126944645 ps
CPU time 7.26 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:31 PM PDT 24
Peak memory 201644 kb
Host smart-1a40091b-163c-469e-89df-0fa8c9261734
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737787812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.737787812
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.269112607
Short name T327
Test name
Test status
Simulation time 2664406344 ps
CPU time 1.43 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:24 PM PDT 24
Peak memory 201708 kb
Host smart-7ee8f674-d542-4ab3-a08a-e2d5f4f26813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269112607 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.269112607
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2590111921
Short name T335
Test name
Test status
Simulation time 2115817441 ps
CPU time 2.11 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:27 PM PDT 24
Peak memory 201324 kb
Host smart-2c36c53c-3868-4943-93d2-d81b3ed1dce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590111921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.2590111921
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1890703789
Short name T795
Test name
Test status
Simulation time 2043888458 ps
CPU time 1.95 seconds
Started Aug 01 05:22:22 PM PDT 24
Finished Aug 01 05:22:24 PM PDT 24
Peak memory 201164 kb
Host smart-83b1df27-b460-4d01-acc3-d5e21092ab40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890703789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.1890703789
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.491502104
Short name T873
Test name
Test status
Simulation time 9761758031 ps
CPU time 13.38 seconds
Started Aug 01 05:22:24 PM PDT 24
Finished Aug 01 05:22:37 PM PDT 24
Peak memory 201672 kb
Host smart-ce1a1597-2c88-499f-9b62-db0450e4bcdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491502104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_same_csr_outstanding.491502104
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1980678609
Short name T880
Test name
Test status
Simulation time 2555914223 ps
CPU time 4.29 seconds
Started Aug 01 05:22:19 PM PDT 24
Finished Aug 01 05:22:24 PM PDT 24
Peak memory 201796 kb
Host smart-a5214336-bfbb-40e3-a081-7c9e8a91d267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980678609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.1980678609
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.239247171
Short name T98
Test name
Test status
Simulation time 42747489405 ps
CPU time 42.89 seconds
Started Aug 01 05:22:21 PM PDT 24
Finished Aug 01 05:23:04 PM PDT 24
Peak memory 201708 kb
Host smart-8fb3ed49-5632-4f8a-b15d-1ef02d831df2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239247171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_tl_intg_err.239247171
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3240460920
Short name T624
Test name
Test status
Simulation time 2009798753 ps
CPU time 5.22 seconds
Started Aug 01 05:23:53 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 200684 kb
Host smart-9b9aa2c7-4268-4281-ae91-db1d92bf2c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240460920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3240460920
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2659795153
Short name T582
Test name
Test status
Simulation time 3314491692 ps
CPU time 9.2 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:24:03 PM PDT 24
Peak memory 200844 kb
Host smart-8f8abb3c-172f-490c-917d-24ab37e86dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659795153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2659795153
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.1013074216
Short name T356
Test name
Test status
Simulation time 159828973267 ps
CPU time 214.29 seconds
Started Aug 01 05:23:52 PM PDT 24
Finished Aug 01 05:27:27 PM PDT 24
Peak memory 200944 kb
Host smart-5c170160-975f-46c3-81f8-fa089dfb1d2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013074216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.1013074216
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2081558559
Short name T752
Test name
Test status
Simulation time 2236580759 ps
CPU time 1.87 seconds
Started Aug 01 05:23:50 PM PDT 24
Finished Aug 01 05:23:52 PM PDT 24
Peak memory 200748 kb
Host smart-099f9190-3f4f-47d0-9e05-7e82de9d3afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081558559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2081558559
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1340960249
Short name T270
Test name
Test status
Simulation time 2540449682 ps
CPU time 1.92 seconds
Started Aug 01 05:23:43 PM PDT 24
Finished Aug 01 05:23:45 PM PDT 24
Peak memory 200840 kb
Host smart-6825582c-8d15-48cb-b9f6-e8c6adfaef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340960249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1340960249
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3697476480
Short name T108
Test name
Test status
Simulation time 27080856293 ps
CPU time 69.03 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:25:03 PM PDT 24
Peak memory 201048 kb
Host smart-f13cd6da-4b2a-4f6f-a25f-02ecb17776fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697476480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.3697476480
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.594087850
Short name T405
Test name
Test status
Simulation time 4847141786 ps
CPU time 3.32 seconds
Started Aug 01 05:23:55 PM PDT 24
Finished Aug 01 05:23:59 PM PDT 24
Peak memory 200780 kb
Host smart-2391e5d4-1516-46ca-a07e-1471a9e48d4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594087850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ec_pwr_on_rst.594087850
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2052353288
Short name T11
Test name
Test status
Simulation time 2730558652 ps
CPU time 6.76 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:24:01 PM PDT 24
Peak memory 200820 kb
Host smart-66b67862-f026-4761-8652-512ac71d7ac8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052353288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2052353288
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.141319112
Short name T632
Test name
Test status
Simulation time 2629095721 ps
CPU time 2.22 seconds
Started Aug 01 05:23:47 PM PDT 24
Finished Aug 01 05:23:50 PM PDT 24
Peak memory 200860 kb
Host smart-06002fda-7a77-4978-9c43-b22b5489899f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141319112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.141319112
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2529693059
Short name T430
Test name
Test status
Simulation time 2475219232 ps
CPU time 4.07 seconds
Started Aug 01 05:23:43 PM PDT 24
Finished Aug 01 05:23:47 PM PDT 24
Peak memory 200736 kb
Host smart-d62bd325-e6f0-4754-8db7-114de9b65ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529693059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2529693059
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1796181445
Short name T607
Test name
Test status
Simulation time 2166272645 ps
CPU time 5.79 seconds
Started Aug 01 05:23:47 PM PDT 24
Finished Aug 01 05:23:53 PM PDT 24
Peak memory 200844 kb
Host smart-4b302ea5-f3fa-4e17-9512-c779b48940a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796181445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1796181445
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1474284115
Short name T528
Test name
Test status
Simulation time 2516576571 ps
CPU time 3.92 seconds
Started Aug 01 05:23:50 PM PDT 24
Finished Aug 01 05:23:54 PM PDT 24
Peak memory 200728 kb
Host smart-b31fdefc-eb8f-4b23-aa23-8fcc7184556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474284115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1474284115
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.3563235041
Short name T236
Test name
Test status
Simulation time 2113411702 ps
CPU time 6.14 seconds
Started Aug 01 05:23:43 PM PDT 24
Finished Aug 01 05:23:49 PM PDT 24
Peak memory 200668 kb
Host smart-9e646fd8-faa2-42ed-98b5-66d519e022fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563235041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3563235041
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.1900012411
Short name T195
Test name
Test status
Simulation time 12396913458 ps
CPU time 32.11 seconds
Started Aug 01 05:23:56 PM PDT 24
Finished Aug 01 05:24:28 PM PDT 24
Peak memory 200920 kb
Host smart-c6657153-ec04-4955-afec-6cba0ddb50fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900012411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.1900012411
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.861870834
Short name T167
Test name
Test status
Simulation time 7670923011 ps
CPU time 2.47 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:23:57 PM PDT 24
Peak memory 200752 kb
Host smart-464601c2-82ee-4cc6-b711-ecee4c08f023
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861870834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ultra_low_pwr.861870834
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.4095372941
Short name T525
Test name
Test status
Simulation time 2013619037 ps
CPU time 5.81 seconds
Started Aug 01 05:23:56 PM PDT 24
Finished Aug 01 05:24:02 PM PDT 24
Peak memory 200748 kb
Host smart-047b533a-f9e0-4059-bb4f-e2ae2edd7af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095372941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.4095372941
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.4199684358
Short name T545
Test name
Test status
Simulation time 3671358200 ps
CPU time 9.81 seconds
Started Aug 01 05:23:56 PM PDT 24
Finished Aug 01 05:24:06 PM PDT 24
Peak memory 200844 kb
Host smart-b2cb9740-16d1-4778-a881-8ea1de1369e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199684358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.4199684358
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3839768367
Short name T288
Test name
Test status
Simulation time 126770335162 ps
CPU time 66.44 seconds
Started Aug 01 05:23:55 PM PDT 24
Finished Aug 01 05:25:02 PM PDT 24
Peak memory 201012 kb
Host smart-bb177506-775b-405b-874f-cfdd335dfa4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839768367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.3839768367
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2695801579
Short name T775
Test name
Test status
Simulation time 2157932591 ps
CPU time 5.87 seconds
Started Aug 01 05:23:56 PM PDT 24
Finished Aug 01 05:24:02 PM PDT 24
Peak memory 200724 kb
Host smart-dc47dcd3-c98b-4bb2-9d90-22a08fac21c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695801579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2695801579
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3289145446
Short name T792
Test name
Test status
Simulation time 2542403163 ps
CPU time 4.03 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:23:58 PM PDT 24
Peak memory 200796 kb
Host smart-dbf37dcc-4ce0-442e-b328-bf28eba417db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289145446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3289145446
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1624477319
Short name T250
Test name
Test status
Simulation time 3250243906 ps
CPU time 6.01 seconds
Started Aug 01 05:23:57 PM PDT 24
Finished Aug 01 05:24:03 PM PDT 24
Peak memory 200720 kb
Host smart-c91f64ae-c02e-47a5-abf1-16eaf14bcd01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624477319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.1624477319
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3353891919
Short name T492
Test name
Test status
Simulation time 3187400642 ps
CPU time 4.96 seconds
Started Aug 01 05:23:55 PM PDT 24
Finished Aug 01 05:24:00 PM PDT 24
Peak memory 200744 kb
Host smart-d4fee5db-e0f1-4eeb-92c8-25db5c4e2134
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353891919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.3353891919
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1779694498
Short name T235
Test name
Test status
Simulation time 2617048742 ps
CPU time 3.77 seconds
Started Aug 01 05:23:53 PM PDT 24
Finished Aug 01 05:23:57 PM PDT 24
Peak memory 200724 kb
Host smart-d8f685c0-93fc-45dc-8ada-c2c24437da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779694498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1779694498
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2956906922
Short name T577
Test name
Test status
Simulation time 2467391838 ps
CPU time 3.91 seconds
Started Aug 01 05:23:53 PM PDT 24
Finished Aug 01 05:23:57 PM PDT 24
Peak memory 200728 kb
Host smart-92ccb6f6-8d1d-44f8-be82-ef5393365ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956906922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2956906922
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.37700285
Short name T414
Test name
Test status
Simulation time 2031630081 ps
CPU time 5.75 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:23:59 PM PDT 24
Peak memory 200772 kb
Host smart-6f4035bc-9e06-498e-91d0-0d30320f3d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37700285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.37700285
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.154749402
Short name T786
Test name
Test status
Simulation time 2508619777 ps
CPU time 7.36 seconds
Started Aug 01 05:23:55 PM PDT 24
Finished Aug 01 05:24:03 PM PDT 24
Peak memory 200736 kb
Host smart-b625e650-aea3-49fa-b622-6cd68eafcace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154749402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.154749402
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3261053040
Short name T306
Test name
Test status
Simulation time 42011887797 ps
CPU time 110.53 seconds
Started Aug 01 05:23:56 PM PDT 24
Finished Aug 01 05:25:47 PM PDT 24
Peak memory 220548 kb
Host smart-6924ba50-3879-41f4-9945-b7903ea79ad1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261053040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3261053040
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2223241600
Short name T572
Test name
Test status
Simulation time 2110538494 ps
CPU time 5.97 seconds
Started Aug 01 05:23:55 PM PDT 24
Finished Aug 01 05:24:01 PM PDT 24
Peak memory 200628 kb
Host smart-b85c3966-8f36-4146-87fb-48a9a89486ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223241600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2223241600
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3856437616
Short name T243
Test name
Test status
Simulation time 104306264908 ps
CPU time 57.39 seconds
Started Aug 01 05:23:54 PM PDT 24
Finished Aug 01 05:24:52 PM PDT 24
Peak memory 209424 kb
Host smart-60727f9c-9e81-4853-9cd0-0862a9ddda07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856437616 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3856437616
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1619417248
Short name T147
Test name
Test status
Simulation time 4524803132 ps
CPU time 6.59 seconds
Started Aug 01 05:23:52 PM PDT 24
Finished Aug 01 05:23:59 PM PDT 24
Peak memory 200888 kb
Host smart-0e43d218-41ae-427b-8b82-2119d9cdb4c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619417248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1619417248
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.301461283
Short name T351
Test name
Test status
Simulation time 52660805577 ps
CPU time 72.01 seconds
Started Aug 01 05:24:37 PM PDT 24
Finished Aug 01 05:25:49 PM PDT 24
Peak memory 201020 kb
Host smart-aedd4b31-e0bb-45bf-b6a0-0638e651dae6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301461283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.301461283
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3168258713
Short name T374
Test name
Test status
Simulation time 122700449426 ps
CPU time 78.97 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:25:55 PM PDT 24
Peak memory 201160 kb
Host smart-ab6a939d-3cff-4f4e-84bb-b3b3a698c88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168258713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.3168258713
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3187546222
Short name T529
Test name
Test status
Simulation time 2967524260 ps
CPU time 2.55 seconds
Started Aug 01 05:24:37 PM PDT 24
Finished Aug 01 05:24:40 PM PDT 24
Peak memory 200744 kb
Host smart-ba13fdcb-269d-4cbc-a365-b3a6afc33765
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187546222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.3187546222
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.2664995599
Short name T212
Test name
Test status
Simulation time 3839222118 ps
CPU time 8.44 seconds
Started Aug 01 05:24:37 PM PDT 24
Finished Aug 01 05:24:46 PM PDT 24
Peak memory 200812 kb
Host smart-6d2311e5-2374-4a3f-a8a2-b0108277d332
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664995599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.2664995599
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1274076711
Short name T512
Test name
Test status
Simulation time 2612353691 ps
CPU time 6.75 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200780 kb
Host smart-df8f7836-f732-4408-bd70-0e7c670ed36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274076711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1274076711
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1097542927
Short name T659
Test name
Test status
Simulation time 2510443930 ps
CPU time 2.3 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:37 PM PDT 24
Peak memory 200732 kb
Host smart-057b5c00-29f1-40d1-a6a2-faaec4ef5c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097542927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1097542927
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2581460603
Short name T779
Test name
Test status
Simulation time 2156847480 ps
CPU time 5.92 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:24:46 PM PDT 24
Peak memory 200732 kb
Host smart-6990e295-8244-46ea-a9eb-e1e3dc31e1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581460603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2581460603
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1325823702
Short name T127
Test name
Test status
Simulation time 2513534200 ps
CPU time 7.23 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:43 PM PDT 24
Peak memory 200788 kb
Host smart-abeac00c-c589-45ec-b1ab-3a0d4d1a1901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325823702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1325823702
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.3281109643
Short name T522
Test name
Test status
Simulation time 2115150710 ps
CPU time 3.36 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:24:39 PM PDT 24
Peak memory 200700 kb
Host smart-c4016329-299e-4b19-a5b0-a39f688f144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281109643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3281109643
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.2516884088
Short name T266
Test name
Test status
Simulation time 12288152217 ps
CPU time 17.7 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:24:54 PM PDT 24
Peak memory 200708 kb
Host smart-24e6a086-10ea-4f2e-a1c9-40371b729d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516884088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.2516884088
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.608357541
Short name T131
Test name
Test status
Simulation time 7515326172 ps
CPU time 7.47 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:43 PM PDT 24
Peak memory 200780 kb
Host smart-6db9c812-243f-4791-892e-f3d9dc625f07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608357541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ultra_low_pwr.608357541
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.41470178
Short name T394
Test name
Test status
Simulation time 2012847549 ps
CPU time 5.77 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:45 PM PDT 24
Peak memory 200808 kb
Host smart-a429fb6e-b125-43c4-846b-d73c23528c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test
.41470178
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.612362502
Short name T46
Test name
Test status
Simulation time 3284142403 ps
CPU time 8.71 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:24:45 PM PDT 24
Peak memory 200872 kb
Host smart-bbd9b27f-4b9d-423c-b56d-2439809ca2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612362502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.612362502
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.231089112
Short name T264
Test name
Test status
Simulation time 40239821590 ps
CPU time 104.68 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:26:24 PM PDT 24
Peak memory 201056 kb
Host smart-5a15afe8-c3cc-4ddc-84ad-389a84098712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231089112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.231089112
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.4125994541
Short name T766
Test name
Test status
Simulation time 3145554073 ps
CPU time 1.88 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200720 kb
Host smart-593b10f6-0765-46c4-bf6a-05e856866a13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125994541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.4125994541
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.3268103846
Short name T13
Test name
Test status
Simulation time 3965422575 ps
CPU time 9.16 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:24:46 PM PDT 24
Peak memory 200792 kb
Host smart-dbe818a3-b41c-4a78-b3b2-1d5b9d3fe04c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268103846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.3268103846
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1593486305
Short name T260
Test name
Test status
Simulation time 2629504119 ps
CPU time 2.24 seconds
Started Aug 01 05:24:37 PM PDT 24
Finished Aug 01 05:24:40 PM PDT 24
Peak memory 200780 kb
Host smart-cf7c515a-b66f-45f4-a59b-0c2e73079c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593486305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1593486305
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3647653867
Short name T446
Test name
Test status
Simulation time 2490424674 ps
CPU time 2.04 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:41 PM PDT 24
Peak memory 200804 kb
Host smart-8cd652c1-e1f5-4f94-a3d2-e337332009bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647653867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3647653867
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2786023902
Short name T192
Test name
Test status
Simulation time 2061497613 ps
CPU time 6.05 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200748 kb
Host smart-6e6e1b50-63c9-4540-8731-228fc68d9dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786023902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.2786023902
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3383717927
Short name T734
Test name
Test status
Simulation time 2529194488 ps
CPU time 2.23 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200804 kb
Host smart-9b4a96c2-9f9a-49c6-acf6-b6c6ad7867c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383717927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3383717927
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.112118653
Short name T451
Test name
Test status
Simulation time 2111238656 ps
CPU time 6.07 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:44 PM PDT 24
Peak memory 200672 kb
Host smart-d8dab136-492f-462f-a91d-e31082a7ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112118653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.112118653
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.1362413012
Short name T516
Test name
Test status
Simulation time 6890122921 ps
CPU time 5.34 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:44 PM PDT 24
Peak memory 200800 kb
Host smart-09a5ecd0-0a19-4b11-bb00-7348a03c28dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362413012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.1362413012
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2380082320
Short name T567
Test name
Test status
Simulation time 27415509000 ps
CPU time 47.85 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:25:25 PM PDT 24
Peak memory 217168 kb
Host smart-35d8a134-0672-4370-b44c-743384d7d1bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380082320 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2380082320
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1816727073
Short name T162
Test name
Test status
Simulation time 9243146000 ps
CPU time 8.93 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:47 PM PDT 24
Peak memory 200892 kb
Host smart-32ac63cc-8233-44fe-b8e1-0343f2d20b59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816727073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1816727073
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.3262138662
Short name T557
Test name
Test status
Simulation time 2032465104 ps
CPU time 1.87 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:41 PM PDT 24
Peak memory 200732 kb
Host smart-20c41999-b557-4181-a412-f5307130f367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262138662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.3262138662
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.299822236
Short name T703
Test name
Test status
Simulation time 3463089322 ps
CPU time 9.47 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:24:50 PM PDT 24
Peak memory 200808 kb
Host smart-cc59713c-949c-47ed-936d-37f074eff856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299822236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.299822236
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3103490719
Short name T301
Test name
Test status
Simulation time 139465027214 ps
CPU time 88.91 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:26:09 PM PDT 24
Peak memory 201012 kb
Host smart-c60f8028-7dbe-492a-b376-2e1faa1f4dbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103490719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3103490719
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4210818425
Short name T357
Test name
Test status
Simulation time 33710302474 ps
CPU time 22.82 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:25:02 PM PDT 24
Peak memory 201104 kb
Host smart-2b65d55b-f9d4-48a1-bf1a-3627bfeca735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210818425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.4210818425
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.944585415
Short name T670
Test name
Test status
Simulation time 2656671970 ps
CPU time 1.41 seconds
Started Aug 01 05:24:41 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200832 kb
Host smart-78542a8e-d7d6-4c52-abf2-aa6f62223598
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944585415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ec_pwr_on_rst.944585415
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.3568803923
Short name T211
Test name
Test status
Simulation time 3264223145 ps
CPU time 6.89 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:24:47 PM PDT 24
Peak memory 200856 kb
Host smart-16a5fb19-fb2c-4d77-8461-ebe6cc6dd83d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568803923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.3568803923
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2322302321
Short name T170
Test name
Test status
Simulation time 2614982660 ps
CPU time 3.95 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:24:40 PM PDT 24
Peak memory 200764 kb
Host smart-e8d3bb56-9190-4845-9f48-e985ebb1edaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322302321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2322302321
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2219748217
Short name T318
Test name
Test status
Simulation time 2460661277 ps
CPU time 6.71 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:46 PM PDT 24
Peak memory 200796 kb
Host smart-f093e84f-ac86-4cad-a428-a6429954ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219748217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2219748217
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3589544376
Short name T468
Test name
Test status
Simulation time 2175526403 ps
CPU time 2.03 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200740 kb
Host smart-a99191f1-a7ad-4745-888e-45c217a733fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589544376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3589544376
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1612776735
Short name T393
Test name
Test status
Simulation time 2509343358 ps
CPU time 6.83 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:45 PM PDT 24
Peak memory 200800 kb
Host smart-2b91b7e5-0711-428b-951e-9999fbc18a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612776735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1612776735
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.2640343739
Short name T546
Test name
Test status
Simulation time 2118863452 ps
CPU time 3.71 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:43 PM PDT 24
Peak memory 200660 kb
Host smart-1ec2627b-41e0-4a96-8665-f31f75748d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640343739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2640343739
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.339880461
Short name T711
Test name
Test status
Simulation time 9069245183 ps
CPU time 26.07 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:25:06 PM PDT 24
Peak memory 200792 kb
Host smart-04eb01e7-0a93-43d1-9603-e61cd43361ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339880461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.339880461
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1541324230
Short name T311
Test name
Test status
Simulation time 54129629090 ps
CPU time 143.13 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:27:03 PM PDT 24
Peak memory 201228 kb
Host smart-ff45034e-cfdf-4c17-962c-8e60b4abf049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541324230 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.1541324230
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2402691635
Short name T166
Test name
Test status
Simulation time 7291096836 ps
CPU time 8.49 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:48 PM PDT 24
Peak memory 200860 kb
Host smart-002d477a-91d6-490f-a083-0f1b5fb08236
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402691635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2402691635
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1308858408
Short name T578
Test name
Test status
Simulation time 2042175165 ps
CPU time 1.66 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:49 PM PDT 24
Peak memory 200808 kb
Host smart-37d22bc3-2071-4a3c-b33c-6154f2311b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308858408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1308858408
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3241438256
Short name T267
Test name
Test status
Simulation time 3588842879 ps
CPU time 2.79 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200852 kb
Host smart-2520f2f3-1ccd-4054-a057-3d582cfd2b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241438256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3
241438256
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.142823457
Short name T593
Test name
Test status
Simulation time 32588242416 ps
CPU time 80.83 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:25:59 PM PDT 24
Peak memory 201056 kb
Host smart-d511e07c-c4d9-40cc-81f4-0faaf5b0c782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142823457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.142823457
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2777778164
Short name T457
Test name
Test status
Simulation time 4928777390 ps
CPU time 3.64 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:42 PM PDT 24
Peak memory 200772 kb
Host smart-a3eeee4e-aa34-4b20-8255-a56f7270c852
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777778164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.2777778164
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.383542644
Short name T230
Test name
Test status
Simulation time 2866071774 ps
CPU time 1.07 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:39 PM PDT 24
Peak memory 200836 kb
Host smart-bbfdd414-5444-435a-bd40-a9928bfc5b2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383542644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctr
l_edge_detect.383542644
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.654658234
Short name T452
Test name
Test status
Simulation time 2669955257 ps
CPU time 1.27 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:40 PM PDT 24
Peak memory 200764 kb
Host smart-257b3064-6033-4038-94b2-4bbd630cbb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654658234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.654658234
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.984292861
Short name T681
Test name
Test status
Simulation time 2529827800 ps
CPU time 1.11 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:24:41 PM PDT 24
Peak memory 200572 kb
Host smart-54a6f0d6-b970-4e13-8e9a-00a218cb25fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984292861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.984292861
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1735410519
Short name T129
Test name
Test status
Simulation time 2122208656 ps
CPU time 6.1 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:41 PM PDT 24
Peak memory 200640 kb
Host smart-7c7a0e33-f390-4e1b-8d11-46efa6a855c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735410519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1735410519
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1899335896
Short name T197
Test name
Test status
Simulation time 2527141668 ps
CPU time 2.17 seconds
Started Aug 01 05:24:42 PM PDT 24
Finished Aug 01 05:24:44 PM PDT 24
Peak memory 200776 kb
Host smart-be52dfa1-4c66-4c12-abed-7242b7633840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899335896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1899335896
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2620836407
Short name T179
Test name
Test status
Simulation time 2109183123 ps
CPU time 5.99 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:24:46 PM PDT 24
Peak memory 200660 kb
Host smart-243f3a03-1a70-4eb2-b8c8-83e5ac069589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620836407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2620836407
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.53478821
Short name T552
Test name
Test status
Simulation time 11192491361 ps
CPU time 20.85 seconds
Started Aug 01 05:24:46 PM PDT 24
Finished Aug 01 05:25:07 PM PDT 24
Peak memory 200692 kb
Host smart-24b91c6e-4b48-4c52-a838-a09562c97ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53478821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_str
ess_all.53478821
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2425029843
Short name T227
Test name
Test status
Simulation time 45812458764 ps
CPU time 116.56 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:26:36 PM PDT 24
Peak memory 209396 kb
Host smart-fd565fdb-e6cc-4ba2-b97c-a1defc2a5146
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425029843 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.2425029843
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3033566614
Short name T605
Test name
Test status
Simulation time 4178405797 ps
CPU time 5.39 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:43 PM PDT 24
Peak memory 200832 kb
Host smart-935963c7-40e0-45a0-b859-af49cc1fad12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033566614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.3033566614
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.1691786793
Short name T526
Test name
Test status
Simulation time 2041778647 ps
CPU time 1.48 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:50 PM PDT 24
Peak memory 200820 kb
Host smart-740dbff3-f59c-4edc-b5ed-5aebaf3ce4fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691786793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.1691786793
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1579776291
Short name T602
Test name
Test status
Simulation time 3625497826 ps
CPU time 9.99 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:57 PM PDT 24
Peak memory 200792 kb
Host smart-6eee6794-d056-4909-a67f-4ccb9d9e21ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579776291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
579776291
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.73434273
Short name T66
Test name
Test status
Simulation time 124414832825 ps
CPU time 67.52 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:25:55 PM PDT 24
Peak memory 200992 kb
Host smart-ad654f2c-875a-4594-9be8-a9e73f4a9020
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73434273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_combo_detect.73434273
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3686586508
Short name T428
Test name
Test status
Simulation time 3118991662 ps
CPU time 7.8 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:56 PM PDT 24
Peak memory 200836 kb
Host smart-202768ed-c5b3-44ae-89e1-1c3d3c907fdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686586508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.3686586508
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.83003458
Short name T200
Test name
Test status
Simulation time 3464784280 ps
CPU time 2.2 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:49 PM PDT 24
Peak memory 200880 kb
Host smart-341d6d7a-39f1-491a-a55f-f0a423a19e7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83003458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl
_edge_detect.83003458
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3199165082
Short name T556
Test name
Test status
Simulation time 2609133872 ps
CPU time 7.14 seconds
Started Aug 01 05:24:46 PM PDT 24
Finished Aug 01 05:24:54 PM PDT 24
Peak memory 200792 kb
Host smart-d87968e0-ba0d-4f64-83f7-69684ca0bed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199165082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3199165082
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1513982658
Short name T716
Test name
Test status
Simulation time 2463676638 ps
CPU time 3.72 seconds
Started Aug 01 05:24:46 PM PDT 24
Finished Aug 01 05:24:50 PM PDT 24
Peak memory 200780 kb
Host smart-93c84e35-9a02-48e7-adeb-81e5cba450cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513982658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1513982658
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2260856161
Short name T509
Test name
Test status
Simulation time 2085564785 ps
CPU time 3.35 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:51 PM PDT 24
Peak memory 200708 kb
Host smart-39d9a7fa-13cc-4e78-a823-9ea39d0da770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260856161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2260856161
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3520942548
Short name T190
Test name
Test status
Simulation time 2525446464 ps
CPU time 2.41 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:51 PM PDT 24
Peak memory 200788 kb
Host smart-42c6baf5-862e-4b5f-90f0-fb7c6d77d97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520942548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.3520942548
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.2396065036
Short name T504
Test name
Test status
Simulation time 2112100568 ps
CPU time 5.6 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:53 PM PDT 24
Peak memory 200600 kb
Host smart-9efb655a-d781-42f8-86fc-e07a8f198f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396065036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.2396065036
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.1290721952
Short name T497
Test name
Test status
Simulation time 461646056625 ps
CPU time 1132.24 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:43:40 PM PDT 24
Peak memory 200840 kb
Host smart-7e02bc8d-e755-400f-9804-e0184c60168e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290721952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.1290721952
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1401031125
Short name T599
Test name
Test status
Simulation time 11799771500 ps
CPU time 30.18 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:25:17 PM PDT 24
Peak memory 217404 kb
Host smart-3a0363f2-d91c-4cfa-83ee-2f680bf0726e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401031125 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1401031125
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2028546718
Short name T323
Test name
Test status
Simulation time 3850278283 ps
CPU time 5.53 seconds
Started Aug 01 05:24:46 PM PDT 24
Finished Aug 01 05:24:52 PM PDT 24
Peak memory 200880 kb
Host smart-1ffca963-3e0b-4baa-aa8a-a6bf9b25f923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028546718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.2028546718
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.152542052
Short name T392
Test name
Test status
Simulation time 2040416034 ps
CPU time 1.87 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:50 PM PDT 24
Peak memory 200792 kb
Host smart-8e101aff-bb88-49b0-8e25-0dfa063c3ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152542052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.152542052
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2229496364
Short name T554
Test name
Test status
Simulation time 3511115168 ps
CPU time 9.16 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:57 PM PDT 24
Peak memory 200772 kb
Host smart-013b278d-21e7-4f2b-9a2e-60d4f5019879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229496364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
229496364
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2418489488
Short name T370
Test name
Test status
Simulation time 92322580744 ps
CPU time 43.62 seconds
Started Aug 01 05:24:50 PM PDT 24
Finished Aug 01 05:25:34 PM PDT 24
Peak memory 201036 kb
Host smart-38219c26-3d72-48f0-8d7a-62cfd683ba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418489488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.2418489488
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.932850857
Short name T596
Test name
Test status
Simulation time 3941228447 ps
CPU time 5.17 seconds
Started Aug 01 05:24:52 PM PDT 24
Finished Aug 01 05:24:57 PM PDT 24
Peak memory 200720 kb
Host smart-7558cfa6-d008-40d4-b506-bc169d65ad98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932850857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ec_pwr_on_rst.932850857
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3287758278
Short name T231
Test name
Test status
Simulation time 4495399215 ps
CPU time 2.81 seconds
Started Aug 01 05:24:52 PM PDT 24
Finished Aug 01 05:24:55 PM PDT 24
Peak memory 200812 kb
Host smart-1177ddb7-cea3-4cde-b4ce-57a01aba28a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287758278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3287758278
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3273290498
Short name T560
Test name
Test status
Simulation time 2629021092 ps
CPU time 1.97 seconds
Started Aug 01 05:24:50 PM PDT 24
Finished Aug 01 05:24:53 PM PDT 24
Peak memory 200744 kb
Host smart-5eeea5e8-0d99-4127-9d20-8bbc5ffffdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273290498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.3273290498
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2089362288
Short name T603
Test name
Test status
Simulation time 2498321727 ps
CPU time 1.19 seconds
Started Aug 01 05:24:49 PM PDT 24
Finished Aug 01 05:24:51 PM PDT 24
Peak memory 200720 kb
Host smart-82a5269b-763b-4700-b211-5851260d0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089362288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2089362288
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1542267779
Short name T594
Test name
Test status
Simulation time 2245725398 ps
CPU time 2.05 seconds
Started Aug 01 05:24:49 PM PDT 24
Finished Aug 01 05:24:52 PM PDT 24
Peak memory 200736 kb
Host smart-dbcbba5f-899a-4624-9260-0f11e0274092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542267779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1542267779
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.848709742
Short name T322
Test name
Test status
Simulation time 2522085466 ps
CPU time 2.37 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:50 PM PDT 24
Peak memory 200724 kb
Host smart-cc9e3755-ee42-4ea4-97e0-c69a0af13d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848709742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.848709742
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.2587295220
Short name T419
Test name
Test status
Simulation time 2113746346 ps
CPU time 5.5 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:53 PM PDT 24
Peak memory 200628 kb
Host smart-ef4b464e-0ffd-4a56-9719-4a2db3791724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587295220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.2587295220
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1701199952
Short name T732
Test name
Test status
Simulation time 16881105749 ps
CPU time 17.76 seconds
Started Aug 01 05:24:49 PM PDT 24
Finished Aug 01 05:25:08 PM PDT 24
Peak memory 200824 kb
Host smart-7e9ffa03-7e18-444d-a73d-80140702061a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701199952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1701199952
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2343691670
Short name T244
Test name
Test status
Simulation time 47514939991 ps
CPU time 48.6 seconds
Started Aug 01 05:24:53 PM PDT 24
Finished Aug 01 05:25:42 PM PDT 24
Peak memory 209436 kb
Host smart-327a29ec-ddc9-4bec-8636-fed32cebb10e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343691670 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2343691670
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3723375682
Short name T549
Test name
Test status
Simulation time 3983756633 ps
CPU time 7.32 seconds
Started Aug 01 05:24:50 PM PDT 24
Finished Aug 01 05:24:57 PM PDT 24
Peak memory 200948 kb
Host smart-ae790ab9-7e32-45e9-ad18-a07361016802
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723375682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.3723375682
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.1194124212
Short name T524
Test name
Test status
Simulation time 2040957721 ps
CPU time 1.78 seconds
Started Aug 01 05:24:52 PM PDT 24
Finished Aug 01 05:24:54 PM PDT 24
Peak memory 200752 kb
Host smart-4e80b84d-0179-4d1b-a1d5-3efd1cd65049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194124212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.1194124212
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3406333622
Short name T139
Test name
Test status
Simulation time 3682799726 ps
CPU time 4.45 seconds
Started Aug 01 05:24:50 PM PDT 24
Finished Aug 01 05:24:55 PM PDT 24
Peak memory 200872 kb
Host smart-71cd4f95-7018-4210-8598-c246a88468b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406333622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3
406333622
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1855670666
Short name T285
Test name
Test status
Simulation time 142523514735 ps
CPU time 90.09 seconds
Started Aug 01 05:24:49 PM PDT 24
Finished Aug 01 05:26:20 PM PDT 24
Peak memory 201064 kb
Host smart-f3ec19e1-4b90-4840-ad05-92678d6dd694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855670666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1855670666
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2868118570
Short name T298
Test name
Test status
Simulation time 116807044032 ps
CPU time 144.34 seconds
Started Aug 01 05:24:52 PM PDT 24
Finished Aug 01 05:27:16 PM PDT 24
Peak memory 201084 kb
Host smart-9cdf2913-ddcd-4813-84f2-b74007d4c568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868118570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2868118570
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3853628630
Short name T458
Test name
Test status
Simulation time 2688863885 ps
CPU time 1.41 seconds
Started Aug 01 05:24:52 PM PDT 24
Finished Aug 01 05:24:54 PM PDT 24
Peak memory 200792 kb
Host smart-4c481e48-079e-44bb-8a24-6a13974be27f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853628630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.3853628630
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2484232545
Short name T543
Test name
Test status
Simulation time 3135457205 ps
CPU time 1.73 seconds
Started Aug 01 05:24:50 PM PDT 24
Finished Aug 01 05:24:52 PM PDT 24
Peak memory 200784 kb
Host smart-ff0eeb12-8ee0-41ff-a2d7-a164ed4fd2f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484232545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.2484232545
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2578101223
Short name T741
Test name
Test status
Simulation time 2632371447 ps
CPU time 2 seconds
Started Aug 01 05:24:53 PM PDT 24
Finished Aug 01 05:24:55 PM PDT 24
Peak memory 200780 kb
Host smart-b05db8b9-e22d-4920-b934-12a981bfa8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578101223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.2578101223
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.56751446
Short name T595
Test name
Test status
Simulation time 2482144881 ps
CPU time 3.64 seconds
Started Aug 01 05:24:53 PM PDT 24
Finished Aug 01 05:24:57 PM PDT 24
Peak memory 200796 kb
Host smart-4a6d7523-9300-4673-8644-0db1c41f091a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56751446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.56751446
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3877964947
Short name T439
Test name
Test status
Simulation time 2144665013 ps
CPU time 3.31 seconds
Started Aug 01 05:24:52 PM PDT 24
Finished Aug 01 05:24:56 PM PDT 24
Peak memory 200684 kb
Host smart-5edc3770-b8b2-44bf-8a3b-8086281858e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877964947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3877964947
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1008917876
Short name T517
Test name
Test status
Simulation time 2512681029 ps
CPU time 6.94 seconds
Started Aug 01 05:24:53 PM PDT 24
Finished Aug 01 05:25:00 PM PDT 24
Peak memory 200748 kb
Host smart-486d7850-7d09-439b-974c-9ffbd451e647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008917876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.1008917876
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.1163898338
Short name T417
Test name
Test status
Simulation time 2130644746 ps
CPU time 1.88 seconds
Started Aug 01 05:24:53 PM PDT 24
Finished Aug 01 05:24:55 PM PDT 24
Peak memory 200716 kb
Host smart-3fc34295-2d8f-4e00-b927-3efa7a28d93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163898338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1163898338
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2032778428
Short name T538
Test name
Test status
Simulation time 11350182339 ps
CPU time 7.63 seconds
Started Aug 01 05:24:54 PM PDT 24
Finished Aug 01 05:25:02 PM PDT 24
Peak memory 200860 kb
Host smart-8e6a4fd6-080a-4aad-ba85-7044a74073ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032778428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2032778428
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2297021569
Short name T106
Test name
Test status
Simulation time 891832286383 ps
CPU time 164.06 seconds
Started Aug 01 05:24:50 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 209408 kb
Host smart-fb074c9f-af65-4bae-9787-97f95a1e1941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297021569 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.2297021569
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.290533854
Short name T56
Test name
Test status
Simulation time 3890467098 ps
CPU time 3.19 seconds
Started Aug 01 05:24:49 PM PDT 24
Finished Aug 01 05:24:52 PM PDT 24
Peak memory 200852 kb
Host smart-c3fb83b5-b24e-43df-850f-59e996ad704e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290533854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ultra_low_pwr.290533854
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1502614960
Short name T735
Test name
Test status
Simulation time 2013171829 ps
CPU time 5.38 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:53 PM PDT 24
Peak memory 200680 kb
Host smart-efee5583-8400-426f-8d90-3d9019e14734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502614960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1502614960
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1279752171
Short name T657
Test name
Test status
Simulation time 3686949890 ps
CPU time 5.05 seconds
Started Aug 01 05:24:46 PM PDT 24
Finished Aug 01 05:24:51 PM PDT 24
Peak memory 200820 kb
Host smart-a6b3adfd-e667-426a-8d4a-af9cfbbf4d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279752171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
279752171
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.199535419
Short name T297
Test name
Test status
Simulation time 138941403716 ps
CPU time 88.44 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:26:16 PM PDT 24
Peak memory 201076 kb
Host smart-ff2829d3-9781-4f82-b10e-83e430812e55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199535419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.199535419
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.916261733
Short name T281
Test name
Test status
Simulation time 73055997880 ps
CPU time 46.87 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:25:34 PM PDT 24
Peak memory 201036 kb
Host smart-c62760c3-1fc4-4a1b-8092-6060fc7fac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916261733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_wi
th_pre_cond.916261733
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2287554849
Short name T544
Test name
Test status
Simulation time 4459411458 ps
CPU time 4.47 seconds
Started Aug 01 05:24:51 PM PDT 24
Finished Aug 01 05:24:55 PM PDT 24
Peak memory 200720 kb
Host smart-f96ba85d-e831-41ea-94cf-e2413ce8dd26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287554849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.2287554849
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.6554857
Short name T103
Test name
Test status
Simulation time 3045949306 ps
CPU time 2.32 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:51 PM PDT 24
Peak memory 200864 kb
Host smart-736db679-1772-4ed9-aac6-a9d27863d391
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6554857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_
edge_detect.6554857
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2887135651
Short name T69
Test name
Test status
Simulation time 2629885355 ps
CPU time 1.93 seconds
Started Aug 01 05:24:54 PM PDT 24
Finished Aug 01 05:24:57 PM PDT 24
Peak memory 200780 kb
Host smart-a594d345-ec60-4cf4-8edc-bf2569cfd203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887135651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2887135651
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.154241485
Short name T64
Test name
Test status
Simulation time 2458400247 ps
CPU time 7.27 seconds
Started Aug 01 05:24:50 PM PDT 24
Finished Aug 01 05:24:58 PM PDT 24
Peak memory 200724 kb
Host smart-3c16c4e5-efc1-4619-a957-e3c5b702ff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154241485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.154241485
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.4036492406
Short name T305
Test name
Test status
Simulation time 2071562236 ps
CPU time 1.99 seconds
Started Aug 01 05:24:54 PM PDT 24
Finished Aug 01 05:24:56 PM PDT 24
Peak memory 200728 kb
Host smart-d6bf985e-6a0f-483c-a9c0-87a7b0e463dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036492406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.4036492406
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1607931112
Short name T432
Test name
Test status
Simulation time 2512242057 ps
CPU time 6.94 seconds
Started Aug 01 05:24:53 PM PDT 24
Finished Aug 01 05:25:01 PM PDT 24
Peak memory 200784 kb
Host smart-3d432ae3-809e-4ffa-98da-18f6db126848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607931112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1607931112
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.568169058
Short name T462
Test name
Test status
Simulation time 2122844642 ps
CPU time 2.01 seconds
Started Aug 01 05:24:54 PM PDT 24
Finished Aug 01 05:24:56 PM PDT 24
Peak memory 200716 kb
Host smart-75201470-f1d1-4d6c-a9ac-9c527e8ba8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568169058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.568169058
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.570839646
Short name T387
Test name
Test status
Simulation time 17123807287 ps
CPU time 23.21 seconds
Started Aug 01 05:24:46 PM PDT 24
Finished Aug 01 05:25:09 PM PDT 24
Peak memory 200856 kb
Host smart-6368f724-05bc-457e-863b-f3f43b704b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570839646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_st
ress_all.570839646
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3504748845
Short name T58
Test name
Test status
Simulation time 2627435057 ps
CPU time 6.21 seconds
Started Aug 01 05:24:47 PM PDT 24
Finished Aug 01 05:24:54 PM PDT 24
Peak memory 200740 kb
Host smart-4c36fc73-7f49-46f2-8a79-321220f8f27c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504748845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.3504748845
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3883126729
Short name T725
Test name
Test status
Simulation time 2054077711 ps
CPU time 1.72 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:11 PM PDT 24
Peak memory 200708 kb
Host smart-f077aae5-83d5-4cda-ba99-eda6266cd240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883126729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3883126729
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2693608651
Short name T561
Test name
Test status
Simulation time 3053550310 ps
CPU time 2.72 seconds
Started Aug 01 05:24:57 PM PDT 24
Finished Aug 01 05:25:00 PM PDT 24
Peak memory 200852 kb
Host smart-5299740c-87ee-4f97-8182-5c2aad56b7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693608651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.2
693608651
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1634513647
Short name T122
Test name
Test status
Simulation time 83439483022 ps
CPU time 212.71 seconds
Started Aug 01 05:24:57 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 201068 kb
Host smart-40deab6a-55dc-4d3a-98b9-10f7f7d442d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634513647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.1634513647
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1321319542
Short name T425
Test name
Test status
Simulation time 32685156046 ps
CPU time 22.39 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:33 PM PDT 24
Peak memory 201060 kb
Host smart-fc1eaba2-ccfd-4bd7-87a9-5218fb5397c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321319542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.1321319542
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3256184743
Short name T416
Test name
Test status
Simulation time 2756063931 ps
CPU time 7.4 seconds
Started Aug 01 05:24:59 PM PDT 24
Finished Aug 01 05:25:06 PM PDT 24
Peak memory 200720 kb
Host smart-eafda8e4-dee4-4338-a317-7eb16d70c287
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256184743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.3256184743
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.3189467295
Short name T210
Test name
Test status
Simulation time 4144096705 ps
CPU time 10.79 seconds
Started Aug 01 05:24:57 PM PDT 24
Finished Aug 01 05:25:08 PM PDT 24
Peak memory 200844 kb
Host smart-56cd2878-89bf-49a6-bc07-7267c8b92620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189467295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.3189467295
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3982222994
Short name T494
Test name
Test status
Simulation time 2615096992 ps
CPU time 4.05 seconds
Started Aug 01 05:25:02 PM PDT 24
Finished Aug 01 05:25:06 PM PDT 24
Peak memory 200816 kb
Host smart-25f461df-49f4-4706-87c8-8192dd3448e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982222994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.3982222994
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2748014517
Short name T216
Test name
Test status
Simulation time 2477582992 ps
CPU time 2.45 seconds
Started Aug 01 05:24:49 PM PDT 24
Finished Aug 01 05:24:51 PM PDT 24
Peak memory 200724 kb
Host smart-acc82435-7cd5-42bc-b23a-be229090118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748014517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2748014517
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1918869737
Short name T680
Test name
Test status
Simulation time 2258647894 ps
CPU time 1.33 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:50 PM PDT 24
Peak memory 200764 kb
Host smart-77c24a8b-650a-4c0c-9e6f-fd8af48e13bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918869737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1918869737
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3569953620
Short name T564
Test name
Test status
Simulation time 2524841755 ps
CPU time 2.41 seconds
Started Aug 01 05:24:48 PM PDT 24
Finished Aug 01 05:24:51 PM PDT 24
Peak memory 200800 kb
Host smart-a5b1916d-a596-41ed-897e-1c52ee6df31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569953620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3569953620
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.1834587526
Short name T422
Test name
Test status
Simulation time 2111152761 ps
CPU time 5.73 seconds
Started Aug 01 05:24:46 PM PDT 24
Finished Aug 01 05:24:52 PM PDT 24
Peak memory 200604 kb
Host smart-20ab4ee6-3729-44e3-9b7e-64fe08a7da6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834587526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1834587526
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.2386008767
Short name T541
Test name
Test status
Simulation time 174169583748 ps
CPU time 451.31 seconds
Started Aug 01 05:25:01 PM PDT 24
Finished Aug 01 05:32:32 PM PDT 24
Peak memory 200956 kb
Host smart-fad4377f-c1da-4d2d-9d8b-32352c6c1922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386008767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.2386008767
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.315107792
Short name T764
Test name
Test status
Simulation time 30544368264 ps
CPU time 18.26 seconds
Started Aug 01 05:25:00 PM PDT 24
Finished Aug 01 05:25:19 PM PDT 24
Peak memory 217516 kb
Host smart-7ebe30c4-9d7f-434b-a559-e445aa079f16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315107792 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.315107792
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.2787222714
Short name T571
Test name
Test status
Simulation time 2012053107 ps
CPU time 5.33 seconds
Started Aug 01 05:25:08 PM PDT 24
Finished Aug 01 05:25:14 PM PDT 24
Peak memory 200648 kb
Host smart-acea3e0a-46aa-4d6d-805e-d0d50b06c752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787222714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.2787222714
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1484277153
Short name T262
Test name
Test status
Simulation time 3224341761 ps
CPU time 2.88 seconds
Started Aug 01 05:25:01 PM PDT 24
Finished Aug 01 05:25:04 PM PDT 24
Peak memory 200848 kb
Host smart-aa9c6dea-6ead-4130-a51e-4a1c56386c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484277153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
484277153
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.2171942965
Short name T693
Test name
Test status
Simulation time 26084320946 ps
CPU time 14.43 seconds
Started Aug 01 05:25:02 PM PDT 24
Finished Aug 01 05:25:17 PM PDT 24
Peak memory 201096 kb
Host smart-c1b4472e-b054-45af-a0d7-1f69c2c17ebe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171942965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.2171942965
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3037630261
Short name T619
Test name
Test status
Simulation time 66004183782 ps
CPU time 43.08 seconds
Started Aug 01 05:24:57 PM PDT 24
Finished Aug 01 05:25:41 PM PDT 24
Peak memory 201140 kb
Host smart-cc3d43eb-fbc8-41ed-b9e5-648b32372d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037630261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.3037630261
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.838937544
Short name T126
Test name
Test status
Simulation time 2585885915 ps
CPU time 6.7 seconds
Started Aug 01 05:24:58 PM PDT 24
Finished Aug 01 05:25:05 PM PDT 24
Peak memory 200728 kb
Host smart-b31f8088-c781-46f6-8059-3e8c10ab2de4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838937544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.838937544
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3040373254
Short name T737
Test name
Test status
Simulation time 2915243654 ps
CPU time 2.34 seconds
Started Aug 01 05:24:58 PM PDT 24
Finished Aug 01 05:25:00 PM PDT 24
Peak memory 200772 kb
Host smart-fb39befd-87f6-418f-aa0c-ba267399f293
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040373254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.3040373254
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2977126916
Short name T472
Test name
Test status
Simulation time 2629740989 ps
CPU time 2.58 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:12 PM PDT 24
Peak memory 200700 kb
Host smart-84dd2c12-931b-4dc8-a435-bfc9a3ecd58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977126916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2977126916
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3269086560
Short name T615
Test name
Test status
Simulation time 2493883047 ps
CPU time 3.52 seconds
Started Aug 01 05:24:57 PM PDT 24
Finished Aug 01 05:25:01 PM PDT 24
Peak memory 200680 kb
Host smart-b31a0b19-92e0-4bae-82bc-d3308efc7c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269086560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3269086560
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.511272938
Short name T501
Test name
Test status
Simulation time 2248077394 ps
CPU time 2.07 seconds
Started Aug 01 05:24:56 PM PDT 24
Finished Aug 01 05:24:59 PM PDT 24
Peak memory 200740 kb
Host smart-1897098b-a8f9-483f-a26f-53963e07be4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511272938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.511272938
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.4247902882
Short name T198
Test name
Test status
Simulation time 2537124326 ps
CPU time 2.28 seconds
Started Aug 01 05:25:03 PM PDT 24
Finished Aug 01 05:25:05 PM PDT 24
Peak memory 200816 kb
Host smart-36fdf084-7ff9-4b78-834a-b027456e783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247902882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.4247902882
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.2086550939
Short name T758
Test name
Test status
Simulation time 2141706002 ps
CPU time 1.45 seconds
Started Aug 01 05:25:05 PM PDT 24
Finished Aug 01 05:25:06 PM PDT 24
Peak memory 200656 kb
Host smart-fa162f93-e276-48ab-8195-0b8782de2561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086550939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2086550939
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1757251784
Short name T650
Test name
Test status
Simulation time 89631855140 ps
CPU time 120.65 seconds
Started Aug 01 05:25:01 PM PDT 24
Finished Aug 01 05:27:02 PM PDT 24
Peak memory 201016 kb
Host smart-8e96728f-7607-4926-a4ca-0d9edf8c6597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757251784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1757251784
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2512904258
Short name T313
Test name
Test status
Simulation time 13342856922 ps
CPU time 34.33 seconds
Started Aug 01 05:25:05 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 211400 kb
Host smart-dd27bdf3-ecb4-4730-8e1d-8d6e38ca3ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512904258 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2512904258
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1237860765
Short name T433
Test name
Test status
Simulation time 2014123875 ps
CPU time 5.26 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:24:08 PM PDT 24
Peak memory 200764 kb
Host smart-31f6faa5-0df1-4377-b41c-6ce1c4d171c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237860765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1237860765
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3691972735
Short name T612
Test name
Test status
Simulation time 3196649202 ps
CPU time 8.42 seconds
Started Aug 01 05:24:09 PM PDT 24
Finished Aug 01 05:24:18 PM PDT 24
Peak memory 200804 kb
Host smart-321bd303-c416-41af-be94-044abe25af1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691972735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3691972735
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3247813357
Short name T152
Test name
Test status
Simulation time 2434490124 ps
CPU time 2.03 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:24:05 PM PDT 24
Peak memory 200792 kb
Host smart-1976eeb3-1a9a-44d1-a3d8-423ad5ed1dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247813357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3247813357
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1790640340
Short name T31
Test name
Test status
Simulation time 2513828651 ps
CPU time 4.06 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:24:07 PM PDT 24
Peak memory 200780 kb
Host smart-569b31d9-d195-461b-ac1b-f9fff73fcb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790640340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1790640340
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2546318233
Short name T547
Test name
Test status
Simulation time 5079779713 ps
CPU time 4.14 seconds
Started Aug 01 05:24:02 PM PDT 24
Finished Aug 01 05:24:06 PM PDT 24
Peak memory 200724 kb
Host smart-c4bda111-c47b-443d-9d97-375867d83242
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546318233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2546318233
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3349898105
Short name T254
Test name
Test status
Simulation time 2570292462 ps
CPU time 3.38 seconds
Started Aug 01 05:24:04 PM PDT 24
Finished Aug 01 05:24:08 PM PDT 24
Peak memory 200840 kb
Host smart-402663e6-1fd7-4900-9ace-7518757cd78c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349898105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.3349898105
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1460193931
Short name T710
Test name
Test status
Simulation time 2614667390 ps
CPU time 7.55 seconds
Started Aug 01 05:24:06 PM PDT 24
Finished Aug 01 05:24:14 PM PDT 24
Peak memory 200780 kb
Host smart-10720054-268b-497d-bf6c-69eec6d27bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460193931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1460193931
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3733941723
Short name T134
Test name
Test status
Simulation time 2460773369 ps
CPU time 6.85 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:24:10 PM PDT 24
Peak memory 200788 kb
Host smart-3f5a8960-891a-4cb8-b4a0-98900dc83c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733941723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3733941723
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.3654330617
Short name T86
Test name
Test status
Simulation time 2248766847 ps
CPU time 3.39 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:24:06 PM PDT 24
Peak memory 200744 kb
Host smart-d3d1874d-317a-4ac8-8c66-c1ba48a28445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654330617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3654330617
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3601673367
Short name T24
Test name
Test status
Simulation time 2509101689 ps
CPU time 6.89 seconds
Started Aug 01 05:24:04 PM PDT 24
Finished Aug 01 05:24:11 PM PDT 24
Peak memory 200656 kb
Host smart-46c1c86a-df7f-4c40-b7a8-3f959384b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601673367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3601673367
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2742225653
Short name T79
Test name
Test status
Simulation time 42439219230 ps
CPU time 13.09 seconds
Started Aug 01 05:24:07 PM PDT 24
Finished Aug 01 05:24:21 PM PDT 24
Peak memory 220524 kb
Host smart-bf36a1a8-0202-4023-ae8f-3e82847a6769
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742225653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2742225653
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.2308100725
Short name T760
Test name
Test status
Simulation time 2113358796 ps
CPU time 3.43 seconds
Started Aug 01 05:23:56 PM PDT 24
Finished Aug 01 05:23:59 PM PDT 24
Peak memory 200648 kb
Host smart-a3bdb8ec-d7d9-41c3-87c5-4c671cf15654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308100725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.2308100725
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.830579854
Short name T316
Test name
Test status
Simulation time 11573096571 ps
CPU time 4.03 seconds
Started Aug 01 05:24:02 PM PDT 24
Finished Aug 01 05:24:06 PM PDT 24
Peak memory 200836 kb
Host smart-2bc1e1a8-e476-4400-be39-113da26a96c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830579854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str
ess_all.830579854
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1741230424
Short name T718
Test name
Test status
Simulation time 524036485552 ps
CPU time 144.53 seconds
Started Aug 01 05:24:01 PM PDT 24
Finished Aug 01 05:26:26 PM PDT 24
Peak memory 209440 kb
Host smart-b25567ad-2977-40f4-bc69-2852d341799a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741230424 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1741230424
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3850910204
Short name T745
Test name
Test status
Simulation time 469746837094 ps
CPU time 75.29 seconds
Started Aug 01 05:24:07 PM PDT 24
Finished Aug 01 05:25:22 PM PDT 24
Peak memory 200792 kb
Host smart-c466c52d-f617-461b-9c19-87d74ddddc34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850910204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3850910204
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3835552661
Short name T691
Test name
Test status
Simulation time 2013220408 ps
CPU time 5.83 seconds
Started Aug 01 05:25:05 PM PDT 24
Finished Aug 01 05:25:11 PM PDT 24
Peak memory 200728 kb
Host smart-f68763b4-b2e7-4ea8-b501-a8446a8287a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835552661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3835552661
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1238679743
Short name T26
Test name
Test status
Simulation time 2992412467 ps
CPU time 2.46 seconds
Started Aug 01 05:25:04 PM PDT 24
Finished Aug 01 05:25:07 PM PDT 24
Peak memory 200788 kb
Host smart-cf10f021-a5a8-4614-a78e-e327f341ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238679743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.1
238679743
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.375541028
Short name T113
Test name
Test status
Simulation time 159348645750 ps
CPU time 101.37 seconds
Started Aug 01 05:25:00 PM PDT 24
Finished Aug 01 05:26:42 PM PDT 24
Peak memory 200952 kb
Host smart-b5e441af-fdfb-4141-b91b-9bf4f6e4f643
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375541028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.375541028
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3646970030
Short name T367
Test name
Test status
Simulation time 54386293501 ps
CPU time 65.77 seconds
Started Aug 01 05:25:06 PM PDT 24
Finished Aug 01 05:26:12 PM PDT 24
Peak memory 201024 kb
Host smart-040b3f8e-fafb-46b2-8bc2-c75e9247522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646970030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.3646970030
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3521545207
Short name T253
Test name
Test status
Simulation time 4883860237 ps
CPU time 12.83 seconds
Started Aug 01 05:25:04 PM PDT 24
Finished Aug 01 05:25:17 PM PDT 24
Peak memory 200744 kb
Host smart-1bba8a5d-5955-4450-8c89-f2b77deb9912
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521545207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3521545207
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3406144508
Short name T515
Test name
Test status
Simulation time 2821091267 ps
CPU time 2.08 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:13 PM PDT 24
Peak memory 200760 kb
Host smart-2c03d0b4-6633-48e5-9159-2f1bc7351453
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406144508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3406144508
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.673542578
Short name T194
Test name
Test status
Simulation time 2609706992 ps
CPU time 6.78 seconds
Started Aug 01 05:24:58 PM PDT 24
Finished Aug 01 05:25:05 PM PDT 24
Peak memory 200736 kb
Host smart-8cad7ead-ab3c-4f92-a324-3b8628bda10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673542578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.673542578
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.738467003
Short name T629
Test name
Test status
Simulation time 2450034225 ps
CPU time 7.62 seconds
Started Aug 01 05:25:02 PM PDT 24
Finished Aug 01 05:25:10 PM PDT 24
Peak memory 200792 kb
Host smart-87d124e0-5081-45d0-824c-aafea3b22475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738467003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.738467003
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3705501252
Short name T685
Test name
Test status
Simulation time 2059503406 ps
CPU time 3.11 seconds
Started Aug 01 05:24:58 PM PDT 24
Finished Aug 01 05:25:01 PM PDT 24
Peak memory 200716 kb
Host smart-94af2577-e8ec-4e08-8474-62391ca75ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705501252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3705501252
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.220529320
Short name T418
Test name
Test status
Simulation time 2561759968 ps
CPU time 1.45 seconds
Started Aug 01 05:24:58 PM PDT 24
Finished Aug 01 05:25:00 PM PDT 24
Peak memory 200016 kb
Host smart-5abe85c4-f9f1-4625-98c5-9b34ab608748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220529320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.220529320
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.580300373
Short name T610
Test name
Test status
Simulation time 2150090562 ps
CPU time 1.5 seconds
Started Aug 01 05:24:57 PM PDT 24
Finished Aug 01 05:24:58 PM PDT 24
Peak memory 200760 kb
Host smart-cb9ec8e9-949c-40e0-9d70-996a8df6a66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580300373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.580300373
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3902212394
Short name T500
Test name
Test status
Simulation time 11714691536 ps
CPU time 32.06 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:42 PM PDT 24
Peak memory 200720 kb
Host smart-ef691065-ec35-4708-86b9-c6863a1fe57f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902212394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3902212394
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.971518726
Short name T175
Test name
Test status
Simulation time 24701750368 ps
CPU time 63.7 seconds
Started Aug 01 05:25:06 PM PDT 24
Finished Aug 01 05:26:10 PM PDT 24
Peak memory 209368 kb
Host smart-f5c8dc5f-57b9-4aa8-9519-c509d5af6318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971518726 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.971518726
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.720827463
Short name T160
Test name
Test status
Simulation time 4729689284 ps
CPU time 2.08 seconds
Started Aug 01 05:25:06 PM PDT 24
Finished Aug 01 05:25:08 PM PDT 24
Peak memory 200780 kb
Host smart-fd057c6b-2f4b-4353-a310-9e795e1d0ebd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720827463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ultra_low_pwr.720827463
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.3989272996
Short name T460
Test name
Test status
Simulation time 2009513476 ps
CPU time 5.77 seconds
Started Aug 01 05:25:08 PM PDT 24
Finished Aug 01 05:25:14 PM PDT 24
Peak memory 200812 kb
Host smart-3c5cf495-b473-40cf-903a-0d01ebb2ecb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989272996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.3989272996
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2174297170
Short name T548
Test name
Test status
Simulation time 3601705569 ps
CPU time 2.8 seconds
Started Aug 01 05:24:57 PM PDT 24
Finished Aug 01 05:25:00 PM PDT 24
Peak memory 200828 kb
Host smart-e9f2b1be-589e-43b0-bb39-162cadff7548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174297170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.2
174297170
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.215806348
Short name T749
Test name
Test status
Simulation time 155375960514 ps
CPU time 203.33 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:28:33 PM PDT 24
Peak memory 201012 kb
Host smart-056630d1-d6bf-48a2-886a-eb390d79c0c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215806348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_combo_detect.215806348
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1302212152
Short name T769
Test name
Test status
Simulation time 51767026030 ps
CPU time 32.87 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:43 PM PDT 24
Peak memory 200964 kb
Host smart-4d0fbc64-a5dd-4ede-b627-12062344dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302212152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.1302212152
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2843876786
Short name T420
Test name
Test status
Simulation time 5957474023 ps
CPU time 4.72 seconds
Started Aug 01 05:24:59 PM PDT 24
Finished Aug 01 05:25:04 PM PDT 24
Peak memory 200772 kb
Host smart-9fc07c13-bef6-4a08-a07e-f6878b7cb142
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843876786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.2843876786
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3993642900
Short name T489
Test name
Test status
Simulation time 2599546180 ps
CPU time 2.07 seconds
Started Aug 01 05:25:08 PM PDT 24
Finished Aug 01 05:25:10 PM PDT 24
Peak memory 200820 kb
Host smart-85646b18-6e73-4c28-ad8f-83769f091bc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993642900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3993642900
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1906506650
Short name T209
Test name
Test status
Simulation time 2613454399 ps
CPU time 6.65 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:17 PM PDT 24
Peak memory 200700 kb
Host smart-fa7a400c-5a0c-49a4-9b29-4aa424f9859e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906506650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.1906506650
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2802391037
Short name T445
Test name
Test status
Simulation time 2463382229 ps
CPU time 5.25 seconds
Started Aug 01 05:25:06 PM PDT 24
Finished Aug 01 05:25:11 PM PDT 24
Peak memory 200732 kb
Host smart-94084286-f500-4570-8fdf-9cecf78f204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802391037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2802391037
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3495299723
Short name T332
Test name
Test status
Simulation time 2045431572 ps
CPU time 5.64 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:15 PM PDT 24
Peak memory 200648 kb
Host smart-36c51e9d-1d0a-4ad5-b2c3-5ab6fbec0e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495299723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3495299723
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3205727503
Short name T442
Test name
Test status
Simulation time 2519949798 ps
CPU time 3.78 seconds
Started Aug 01 05:25:07 PM PDT 24
Finished Aug 01 05:25:11 PM PDT 24
Peak memory 200736 kb
Host smart-c36cac2b-ee7b-40d5-b218-0397df403f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205727503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3205727503
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.2726303873
Short name T470
Test name
Test status
Simulation time 2110910044 ps
CPU time 6.13 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:16 PM PDT 24
Peak memory 200640 kb
Host smart-ded764f0-0910-4427-adb9-c6454fc76393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726303873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2726303873
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.3862355761
Short name T616
Test name
Test status
Simulation time 10530575192 ps
CPU time 3.27 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:13 PM PDT 24
Peak memory 200852 kb
Host smart-a5992ebf-5cc0-4043-b085-1f85103a8e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862355761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.3862355761
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.999141688
Short name T398
Test name
Test status
Simulation time 3379009670 ps
CPU time 2.62 seconds
Started Aug 01 05:24:58 PM PDT 24
Finished Aug 01 05:25:01 PM PDT 24
Peak memory 200836 kb
Host smart-51aefe82-b788-4255-b5d3-3de15ccbce4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999141688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ultra_low_pwr.999141688
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3916634219
Short name T435
Test name
Test status
Simulation time 2011731192 ps
CPU time 5.64 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:16 PM PDT 24
Peak memory 200860 kb
Host smart-567333fc-3d52-4f61-a8ca-7b23ca8a1bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916634219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3916634219
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1547582507
Short name T48
Test name
Test status
Simulation time 3287895081 ps
CPU time 8.88 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:18 PM PDT 24
Peak memory 200840 kb
Host smart-b9fb4c50-c0e4-458a-ba93-9cb658e87e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547582507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1
547582507
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1495342989
Short name T101
Test name
Test status
Simulation time 23080410265 ps
CPU time 7.29 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:16 PM PDT 24
Peak memory 201016 kb
Host smart-0cb2435e-d149-481c-9785-9123179f1627
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495342989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1495342989
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3923996998
Short name T722
Test name
Test status
Simulation time 81234624511 ps
CPU time 204.95 seconds
Started Aug 01 05:25:08 PM PDT 24
Finished Aug 01 05:28:33 PM PDT 24
Peak memory 201096 kb
Host smart-5db26462-68e3-4ee5-8a5b-fba33005dff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923996998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.3923996998
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.140620976
Short name T676
Test name
Test status
Simulation time 3667255959 ps
CPU time 10.03 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:21 PM PDT 24
Peak memory 200724 kb
Host smart-8bd4c620-cdf6-4f59-becf-b654abae1f4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140620976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ec_pwr_on_rst.140620976
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.492072319
Short name T493
Test name
Test status
Simulation time 3001495959 ps
CPU time 6.53 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:17 PM PDT 24
Peak memory 200860 kb
Host smart-2e2d774d-37b8-4e72-a0df-b9f2476a56ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492072319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctr
l_edge_detect.492072319
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2555591714
Short name T535
Test name
Test status
Simulation time 2674132924 ps
CPU time 1.03 seconds
Started Aug 01 05:25:08 PM PDT 24
Finished Aug 01 05:25:09 PM PDT 24
Peak memory 200764 kb
Host smart-9f0dc3f7-262e-424b-b224-fe842fbe3365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555591714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.2555591714
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.3926121066
Short name T62
Test name
Test status
Simulation time 2476766949 ps
CPU time 2.11 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:12 PM PDT 24
Peak memory 200804 kb
Host smart-06446ec3-76e4-444a-a723-dc5fb45bbebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926121066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3926121066
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1401017788
Short name T562
Test name
Test status
Simulation time 2074831002 ps
CPU time 2.02 seconds
Started Aug 01 05:25:07 PM PDT 24
Finished Aug 01 05:25:09 PM PDT 24
Peak memory 200748 kb
Host smart-cddd32ab-36a9-48bf-9445-5ac37b3ba0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401017788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1401017788
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2977691756
Short name T742
Test name
Test status
Simulation time 2513415183 ps
CPU time 4.12 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:15 PM PDT 24
Peak memory 200676 kb
Host smart-eff77c36-988f-407f-87a3-40e951d8b4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977691756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2977691756
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.2005479400
Short name T633
Test name
Test status
Simulation time 2114334193 ps
CPU time 3.43 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:13 PM PDT 24
Peak memory 200768 kb
Host smart-8beb67a1-6d57-403b-8e48-8abdf975462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005479400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2005479400
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.1619884991
Short name T208
Test name
Test status
Simulation time 17133511425 ps
CPU time 32.93 seconds
Started Aug 01 05:25:13 PM PDT 24
Finished Aug 01 05:25:46 PM PDT 24
Peak memory 200772 kb
Host smart-5e209833-2769-40a1-a1e3-5762dd41ceb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619884991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.1619884991
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2822053221
Short name T20
Test name
Test status
Simulation time 22926531097 ps
CPU time 23.96 seconds
Started Aug 01 05:25:07 PM PDT 24
Finished Aug 01 05:25:31 PM PDT 24
Peak memory 216904 kb
Host smart-7fb908c9-7abf-4fd4-9524-f228b1a6bf6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822053221 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2822053221
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3852834707
Short name T159
Test name
Test status
Simulation time 6440511161 ps
CPU time 7.77 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:17 PM PDT 24
Peak memory 200844 kb
Host smart-4d4837c8-d26c-4d02-a95a-ec1b22a7bb8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852834707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3852834707
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1542057398
Short name T707
Test name
Test status
Simulation time 2017706821 ps
CPU time 5.67 seconds
Started Aug 01 05:25:24 PM PDT 24
Finished Aug 01 05:25:29 PM PDT 24
Peak memory 200804 kb
Host smart-33278de2-796b-4da3-a36e-67b2d8a68fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542057398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1542057398
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.1180953371
Short name T696
Test name
Test status
Simulation time 3034623436 ps
CPU time 2.01 seconds
Started Aug 01 05:25:11 PM PDT 24
Finished Aug 01 05:25:13 PM PDT 24
Peak memory 200808 kb
Host smart-91a5c22c-d7bb-450e-8b9e-17de5bc8c22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180953371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.1
180953371
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.2553304692
Short name T682
Test name
Test status
Simulation time 87601057511 ps
CPU time 58.85 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:26:19 PM PDT 24
Peak memory 201000 kb
Host smart-58ecaa42-5a73-4c13-b68c-c41d893b696e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553304692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.2553304692
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2510552559
Short name T690
Test name
Test status
Simulation time 3863182246 ps
CPU time 3.37 seconds
Started Aug 01 05:25:10 PM PDT 24
Finished Aug 01 05:25:14 PM PDT 24
Peak memory 200788 kb
Host smart-2646a157-d5a8-489d-82c7-95bc4919599a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510552559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.2510552559
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2814073239
Short name T130
Test name
Test status
Simulation time 4215549830 ps
CPU time 6.49 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:29 PM PDT 24
Peak memory 200848 kb
Host smart-ff92cff2-4f42-4447-97ed-86e620ce8c49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814073239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.2814073239
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1875960447
Short name T622
Test name
Test status
Simulation time 2678404259 ps
CPU time 1.28 seconds
Started Aug 01 05:25:07 PM PDT 24
Finished Aug 01 05:25:08 PM PDT 24
Peak memory 200736 kb
Host smart-d7447c59-a761-47a2-9978-8359c587332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875960447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1875960447
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2481443029
Short name T463
Test name
Test status
Simulation time 2468137552 ps
CPU time 4.22 seconds
Started Aug 01 05:25:08 PM PDT 24
Finished Aug 01 05:25:12 PM PDT 24
Peak memory 200748 kb
Host smart-556935c0-f307-42c6-a64e-28cdf5a1f9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481443029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2481443029
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1678372378
Short name T476
Test name
Test status
Simulation time 2297638804 ps
CPU time 1.9 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:11 PM PDT 24
Peak memory 200692 kb
Host smart-17c09668-4163-4bb1-a2c8-6e4569532af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678372378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1678372378
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3688977307
Short name T426
Test name
Test status
Simulation time 2530708871 ps
CPU time 2.13 seconds
Started Aug 01 05:25:11 PM PDT 24
Finished Aug 01 05:25:13 PM PDT 24
Peak memory 200744 kb
Host smart-174d2b0f-af42-4998-8431-21b1d9d3c0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688977307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.3688977307
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.1608431986
Short name T188
Test name
Test status
Simulation time 2118543515 ps
CPU time 3.16 seconds
Started Aug 01 05:25:09 PM PDT 24
Finished Aug 01 05:25:12 PM PDT 24
Peak memory 200748 kb
Host smart-c61e32c0-9813-436a-8276-d4ec08caaed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608431986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.1608431986
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.2446059081
Short name T261
Test name
Test status
Simulation time 11170409080 ps
CPU time 14.81 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:37 PM PDT 24
Peak memory 200724 kb
Host smart-1d0d3d95-58b6-413b-aa39-ba57d3d1975d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446059081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.2446059081
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3553927209
Short name T156
Test name
Test status
Simulation time 616868744617 ps
CPU time 42.68 seconds
Started Aug 01 05:25:21 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200896 kb
Host smart-fbcf8e4d-e1c9-4730-9bfc-7d2669a6029d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553927209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.3553927209
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.4025771784
Short name T441
Test name
Test status
Simulation time 2021022836 ps
CPU time 3.29 seconds
Started Aug 01 05:25:19 PM PDT 24
Finished Aug 01 05:25:22 PM PDT 24
Peak memory 201044 kb
Host smart-fd0e6836-b8f7-4979-9148-414bdd062169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025771784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.4025771784
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2957142549
Short name T44
Test name
Test status
Simulation time 3606129144 ps
CPU time 10.19 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:32 PM PDT 24
Peak memory 200864 kb
Host smart-3fc3abc0-ab17-4da0-aaa3-57e406c8678f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957142549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2
957142549
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.542136447
Short name T110
Test name
Test status
Simulation time 26863758069 ps
CPU time 18.55 seconds
Started Aug 01 05:25:27 PM PDT 24
Finished Aug 01 05:25:45 PM PDT 24
Peak memory 201184 kb
Host smart-52fad71a-cd9e-4648-87e3-e093f846742d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542136447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_wi
th_pre_cond.542136447
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.292509068
Short name T736
Test name
Test status
Simulation time 3274953437 ps
CPU time 4.69 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:27 PM PDT 24
Peak memory 200724 kb
Host smart-1c508258-15b6-4753-88b8-c670e461ad6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292509068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.292509068
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2036307430
Short name T248
Test name
Test status
Simulation time 836025801917 ps
CPU time 166.07 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:28:08 PM PDT 24
Peak memory 200828 kb
Host smart-f4cb285a-92e8-40ff-b638-73ae97620e15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036307430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.2036307430
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2066168944
Short name T714
Test name
Test status
Simulation time 2636537870 ps
CPU time 2.04 seconds
Started Aug 01 05:25:19 PM PDT 24
Finished Aug 01 05:25:21 PM PDT 24
Peak memory 200760 kb
Host smart-138c3aa5-4d1f-4073-ba51-42c3e471b60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066168944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.2066168944
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3284466660
Short name T60
Test name
Test status
Simulation time 2462870088 ps
CPU time 3.48 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:25:24 PM PDT 24
Peak memory 200692 kb
Host smart-57a8ba1f-5836-47b6-9f77-e727aff37cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284466660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3284466660
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1821680864
Short name T601
Test name
Test status
Simulation time 2038889217 ps
CPU time 5.9 seconds
Started Aug 01 05:25:24 PM PDT 24
Finished Aug 01 05:25:30 PM PDT 24
Peak memory 200688 kb
Host smart-4b879a7b-e269-462e-bd93-2f7e443c5860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821680864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1821680864
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1981338917
Short name T482
Test name
Test status
Simulation time 2510728103 ps
CPU time 7.03 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:25:27 PM PDT 24
Peak memory 200860 kb
Host smart-556c1b37-9bb5-4b58-9d0c-48a7220c165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981338917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1981338917
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.2825147869
Short name T640
Test name
Test status
Simulation time 2111656742 ps
CPU time 6.29 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:25:27 PM PDT 24
Peak memory 200740 kb
Host smart-10cc7263-cd96-4eaa-b1d3-88a18478a4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825147869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.2825147869
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2378989752
Short name T104
Test name
Test status
Simulation time 8180101627 ps
CPU time 7.12 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:30 PM PDT 24
Peak memory 200804 kb
Host smart-f9f32300-f5c9-4770-aad8-229281f838f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378989752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2378989752
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1139054895
Short name T444
Test name
Test status
Simulation time 6562036723 ps
CPU time 2.2 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:25:22 PM PDT 24
Peak memory 200860 kb
Host smart-8c88615d-0bc1-4101-a8ee-bf7f53d38e0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139054895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1139054895
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.75043268
Short name T205
Test name
Test status
Simulation time 2016757701 ps
CPU time 3.07 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:25:23 PM PDT 24
Peak memory 200792 kb
Host smart-fb870e54-b22f-41ca-94af-0b2762b592fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75043268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test
.75043268
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.344587021
Short name T135
Test name
Test status
Simulation time 146492292847 ps
CPU time 43.79 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200916 kb
Host smart-90f63d00-df47-438e-8e2a-f4faa71f207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344587021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.344587021
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2842371507
Short name T121
Test name
Test status
Simulation time 52557206635 ps
CPU time 37.16 seconds
Started Aug 01 05:25:19 PM PDT 24
Finished Aug 01 05:25:56 PM PDT 24
Peak memory 201008 kb
Host smart-33aac19b-6f0f-4c67-bde9-30fbfdf18536
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842371507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2842371507
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3165147997
Short name T733
Test name
Test status
Simulation time 84810698694 ps
CPU time 52.49 seconds
Started Aug 01 05:25:25 PM PDT 24
Finished Aug 01 05:26:17 PM PDT 24
Peak memory 201140 kb
Host smart-0aa0189b-f1f3-47fa-9953-d1ea320de627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165147997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.3165147997
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4238488653
Short name T540
Test name
Test status
Simulation time 3755546769 ps
CPU time 5.82 seconds
Started Aug 01 05:25:23 PM PDT 24
Finished Aug 01 05:25:28 PM PDT 24
Peak memory 200856 kb
Host smart-3bd58005-892c-446b-806a-ba7ecc81b1dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238488653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.4238488653
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.209938216
Short name T225
Test name
Test status
Simulation time 4876217293 ps
CPU time 12.25 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200864 kb
Host smart-4a9c0694-e9a3-4772-9d30-08d35bb5b82a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209938216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctr
l_edge_detect.209938216
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3539349047
Short name T234
Test name
Test status
Simulation time 2646924107 ps
CPU time 1.74 seconds
Started Aug 01 05:25:23 PM PDT 24
Finished Aug 01 05:25:25 PM PDT 24
Peak memory 200788 kb
Host smart-e24f4f8f-6ac9-4bdd-925a-fafc3575b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539349047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3539349047
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.187827705
Short name T608
Test name
Test status
Simulation time 2500044634 ps
CPU time 1.68 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:24 PM PDT 24
Peak memory 200680 kb
Host smart-0e37b8fe-9fa7-4b33-8480-e5914f8e3575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187827705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.187827705
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.375318701
Short name T397
Test name
Test status
Simulation time 2192473216 ps
CPU time 3.59 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:26 PM PDT 24
Peak memory 200772 kb
Host smart-69ce6e9b-2c0d-40c3-acfb-64f0c1ec8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375318701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.375318701
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1592964693
Short name T320
Test name
Test status
Simulation time 2510668723 ps
CPU time 7.08 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:29 PM PDT 24
Peak memory 200728 kb
Host smart-bd72ceaf-e953-4277-a942-e2293a0b0e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592964693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1592964693
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.4134200275
Short name T50
Test name
Test status
Simulation time 2130518014 ps
CPU time 1.91 seconds
Started Aug 01 05:25:21 PM PDT 24
Finished Aug 01 05:25:23 PM PDT 24
Peak memory 200724 kb
Host smart-39445caa-c58f-44ec-8162-8c0e08b7dd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134200275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.4134200275
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.158244529
Short name T708
Test name
Test status
Simulation time 14798299944 ps
CPU time 19.53 seconds
Started Aug 01 05:25:23 PM PDT 24
Finished Aug 01 05:25:43 PM PDT 24
Peak memory 200848 kb
Host smart-58527cb4-afde-477f-92e7-fe1df36cf597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158244529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_st
ress_all.158244529
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4126819884
Short name T157
Test name
Test status
Simulation time 5849577768 ps
CPU time 7.09 seconds
Started Aug 01 05:25:21 PM PDT 24
Finished Aug 01 05:25:28 PM PDT 24
Peak memory 200744 kb
Host smart-04d9b58f-a4d7-4392-91a3-0c3fb672a722
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126819884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.4126819884
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.782004129
Short name T436
Test name
Test status
Simulation time 2014809190 ps
CPU time 5.36 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:28 PM PDT 24
Peak memory 200748 kb
Host smart-117fa713-c1b0-468a-b0ef-176e808c68cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782004129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_tes
t.782004129
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2048988377
Short name T467
Test name
Test status
Simulation time 3304293871 ps
CPU time 8.59 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:30 PM PDT 24
Peak memory 200808 kb
Host smart-bcfbd4bc-1edf-4639-8d1f-48836dcae65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048988377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
048988377
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1148544411
Short name T347
Test name
Test status
Simulation time 36632798678 ps
CPU time 48.29 seconds
Started Aug 01 05:25:26 PM PDT 24
Finished Aug 01 05:26:15 PM PDT 24
Peak memory 201072 kb
Host smart-15e705f8-13e8-44d6-a04b-cef7f7d414b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148544411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.1148544411
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3825488924
Short name T6
Test name
Test status
Simulation time 25848820687 ps
CPU time 16.79 seconds
Started Aug 01 05:25:28 PM PDT 24
Finished Aug 01 05:25:45 PM PDT 24
Peak memory 201188 kb
Host smart-3933421f-f670-4040-9275-06e531c73145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825488924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3825488924
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.22996658
Short name T536
Test name
Test status
Simulation time 2962976608 ps
CPU time 2.42 seconds
Started Aug 01 05:25:21 PM PDT 24
Finished Aug 01 05:25:24 PM PDT 24
Peak memory 200740 kb
Host smart-4010eb9f-cf7f-4572-8fd4-775b955bd086
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22996658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_ec_pwr_on_rst.22996658
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.1414310231
Short name T317
Test name
Test status
Simulation time 3101468219 ps
CPU time 7.81 seconds
Started Aug 01 05:25:20 PM PDT 24
Finished Aug 01 05:25:28 PM PDT 24
Peak memory 200804 kb
Host smart-d1ace3e3-1337-4be3-b27f-861ac0f6d4f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414310231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.1414310231
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2202133755
Short name T508
Test name
Test status
Simulation time 2627150329 ps
CPU time 2.29 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:25 PM PDT 24
Peak memory 200724 kb
Host smart-00c38c2a-5914-4e0b-adc1-5e599ae9500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202133755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.2202133755
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3128428293
Short name T698
Test name
Test status
Simulation time 2450088351 ps
CPU time 7.52 seconds
Started Aug 01 05:25:22 PM PDT 24
Finished Aug 01 05:25:30 PM PDT 24
Peak memory 200748 kb
Host smart-a34ae476-a1cc-4895-8932-baf82cecd535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128428293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.3128428293
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.439759148
Short name T783
Test name
Test status
Simulation time 2125224287 ps
CPU time 5.7 seconds
Started Aug 01 05:25:23 PM PDT 24
Finished Aug 01 05:25:29 PM PDT 24
Peak memory 200720 kb
Host smart-c5eeda5c-503b-49e9-ae48-00f3aabf2d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439759148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.439759148
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.1191922143
Short name T321
Test name
Test status
Simulation time 2510799542 ps
CPU time 6.23 seconds
Started Aug 01 05:25:27 PM PDT 24
Finished Aug 01 05:25:34 PM PDT 24
Peak memory 200864 kb
Host smart-b0465a31-9f3d-4b30-bbf1-baef77eba5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191922143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.1191922143
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.484038101
Short name T15
Test name
Test status
Simulation time 2140639463 ps
CPU time 1.7 seconds
Started Aug 01 05:25:21 PM PDT 24
Finished Aug 01 05:25:23 PM PDT 24
Peak memory 200712 kb
Host smart-367dfd53-8cac-4936-bd1d-4d2a840d22ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484038101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.484038101
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3503386711
Short name T53
Test name
Test status
Simulation time 816554283730 ps
CPU time 2064.02 seconds
Started Aug 01 05:25:25 PM PDT 24
Finished Aug 01 05:59:49 PM PDT 24
Peak memory 200776 kb
Host smart-eb80b55b-34f9-4196-bde9-e959f212338f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503386711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3503386711
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1267951729
Short name T182
Test name
Test status
Simulation time 1691121426488 ps
CPU time 625.9 seconds
Started Aug 01 05:25:27 PM PDT 24
Finished Aug 01 05:35:53 PM PDT 24
Peak memory 209548 kb
Host smart-318916c1-4344-4ad2-872e-5f6cba9bc489
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267951729 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.1267951729
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.3837851856
Short name T138
Test name
Test status
Simulation time 3734212365 ps
CPU time 3.75 seconds
Started Aug 01 05:25:25 PM PDT 24
Finished Aug 01 05:25:29 PM PDT 24
Peak memory 200840 kb
Host smart-3bdef514-1b6b-4348-95f3-783f2a311422
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837851856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.3837851856
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.913359652
Short name T697
Test name
Test status
Simulation time 2014667848 ps
CPU time 3.07 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:36 PM PDT 24
Peak memory 200728 kb
Host smart-4158f799-3ad3-465a-b6b3-e9c2995aef48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913359652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.913359652
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2847983241
Short name T704
Test name
Test status
Simulation time 3508608933 ps
CPU time 9.01 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:41 PM PDT 24
Peak memory 200928 kb
Host smart-5ea5fbd7-3962-4230-ab1c-b9ee9774782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847983241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
847983241
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1751052425
Short name T300
Test name
Test status
Simulation time 52479488203 ps
CPU time 142.56 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 201016 kb
Host smart-4c5cbc3d-3b71-454f-a3a7-a7b8bdee4cd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751052425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1751052425
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.21722588
Short name T381
Test name
Test status
Simulation time 30577435818 ps
CPU time 82.71 seconds
Started Aug 01 05:25:36 PM PDT 24
Finished Aug 01 05:26:59 PM PDT 24
Peak memory 201224 kb
Host smart-365bd3c5-c8e3-42ea-b4f8-9e969f964618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21722588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_wit
h_pre_cond.21722588
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3703573604
Short name T490
Test name
Test status
Simulation time 2863484516 ps
CPU time 7.25 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:40 PM PDT 24
Peak memory 200772 kb
Host smart-92edf5ca-b4cc-4567-a1b4-3a687a2be8b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703573604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.3703573604
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.218987287
Short name T411
Test name
Test status
Simulation time 2612886503 ps
CPU time 7.35 seconds
Started Aug 01 05:25:38 PM PDT 24
Finished Aug 01 05:25:46 PM PDT 24
Peak memory 200692 kb
Host smart-e9b9c5ba-d6a2-4f1b-aa22-e7e0893c791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218987287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.218987287
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.200390517
Short name T412
Test name
Test status
Simulation time 2526033695 ps
CPU time 1.79 seconds
Started Aug 01 05:25:31 PM PDT 24
Finished Aug 01 05:25:33 PM PDT 24
Peak memory 200744 kb
Host smart-c76224b2-a60a-4fb2-8b69-be774ef5aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200390517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.200390517
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.501446782
Short name T502
Test name
Test status
Simulation time 2181750021 ps
CPU time 6.57 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200768 kb
Host smart-6f03d256-c7f3-4c9b-aa90-481af0b1e9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501446782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.501446782
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3332271102
Short name T431
Test name
Test status
Simulation time 2515478703 ps
CPU time 3.86 seconds
Started Aug 01 05:25:35 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200748 kb
Host smart-b0a71045-7b03-4ad6-bdae-3d2b397f27a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332271102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.3332271102
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.1367556256
Short name T652
Test name
Test status
Simulation time 2111721010 ps
CPU time 5.94 seconds
Started Aug 01 05:25:26 PM PDT 24
Finished Aug 01 05:25:32 PM PDT 24
Peak memory 200728 kb
Host smart-0edad0fc-6315-4f2c-877c-ff23ccac2cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367556256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1367556256
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.545970798
Short name T272
Test name
Test status
Simulation time 132735054130 ps
CPU time 329.02 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:31:04 PM PDT 24
Peak memory 200792 kb
Host smart-01ff6dac-9a3b-4f9b-b4e5-72fe4a83f78f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545970798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_st
ress_all.545970798
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3555647
Short name T144
Test name
Test status
Simulation time 1019328897045 ps
CPU time 59.61 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:26:31 PM PDT 24
Peak memory 217556 kb
Host smart-c109bcad-c894-41f4-9dd3-9a09a88d01a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555647 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3555647
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3665846799
Short name T142
Test name
Test status
Simulation time 6734818894 ps
CPU time 2.54 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:36 PM PDT 24
Peak memory 200904 kb
Host smart-10faf556-fa34-47bd-bf94-e50ff3352653
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665846799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3665846799
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2604359258
Short name T770
Test name
Test status
Simulation time 2020895537 ps
CPU time 2.84 seconds
Started Aug 01 05:25:35 PM PDT 24
Finished Aug 01 05:25:38 PM PDT 24
Peak memory 200764 kb
Host smart-57bcea3d-8d0c-4889-9234-394299fa7797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604359258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2604359258
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1920097395
Short name T646
Test name
Test status
Simulation time 3486355076 ps
CPU time 8.7 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:42 PM PDT 24
Peak memory 200856 kb
Host smart-b6241b18-95cf-4f8e-9781-17d36a5b1ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920097395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.1
920097395
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.481536470
Short name T123
Test name
Test status
Simulation time 92946246483 ps
CPU time 218.55 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:29:12 PM PDT 24
Peak memory 200992 kb
Host smart-46321eb3-33d1-4f04-9f2b-d835ffda2c2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481536470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_combo_detect.481536470
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3443395752
Short name T642
Test name
Test status
Simulation time 2795963019 ps
CPU time 4.04 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200720 kb
Host smart-36429304-bad1-407c-b6f6-12e85ba2ae2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443395752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.3443395752
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1424488490
Short name T570
Test name
Test status
Simulation time 3095976004 ps
CPU time 3.59 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:37 PM PDT 24
Peak memory 200736 kb
Host smart-4c5c2041-1bfe-41bc-88f6-7157841573f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424488490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1424488490
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.187294257
Short name T171
Test name
Test status
Simulation time 2641594259 ps
CPU time 1.51 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200736 kb
Host smart-95ca5391-481f-425d-9d54-daf58655819f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187294257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.187294257
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.2945455064
Short name T319
Test name
Test status
Simulation time 2462751607 ps
CPU time 6.92 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200780 kb
Host smart-2770a831-f45e-4733-943d-346c7399b59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945455064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2945455064
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2068082550
Short name T762
Test name
Test status
Simulation time 2214023897 ps
CPU time 3.55 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:37 PM PDT 24
Peak memory 200768 kb
Host smart-58111821-9f2c-4864-b293-04c41346ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068082550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2068082550
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2685798350
Short name T484
Test name
Test status
Simulation time 2520319886 ps
CPU time 3.27 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:36 PM PDT 24
Peak memory 200780 kb
Host smart-66a1f665-0eb1-44a7-abbf-7fc23e11adbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685798350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2685798350
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.836885916
Short name T271
Test name
Test status
Simulation time 2111977070 ps
CPU time 5.38 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200744 kb
Host smart-5c82afd3-4cc5-4179-bb8a-4e401524eac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836885916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.836885916
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.216337447
Short name T726
Test name
Test status
Simulation time 13761681694 ps
CPU time 18.35 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:51 PM PDT 24
Peak memory 200812 kb
Host smart-fec19e54-76f3-4028-8194-0af2c25e9bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216337447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_st
ress_all.216337447
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1612833486
Short name T226
Test name
Test status
Simulation time 25864865443 ps
CPU time 61.94 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:26:37 PM PDT 24
Peak memory 209256 kb
Host smart-b62b803b-ec81-4d5b-8396-1f61413c6aec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612833486 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1612833486
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3230620708
Short name T137
Test name
Test status
Simulation time 8515047145 ps
CPU time 2.9 seconds
Started Aug 01 05:25:30 PM PDT 24
Finished Aug 01 05:25:33 PM PDT 24
Peak memory 200716 kb
Host smart-f6838e1d-7073-43e1-aada-204ea39b2873
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230620708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.3230620708
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.1166040858
Short name T613
Test name
Test status
Simulation time 2010749505 ps
CPU time 5.58 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200820 kb
Host smart-946beb75-2506-4555-9c19-d31a8462c50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166040858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.1166040858
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3981621569
Short name T404
Test name
Test status
Simulation time 3303676911 ps
CPU time 9.04 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:43 PM PDT 24
Peak memory 200808 kb
Host smart-287d04a8-f2a3-4bf2-a1c0-682cb9a1518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981621569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3
981621569
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.2551338365
Short name T33
Test name
Test status
Simulation time 118721068108 ps
CPU time 73.26 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:26:47 PM PDT 24
Peak memory 201024 kb
Host smart-3db9ce1c-9607-4aac-8a1e-59ddb07c10b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551338365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.2551338365
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.767869092
Short name T116
Test name
Test status
Simulation time 25590951038 ps
CPU time 37.88 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:26:24 PM PDT 24
Peak memory 201072 kb
Host smart-64399625-c149-44ac-8358-239a3baacb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767869092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_wi
th_pre_cond.767869092
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1395928486
Short name T656
Test name
Test status
Simulation time 4669970133 ps
CPU time 6.57 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:41 PM PDT 24
Peak memory 200684 kb
Host smart-4f0dff6d-404d-40c5-ae2b-80757ec8b8e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395928486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.1395928486
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.401817421
Short name T550
Test name
Test status
Simulation time 3186621502 ps
CPU time 7.75 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:40 PM PDT 24
Peak memory 200792 kb
Host smart-3772834b-eb71-45b5-8e16-b7b77b61906a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401817421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctr
l_edge_detect.401817421
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3447594846
Short name T621
Test name
Test status
Simulation time 2622392495 ps
CPU time 4.12 seconds
Started Aug 01 05:25:30 PM PDT 24
Finished Aug 01 05:25:34 PM PDT 24
Peak memory 200808 kb
Host smart-4a59eabc-7fa9-4cf8-bf88-450c3d52ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447594846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3447594846
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2792253747
Short name T628
Test name
Test status
Simulation time 2473572123 ps
CPU time 3.85 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:36 PM PDT 24
Peak memory 200756 kb
Host smart-3f726da0-7aff-4ebe-b804-5402a56e18d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792253747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2792253747
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2281436877
Short name T671
Test name
Test status
Simulation time 2294341608 ps
CPU time 1.23 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200752 kb
Host smart-2e76ef78-5c80-4783-a061-93fc506ac79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281436877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2281436877
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.2734414407
Short name T630
Test name
Test status
Simulation time 2511977519 ps
CPU time 6.95 seconds
Started Aug 01 05:25:33 PM PDT 24
Finished Aug 01 05:25:41 PM PDT 24
Peak memory 200744 kb
Host smart-9874f6b5-b27d-4b3c-ac5d-451dab11c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734414407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2734414407
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3571182087
Short name T469
Test name
Test status
Simulation time 2120754347 ps
CPU time 3.24 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200628 kb
Host smart-f93e6c25-bf11-4ca6-ba90-2a7932373604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571182087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3571182087
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2732132441
Short name T164
Test name
Test status
Simulation time 12017894662 ps
CPU time 2.76 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200836 kb
Host smart-f9e39150-889f-44a7-b13c-dc3613291e54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732132441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2732132441
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1445774527
Short name T576
Test name
Test status
Simulation time 2014885109 ps
CPU time 4.86 seconds
Started Aug 01 05:24:02 PM PDT 24
Finished Aug 01 05:24:07 PM PDT 24
Peak memory 200808 kb
Host smart-354755c1-8c84-4464-9658-1feb2b10e96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445774527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1445774527
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3292048487
Short name T755
Test name
Test status
Simulation time 3651019993 ps
CPU time 9.62 seconds
Started Aug 01 05:24:06 PM PDT 24
Finished Aug 01 05:24:16 PM PDT 24
Peak memory 200928 kb
Host smart-d7253bf5-aa3b-4c04-81f9-3ee6da49eb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292048487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3292048487
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2278557842
Short name T754
Test name
Test status
Simulation time 77234846774 ps
CPU time 25.52 seconds
Started Aug 01 05:24:04 PM PDT 24
Finished Aug 01 05:24:29 PM PDT 24
Peak memory 201052 kb
Host smart-5ffbbe16-9e5c-40f4-ba6a-8c4f53bccc7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278557842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.2278557842
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2776510076
Short name T290
Test name
Test status
Simulation time 2435019199 ps
CPU time 6.93 seconds
Started Aug 01 05:24:11 PM PDT 24
Finished Aug 01 05:24:18 PM PDT 24
Peak memory 200704 kb
Host smart-e63fd98e-7d43-4313-abbc-0a80d1c8bc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776510076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2776510076
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.409456297
Short name T49
Test name
Test status
Simulation time 2297646380 ps
CPU time 2.64 seconds
Started Aug 01 05:24:06 PM PDT 24
Finished Aug 01 05:24:09 PM PDT 24
Peak memory 200784 kb
Host smart-359904ec-c259-4f3e-b199-fa74de8e6639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409456297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.409456297
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1903840947
Short name T731
Test name
Test status
Simulation time 2657942497 ps
CPU time 2.21 seconds
Started Aug 01 05:24:05 PM PDT 24
Finished Aug 01 05:24:07 PM PDT 24
Peak memory 200720 kb
Host smart-48e9e965-949c-4c69-a3e2-ded7fc08a996
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903840947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.1903840947
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2899776466
Short name T590
Test name
Test status
Simulation time 3504117622 ps
CPU time 3.48 seconds
Started Aug 01 05:24:05 PM PDT 24
Finished Aug 01 05:24:09 PM PDT 24
Peak memory 200832 kb
Host smart-d984c6da-e448-44e1-acab-37c28da3a37e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899776466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.2899776466
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1419753120
Short name T785
Test name
Test status
Simulation time 2625887311 ps
CPU time 2.3 seconds
Started Aug 01 05:24:02 PM PDT 24
Finished Aug 01 05:24:05 PM PDT 24
Peak memory 200736 kb
Host smart-d29bd9c6-f6f2-4e1d-b0e0-7696c5bf877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419753120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.1419753120
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.2662123193
Short name T644
Test name
Test status
Simulation time 2534498110 ps
CPU time 1.22 seconds
Started Aug 01 05:24:13 PM PDT 24
Finished Aug 01 05:24:14 PM PDT 24
Peak memory 200724 kb
Host smart-52bba8bb-4576-4665-b610-5176dae99bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662123193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.2662123193
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3045497078
Short name T221
Test name
Test status
Simulation time 2035636497 ps
CPU time 5.84 seconds
Started Aug 01 05:24:04 PM PDT 24
Finished Aug 01 05:24:10 PM PDT 24
Peak memory 200740 kb
Host smart-50a50d2b-1162-40f8-aa69-a16a7d22d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045497078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3045497078
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1350594531
Short name T523
Test name
Test status
Simulation time 2510168580 ps
CPU time 6.82 seconds
Started Aug 01 05:24:06 PM PDT 24
Finished Aug 01 05:24:13 PM PDT 24
Peak memory 200860 kb
Host smart-80a42af1-8ff6-4282-81e0-bee6699292c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350594531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1350594531
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.1738900083
Short name T80
Test name
Test status
Simulation time 42090558609 ps
CPU time 28.75 seconds
Started Aug 01 05:24:04 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 220336 kb
Host smart-0535a4c8-bb50-4143-bf10-581362be6970
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738900083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1738900083
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.1138339227
Short name T437
Test name
Test status
Simulation time 2110234517 ps
CPU time 5.96 seconds
Started Aug 01 05:24:13 PM PDT 24
Finished Aug 01 05:24:19 PM PDT 24
Peak memory 200660 kb
Host smart-d05bb13d-7107-4f9b-b53c-3f9ea0ebb890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138339227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.1138339227
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.2132158011
Short name T145
Test name
Test status
Simulation time 15776457500 ps
CPU time 32.33 seconds
Started Aug 01 05:24:02 PM PDT 24
Finished Aug 01 05:24:34 PM PDT 24
Peak memory 200856 kb
Host smart-d57532a8-d9d9-406c-935e-5f5e8030a6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132158011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.2132158011
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2984084408
Short name T312
Test name
Test status
Simulation time 41955617652 ps
CPU time 89.06 seconds
Started Aug 01 05:24:08 PM PDT 24
Finished Aug 01 05:25:37 PM PDT 24
Peak memory 217440 kb
Host smart-7729af14-81fc-46a4-91fa-a6e9ec6269ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984084408 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2984084408
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1470872864
Short name T600
Test name
Test status
Simulation time 2934885694 ps
CPU time 2.26 seconds
Started Aug 01 05:24:02 PM PDT 24
Finished Aug 01 05:24:04 PM PDT 24
Peak memory 200868 kb
Host smart-3b14806b-a556-4cfb-8cc6-6293c707ace7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470872864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.1470872864
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.35294468
Short name T765
Test name
Test status
Simulation time 2012798858 ps
CPU time 3.18 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:37 PM PDT 24
Peak memory 200856 kb
Host smart-f7db359b-b2c6-4333-b789-7dfc7a9bd443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35294468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test
.35294468
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2537386592
Short name T328
Test name
Test status
Simulation time 3850553478 ps
CPU time 5.76 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:41 PM PDT 24
Peak memory 200820 kb
Host smart-2493dda2-9ad7-4d38-8ec9-b4be18eb6c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537386592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
537386592
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.891480779
Short name T302
Test name
Test status
Simulation time 80667296598 ps
CPU time 207.74 seconds
Started Aug 01 05:25:37 PM PDT 24
Finished Aug 01 05:29:05 PM PDT 24
Peak memory 201020 kb
Host smart-b03b3f90-2f68-46ec-951a-42023ed53846
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891480779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_combo_detect.891480779
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2907476934
Short name T744
Test name
Test status
Simulation time 4708157054 ps
CPU time 12.86 seconds
Started Aug 01 05:25:37 PM PDT 24
Finished Aug 01 05:25:50 PM PDT 24
Peak memory 200768 kb
Host smart-918652a0-c38d-4311-95fb-7334ba4d0f44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907476934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.2907476934
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2996376091
Short name T242
Test name
Test status
Simulation time 3626706677 ps
CPU time 3.03 seconds
Started Aug 01 05:25:36 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200712 kb
Host smart-844a2406-62e5-46ad-98f3-ad699be534dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996376091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.2996376091
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1216430171
Short name T259
Test name
Test status
Simulation time 2637517059 ps
CPU time 2.39 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200792 kb
Host smart-255cea22-48cf-4335-b3b7-4f3a0254f561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216430171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1216430171
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1555427880
Short name T782
Test name
Test status
Simulation time 2457405922 ps
CPU time 6.58 seconds
Started Aug 01 05:25:36 PM PDT 24
Finished Aug 01 05:25:43 PM PDT 24
Peak memory 200864 kb
Host smart-6dead01b-c6e0-4c63-9fe4-ce8ab571b90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555427880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1555427880
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3217964884
Short name T627
Test name
Test status
Simulation time 2275459356 ps
CPU time 1.47 seconds
Started Aug 01 05:25:36 PM PDT 24
Finished Aug 01 05:25:37 PM PDT 24
Peak memory 200792 kb
Host smart-334b4f02-2e1a-4f0d-bf66-4b6f94e2b350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217964884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3217964884
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1064216096
Short name T70
Test name
Test status
Simulation time 2529396563 ps
CPU time 1.85 seconds
Started Aug 01 05:25:37 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200788 kb
Host smart-acb36ef4-32f6-4d48-a9d6-caff9ceca08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064216096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1064216096
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.2541289943
Short name T706
Test name
Test status
Simulation time 2133375613 ps
CPU time 2.01 seconds
Started Aug 01 05:25:32 PM PDT 24
Finished Aug 01 05:25:34 PM PDT 24
Peak memory 200620 kb
Host smart-1462d491-537e-4181-bbde-987f6c9121be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541289943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.2541289943
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3950844894
Short name T189
Test name
Test status
Simulation time 40105987890 ps
CPU time 25.67 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:26:00 PM PDT 24
Peak memory 210828 kb
Host smart-b6d3e6da-ba84-4dc7-8a5e-61a47701570e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950844894 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.3950844894
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2756173197
Short name T168
Test name
Test status
Simulation time 4595620974 ps
CPU time 3.48 seconds
Started Aug 01 05:25:36 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200840 kb
Host smart-f18d2d53-1136-4d16-9147-90713d615c64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756173197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.2756173197
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.3397621716
Short name T666
Test name
Test status
Simulation time 2037641298 ps
CPU time 1.91 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:48 PM PDT 24
Peak memory 200804 kb
Host smart-68695338-8cd4-481d-adfa-cdc070410710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397621716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.3397621716
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1086297239
Short name T558
Test name
Test status
Simulation time 3610869762 ps
CPU time 9.53 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:56 PM PDT 24
Peak memory 200876 kb
Host smart-874f9f26-3191-43fd-a4e5-0815ef8e972d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086297239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.1
086297239
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3369208352
Short name T375
Test name
Test status
Simulation time 77367329140 ps
CPU time 193.53 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:28:59 PM PDT 24
Peak memory 200988 kb
Host smart-9ba84857-3bb9-4a47-b49b-9347ff618456
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369208352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3369208352
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2349494967
Short name T275
Test name
Test status
Simulation time 34809753220 ps
CPU time 23.84 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:26:09 PM PDT 24
Peak memory 201068 kb
Host smart-fb7ce130-6a83-44ba-90a2-f5ec2603b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349494967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2349494967
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2641276125
Short name T527
Test name
Test status
Simulation time 3026669513 ps
CPU time 2.53 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:49 PM PDT 24
Peak memory 200756 kb
Host smart-2f7cf369-dfd5-440c-9dd6-96e201120a7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641276125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.2641276125
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.1894867959
Short name T228
Test name
Test status
Simulation time 5308056166 ps
CPU time 11.72 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:58 PM PDT 24
Peak memory 200816 kb
Host smart-da20525c-9f21-4e70-9013-a9f49fd30e7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894867959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.1894867959
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.827240827
Short name T263
Test name
Test status
Simulation time 2606952243 ps
CPU time 7.24 seconds
Started Aug 01 05:25:37 PM PDT 24
Finished Aug 01 05:25:44 PM PDT 24
Peak memory 200724 kb
Host smart-3f2926c1-f453-40b1-a817-088ec04e359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827240827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.827240827
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1914251879
Short name T459
Test name
Test status
Simulation time 2524258828 ps
CPU time 1.14 seconds
Started Aug 01 05:25:34 PM PDT 24
Finished Aug 01 05:25:35 PM PDT 24
Peak memory 200744 kb
Host smart-26db1beb-0c96-4d48-b0a0-32e537b0d88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914251879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1914251879
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2527301297
Short name T611
Test name
Test status
Simulation time 2065208031 ps
CPU time 1.99 seconds
Started Aug 01 05:25:36 PM PDT 24
Finished Aug 01 05:25:38 PM PDT 24
Peak memory 200672 kb
Host smart-a33197e7-f8e2-466b-83a4-65b2f1c71182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527301297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2527301297
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.579104643
Short name T645
Test name
Test status
Simulation time 2515721217 ps
CPU time 4.77 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:51 PM PDT 24
Peak memory 200760 kb
Host smart-56777d07-4637-48a1-b1d7-eafabd00e0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579104643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.579104643
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.739644386
Short name T643
Test name
Test status
Simulation time 2189185412 ps
CPU time 1.07 seconds
Started Aug 01 05:25:38 PM PDT 24
Finished Aug 01 05:25:39 PM PDT 24
Peak memory 200784 kb
Host smart-bdfda351-837f-4b78-9d40-d6d7aee5d9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739644386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.739644386
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.74782826
Short name T315
Test name
Test status
Simulation time 13895092944 ps
CPU time 35.48 seconds
Started Aug 01 05:25:44 PM PDT 24
Finished Aug 01 05:26:20 PM PDT 24
Peak memory 200744 kb
Host smart-c308bf4a-08de-4aae-b34f-7f18e714f779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74782826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_str
ess_all.74782826
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.4105636170
Short name T107
Test name
Test status
Simulation time 275447373277 ps
CPU time 168.74 seconds
Started Aug 01 05:25:35 PM PDT 24
Finished Aug 01 05:28:24 PM PDT 24
Peak memory 209476 kb
Host smart-4f38b4f7-0ddc-464f-9467-bf7c1b030466
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105636170 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.4105636170
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1061694562
Short name T57
Test name
Test status
Simulation time 9106607451 ps
CPU time 6.43 seconds
Started Aug 01 05:25:37 PM PDT 24
Finished Aug 01 05:25:43 PM PDT 24
Peak memory 200804 kb
Host smart-8e79784a-65c0-4021-aa29-2f99dd2fd178
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061694562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.1061694562
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.3071517502
Short name T518
Test name
Test status
Simulation time 2050482585 ps
CPU time 1.46 seconds
Started Aug 01 05:25:42 PM PDT 24
Finished Aug 01 05:25:44 PM PDT 24
Peak memory 200772 kb
Host smart-65a22ef6-7964-4624-b403-d2ed4ed1df40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071517502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.3071517502
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3217905022
Short name T401
Test name
Test status
Simulation time 3666474996 ps
CPU time 2.81 seconds
Started Aug 01 05:25:48 PM PDT 24
Finished Aug 01 05:25:51 PM PDT 24
Peak memory 200840 kb
Host smart-90703cf3-c3ab-4230-a0d4-7ac3bff3a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217905022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3
217905022
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.2556101901
Short name T299
Test name
Test status
Simulation time 40180472191 ps
CPU time 105.44 seconds
Started Aug 01 05:25:43 PM PDT 24
Finished Aug 01 05:27:29 PM PDT 24
Peak memory 201008 kb
Host smart-d12e7773-9777-4253-a8aa-82d059b8ad4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556101901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.2556101901
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.367739601
Short name T658
Test name
Test status
Simulation time 47351810882 ps
CPU time 112.71 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:27:38 PM PDT 24
Peak memory 201128 kb
Host smart-671b88be-c2e9-4f5d-9246-7d67e004c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367739601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi
th_pre_cond.367739601
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2322175040
Short name T738
Test name
Test status
Simulation time 3395219687 ps
CPU time 9.57 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:25:55 PM PDT 24
Peak memory 200720 kb
Host smart-158b634d-6262-4cfd-9619-701d744372e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322175040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2322175040
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.2729629233
Short name T39
Test name
Test status
Simulation time 2770349727 ps
CPU time 3.59 seconds
Started Aug 01 05:25:40 PM PDT 24
Finished Aug 01 05:25:44 PM PDT 24
Peak memory 200824 kb
Host smart-3ee8db02-b8d0-4b76-b474-8c7d77a43e1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729629233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.2729629233
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3172290264
Short name T684
Test name
Test status
Simulation time 2627236619 ps
CPU time 2.27 seconds
Started Aug 01 05:25:51 PM PDT 24
Finished Aug 01 05:25:54 PM PDT 24
Peak memory 200728 kb
Host smart-9cb265c4-cc1b-4f38-bb7a-d2f651ed3c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172290264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3172290264
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.980208935
Short name T148
Test name
Test status
Simulation time 2479757482 ps
CPU time 2.49 seconds
Started Aug 01 05:25:42 PM PDT 24
Finished Aug 01 05:25:45 PM PDT 24
Peak memory 200772 kb
Host smart-2d9288bf-b630-49c3-9f31-5ddfd769db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980208935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.980208935
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1273101925
Short name T461
Test name
Test status
Simulation time 2130575806 ps
CPU time 2.05 seconds
Started Aug 01 05:25:43 PM PDT 24
Finished Aug 01 05:25:45 PM PDT 24
Peak memory 200708 kb
Host smart-248533e8-c03f-4148-a678-e40ba3f43737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273101925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1273101925
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3443599276
Short name T637
Test name
Test status
Simulation time 2513026429 ps
CPU time 7.68 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:25:53 PM PDT 24
Peak memory 200744 kb
Host smart-a7560dac-878b-44e4-a0ee-e8bc37f76e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443599276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3443599276
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2264652151
Short name T59
Test name
Test status
Simulation time 2118574707 ps
CPU time 3.23 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:50 PM PDT 24
Peak memory 200740 kb
Host smart-39276c17-c47f-4e20-96fb-1c632550fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264652151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2264652151
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.937413438
Short name T40
Test name
Test status
Simulation time 18916123439 ps
CPU time 12.39 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:58 PM PDT 24
Peak memory 201100 kb
Host smart-25bc501e-c1ec-43ae-99a2-fff9b690ab50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937413438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.937413438
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1796552019
Short name T82
Test name
Test status
Simulation time 23594876136 ps
CPU time 63.15 seconds
Started Aug 01 05:25:56 PM PDT 24
Finished Aug 01 05:26:59 PM PDT 24
Peak memory 209260 kb
Host smart-429b499d-9f3f-493a-b960-6d9ebc053a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796552019 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1796552019
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1580143575
Short name T389
Test name
Test status
Simulation time 528906767010 ps
CPU time 20.51 seconds
Started Aug 01 05:25:41 PM PDT 24
Finished Aug 01 05:26:02 PM PDT 24
Peak memory 200868 kb
Host smart-33496061-9906-4cd6-8b79-6ad12493cd61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580143575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.1580143575
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.2853828002
Short name T712
Test name
Test status
Simulation time 2013693850 ps
CPU time 5.29 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:52 PM PDT 24
Peak memory 200804 kb
Host smart-19e67349-99b9-43cb-97de-65de8d7786be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853828002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.2853828002
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1036463491
Short name T689
Test name
Test status
Simulation time 3428151369 ps
CPU time 2.53 seconds
Started Aug 01 05:25:42 PM PDT 24
Finished Aug 01 05:25:45 PM PDT 24
Peak memory 200844 kb
Host smart-59e20313-18c6-49d2-818c-96e62228c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036463491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1
036463491
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3517225401
Short name T286
Test name
Test status
Simulation time 90149586020 ps
CPU time 81.79 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 200968 kb
Host smart-31eb6a0b-5f56-4b74-b93c-45c2a765a350
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517225401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.3517225401
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1755046562
Short name T241
Test name
Test status
Simulation time 43862959017 ps
CPU time 105.98 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:27:32 PM PDT 24
Peak memory 201024 kb
Host smart-373cbe99-ccb6-4271-9b4a-29eb48de7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755046562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.1755046562
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2358449965
Short name T395
Test name
Test status
Simulation time 5416430468 ps
CPU time 7.32 seconds
Started Aug 01 05:25:42 PM PDT 24
Finished Aug 01 05:25:49 PM PDT 24
Peak memory 200784 kb
Host smart-3f3e6eea-64ee-4d09-a992-f79818c6cda9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358449965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.2358449965
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.751110879
Short name T185
Test name
Test status
Simulation time 2738521197 ps
CPU time 4.03 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:50 PM PDT 24
Peak memory 200820 kb
Host smart-595dc354-473a-40dd-8d05-a828ed611b33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751110879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctr
l_edge_detect.751110879
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2103881011
Short name T496
Test name
Test status
Simulation time 2616902339 ps
CPU time 4.05 seconds
Started Aug 01 05:25:42 PM PDT 24
Finished Aug 01 05:25:47 PM PDT 24
Peak memory 200788 kb
Host smart-39d00fca-36af-4459-b8fb-f45ed84cae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103881011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.2103881011
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1260183193
Short name T756
Test name
Test status
Simulation time 2482039898 ps
CPU time 3.77 seconds
Started Aug 01 05:25:48 PM PDT 24
Finished Aug 01 05:25:52 PM PDT 24
Peak memory 200756 kb
Host smart-0a888b38-f60a-43a0-b412-4b5cb168d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260183193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1260183193
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.877367730
Short name T479
Test name
Test status
Simulation time 2228673227 ps
CPU time 6.13 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200712 kb
Host smart-e056ac3c-fee4-4e95-9040-48f8bbfaf375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877367730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.877367730
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3064775781
Short name T396
Test name
Test status
Simulation time 2527312413 ps
CPU time 2.26 seconds
Started Aug 01 05:25:43 PM PDT 24
Finished Aug 01 05:25:45 PM PDT 24
Peak memory 200808 kb
Host smart-ec8526f4-aed1-44c5-bb52-68426be9c8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064775781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3064775781
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.49447052
Short name T191
Test name
Test status
Simulation time 2130326842 ps
CPU time 1.8 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:25:59 PM PDT 24
Peak memory 200640 kb
Host smart-b8092255-6f45-4c05-b481-c7a3ab53c70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49447052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.49447052
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2716081861
Short name T721
Test name
Test status
Simulation time 10801516085 ps
CPU time 26.19 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:26:23 PM PDT 24
Peak memory 200748 kb
Host smart-39169152-ae61-45ca-afcb-8dec29ae8355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716081861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2716081861
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2501729850
Short name T74
Test name
Test status
Simulation time 5691688935 ps
CPU time 2.47 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:26:00 PM PDT 24
Peak memory 200752 kb
Host smart-cb486553-aebb-4f0b-ac94-b814bef20684
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501729850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.2501729850
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.913836611
Short name T291
Test name
Test status
Simulation time 2038019027 ps
CPU time 1.74 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:25:47 PM PDT 24
Peak memory 200800 kb
Host smart-f2920fe5-fcc2-43b5-bcaf-c7d84822a7ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913836611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.913836611
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.441333755
Short name T403
Test name
Test status
Simulation time 3328462645 ps
CPU time 8.47 seconds
Started Aug 01 05:25:43 PM PDT 24
Finished Aug 01 05:25:52 PM PDT 24
Peak memory 200956 kb
Host smart-99a0187a-a685-4687-8055-08f08fc6e46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441333755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.441333755
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1642366765
Short name T354
Test name
Test status
Simulation time 66499043086 ps
CPU time 157.83 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:28:35 PM PDT 24
Peak memory 200932 kb
Host smart-32e1054d-9888-4e79-afe9-0175678b942e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642366765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.1642366765
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1399188296
Short name T155
Test name
Test status
Simulation time 2688501375 ps
CPU time 1.23 seconds
Started Aug 01 05:25:47 PM PDT 24
Finished Aug 01 05:25:48 PM PDT 24
Peak memory 200776 kb
Host smart-906b660f-7e31-4183-812a-eece4da68d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399188296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1399188296
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.831944995
Short name T329
Test name
Test status
Simulation time 2459909078 ps
CPU time 6.7 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:25:52 PM PDT 24
Peak memory 200796 kb
Host smart-71e5c68e-74fc-4dec-893e-595651dee356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831944995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.831944995
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.202288785
Short name T415
Test name
Test status
Simulation time 2066890486 ps
CPU time 1.7 seconds
Started Aug 01 05:25:43 PM PDT 24
Finished Aug 01 05:25:45 PM PDT 24
Peak memory 200708 kb
Host smart-2fa3d634-684e-42f0-a7c6-e1cc739c55ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202288785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.202288785
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.815269591
Short name T505
Test name
Test status
Simulation time 2515435245 ps
CPU time 3.87 seconds
Started Aug 01 05:25:47 PM PDT 24
Finished Aug 01 05:25:51 PM PDT 24
Peak memory 200760 kb
Host smart-d7b42110-00df-476d-8c88-16a928689fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815269591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.815269591
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.3032712935
Short name T246
Test name
Test status
Simulation time 2133261075 ps
CPU time 1.64 seconds
Started Aug 01 05:25:48 PM PDT 24
Finished Aug 01 05:25:50 PM PDT 24
Peak memory 200716 kb
Host smart-66f01f38-f96e-469a-b5f3-c85b00d9a1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032712935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3032712935
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.3996847263
Short name T626
Test name
Test status
Simulation time 9869170200 ps
CPU time 24.74 seconds
Started Aug 01 05:25:45 PM PDT 24
Finished Aug 01 05:26:10 PM PDT 24
Peak memory 200744 kb
Host smart-345e82a2-7a02-43b0-b0ef-277ddf5d2102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996847263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.3996847263
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3756156275
Short name T330
Test name
Test status
Simulation time 2021860495 ps
CPU time 3.05 seconds
Started Aug 01 05:25:53 PM PDT 24
Finished Aug 01 05:25:57 PM PDT 24
Peak memory 200764 kb
Host smart-1a25aa73-4905-499b-9b84-70984377d855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756156275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3756156275
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.861297513
Short name T252
Test name
Test status
Simulation time 3432327584 ps
CPU time 9.87 seconds
Started Aug 01 05:25:54 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200888 kb
Host smart-86c1e370-7e86-4d62-b040-56e5b089d0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861297513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.861297513
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2780202592
Short name T566
Test name
Test status
Simulation time 152714926255 ps
CPU time 410.47 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:32:49 PM PDT 24
Peak memory 201020 kb
Host smart-d2df2736-de1f-4b69-a4fc-e9aa13ec8c8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780202592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.2780202592
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2212591176
Short name T771
Test name
Test status
Simulation time 32264669045 ps
CPU time 23.51 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:26:19 PM PDT 24
Peak memory 201088 kb
Host smart-26f0c504-15d2-489e-a4e4-55784eabcb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212591176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.2212591176
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3190878634
Short name T477
Test name
Test status
Simulation time 2943141185 ps
CPU time 2.4 seconds
Started Aug 01 05:25:53 PM PDT 24
Finished Aug 01 05:25:56 PM PDT 24
Peak memory 200752 kb
Host smart-7f721e90-277a-4fad-9d13-30536882ad23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190878634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.3190878634
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2406529203
Short name T448
Test name
Test status
Simulation time 2634272738 ps
CPU time 1.85 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:25:57 PM PDT 24
Peak memory 200808 kb
Host smart-bed75566-3474-4b08-b858-c8fbf18e5662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406529203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2406529203
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.3065684336
Short name T638
Test name
Test status
Simulation time 2459168204 ps
CPU time 3.62 seconds
Started Aug 01 05:25:46 PM PDT 24
Finished Aug 01 05:25:50 PM PDT 24
Peak memory 200784 kb
Host smart-26d6bd8d-eeec-4d22-9fd3-4e74c28be3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065684336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.3065684336
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3750440721
Short name T128
Test name
Test status
Simulation time 2173202564 ps
CPU time 5.4 seconds
Started Aug 01 05:25:56 PM PDT 24
Finished Aug 01 05:26:02 PM PDT 24
Peak memory 200796 kb
Host smart-3df55d1b-ec53-4aaf-8fa9-846b385835de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750440721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.3750440721
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2156099742
Short name T510
Test name
Test status
Simulation time 2519445120 ps
CPU time 4.02 seconds
Started Aug 01 05:25:53 PM PDT 24
Finished Aug 01 05:25:58 PM PDT 24
Peak memory 200728 kb
Host smart-bc168c27-b29e-43ff-8eaa-6b0d688362db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156099742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2156099742
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.2856483471
Short name T202
Test name
Test status
Simulation time 2114557594 ps
CPU time 4.66 seconds
Started Aug 01 05:25:48 PM PDT 24
Finished Aug 01 05:25:53 PM PDT 24
Peak memory 200668 kb
Host smart-75e3d528-a33d-455e-91ec-71dcc94289fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856483471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2856483471
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.552241097
Short name T184
Test name
Test status
Simulation time 15611827384 ps
CPU time 37.02 seconds
Started Aug 01 05:25:54 PM PDT 24
Finished Aug 01 05:26:31 PM PDT 24
Peak memory 201052 kb
Host smart-93570892-4773-4b5e-b61a-1d29d8c7bcdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552241097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_st
ress_all.552241097
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3213806273
Short name T223
Test name
Test status
Simulation time 34903734527 ps
CPU time 57.21 seconds
Started Aug 01 05:25:53 PM PDT 24
Finished Aug 01 05:26:50 PM PDT 24
Peak memory 217492 kb
Host smart-d5b61575-daf4-4cfb-b835-672a43d7d1ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213806273 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3213806273
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3673241942
Short name T10
Test name
Test status
Simulation time 7199706428 ps
CPU time 7.72 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:26:05 PM PDT 24
Peak memory 200784 kb
Host smart-eaf01350-5774-4a2d-965d-1f9d9201bfb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673241942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3673241942
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.2170251075
Short name T719
Test name
Test status
Simulation time 2030214763 ps
CPU time 1.91 seconds
Started Aug 01 05:25:54 PM PDT 24
Finished Aug 01 05:25:56 PM PDT 24
Peak memory 200800 kb
Host smart-339103e7-34e5-44b3-85f9-f183a81f2b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170251075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.2170251075
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2588103648
Short name T219
Test name
Test status
Simulation time 3248551283 ps
CPU time 8.87 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:26:06 PM PDT 24
Peak memory 200784 kb
Host smart-0516e7d3-d6c0-4226-a019-a1fd5c6c6d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588103648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.2
588103648
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.93980872
Short name T265
Test name
Test status
Simulation time 105215976318 ps
CPU time 69.65 seconds
Started Aug 01 05:25:54 PM PDT 24
Finished Aug 01 05:27:03 PM PDT 24
Peak memory 201024 kb
Host smart-ddfd8927-d15a-459d-bfbe-e2fc6022774c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93980872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctr
l_combo_detect.93980872
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1246820540
Short name T331
Test name
Test status
Simulation time 46308982307 ps
CPU time 58.87 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:26:54 PM PDT 24
Peak memory 201184 kb
Host smart-0d542715-6d1b-4aa1-835f-926533c1a384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246820540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.1246820540
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.786637803
Short name T641
Test name
Test status
Simulation time 3600046163 ps
CPU time 2.96 seconds
Started Aug 01 05:25:56 PM PDT 24
Finished Aug 01 05:25:59 PM PDT 24
Peak memory 200788 kb
Host smart-821e5822-811b-4e75-b22a-8039eab0ffdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786637803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ec_pwr_on_rst.786637803
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2120253543
Short name T660
Test name
Test status
Simulation time 2441437329 ps
CPU time 6.54 seconds
Started Aug 01 05:26:02 PM PDT 24
Finished Aug 01 05:26:08 PM PDT 24
Peak memory 200840 kb
Host smart-a8509bff-d582-4568-b568-c96bfc9aaed6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120253543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2120253543
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1195632967
Short name T180
Test name
Test status
Simulation time 2609581000 ps
CPU time 7.52 seconds
Started Aug 01 05:25:53 PM PDT 24
Finished Aug 01 05:26:01 PM PDT 24
Peak memory 200676 kb
Host smart-d81fa95e-306c-4e2a-b67d-f41f35ae98ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195632967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1195632967
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2325290953
Short name T466
Test name
Test status
Simulation time 2466906026 ps
CPU time 4.07 seconds
Started Aug 01 05:26:02 PM PDT 24
Finished Aug 01 05:26:06 PM PDT 24
Peak memory 200788 kb
Host smart-0c16cf13-929a-441c-b63d-318f5ac40d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325290953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2325290953
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1883386472
Short name T294
Test name
Test status
Simulation time 2275022273 ps
CPU time 1.92 seconds
Started Aug 01 05:25:54 PM PDT 24
Finished Aug 01 05:25:56 PM PDT 24
Peak memory 200712 kb
Host smart-7bf80c86-b814-4e46-b53d-c2307ccbb467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883386472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1883386472
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.1850892361
Short name T521
Test name
Test status
Simulation time 2509137449 ps
CPU time 6.01 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200720 kb
Host smart-16beb2da-7aa7-4dea-85d5-5410ddd7e8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850892361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.1850892361
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1359916028
Short name T533
Test name
Test status
Simulation time 2114810128 ps
CPU time 3.1 seconds
Started Aug 01 05:25:53 PM PDT 24
Finished Aug 01 05:25:56 PM PDT 24
Peak memory 200632 kb
Host smart-09840660-5197-48a8-af6c-e792dce41ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359916028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1359916028
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.3882249072
Short name T314
Test name
Test status
Simulation time 13503663053 ps
CPU time 35.61 seconds
Started Aug 01 05:25:54 PM PDT 24
Finished Aug 01 05:26:29 PM PDT 24
Peak memory 200780 kb
Host smart-1e1215bc-5e02-4ff9-9e09-738581255bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882249072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.3882249072
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.163013930
Short name T143
Test name
Test status
Simulation time 3691666888 ps
CPU time 6.39 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:05 PM PDT 24
Peak memory 200860 kb
Host smart-ff2e3db9-2beb-4663-9cd8-0ed5dc698dc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163013930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ultra_low_pwr.163013930
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.324779431
Short name T14
Test name
Test status
Simulation time 2016665000 ps
CPU time 5.38 seconds
Started Aug 01 05:26:01 PM PDT 24
Finished Aug 01 05:26:06 PM PDT 24
Peak memory 200808 kb
Host smart-4e1e0aaa-4307-4bda-b2a8-85fd03ea64a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324779431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_tes
t.324779431
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2935133512
Short name T729
Test name
Test status
Simulation time 3975675357 ps
CPU time 10.53 seconds
Started Aug 01 05:25:56 PM PDT 24
Finished Aug 01 05:26:06 PM PDT 24
Peak memory 200872 kb
Host smart-7c7aaa3d-8567-4cf3-b7dd-a29b397eb948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935133512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
935133512
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.970114753
Short name T747
Test name
Test status
Simulation time 53545799257 ps
CPU time 147.37 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:28:22 PM PDT 24
Peak memory 201136 kb
Host smart-7b6218f1-b9b3-405f-a159-27f1dac27afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970114753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.970114753
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2782893433
Short name T662
Test name
Test status
Simulation time 3987495661 ps
CPU time 3.29 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:01 PM PDT 24
Peak memory 200788 kb
Host smart-8b87eaad-7bda-4217-85c5-a57a46ffe2b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782893433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2782893433
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1774022610
Short name T665
Test name
Test status
Simulation time 4451299443 ps
CPU time 8.52 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:26:03 PM PDT 24
Peak memory 200856 kb
Host smart-be239630-7d84-4136-8ab2-8d91873dab86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774022610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.1774022610
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3196378245
Short name T647
Test name
Test status
Simulation time 2611195803 ps
CPU time 6.88 seconds
Started Aug 01 05:25:56 PM PDT 24
Finished Aug 01 05:26:03 PM PDT 24
Peak memory 200804 kb
Host smart-d45082e6-c27b-4eb3-bb67-f33856d3da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196378245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3196378245
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.3108230602
Short name T132
Test name
Test status
Simulation time 2454186621 ps
CPU time 3.96 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:26:01 PM PDT 24
Peak memory 200808 kb
Host smart-48467220-f495-47a2-a0d0-b7bbd48f896a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108230602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.3108230602
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2478627439
Short name T583
Test name
Test status
Simulation time 2130694733 ps
CPU time 1.7 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:00 PM PDT 24
Peak memory 200672 kb
Host smart-7e6ecbf8-9009-408d-b710-bc80ba8a8db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478627439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.2478627439
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.1874394856
Short name T675
Test name
Test status
Simulation time 2520118876 ps
CPU time 3.79 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:25:59 PM PDT 24
Peak memory 200748 kb
Host smart-bca9679a-f19e-4499-ab40-b94c71a0e9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874394856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.1874394856
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1177619774
Short name T574
Test name
Test status
Simulation time 2107138580 ps
CPU time 5.85 seconds
Started Aug 01 05:25:55 PM PDT 24
Finished Aug 01 05:26:01 PM PDT 24
Peak memory 200732 kb
Host smart-aaff68b6-71b7-4565-8ecd-7804b30abbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177619774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1177619774
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.3873402996
Short name T672
Test name
Test status
Simulation time 11952995125 ps
CPU time 6.16 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200748 kb
Host smart-91d0c36a-6e41-463a-b079-6fbc26ad3176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873402996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.3873402996
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.921506774
Short name T105
Test name
Test status
Simulation time 40690624101 ps
CPU time 55.56 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:53 PM PDT 24
Peak memory 209344 kb
Host smart-b384028c-71a0-473b-a5d3-4a167f93df23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921506774 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.921506774
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.313131153
Short name T90
Test name
Test status
Simulation time 2080432841 ps
CPU time 1.12 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:08 PM PDT 24
Peak memory 200736 kb
Host smart-7a09f84e-3f6a-4a5a-8e38-17c63a620bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313131153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_tes
t.313131153
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3015009164
Short name T551
Test name
Test status
Simulation time 3263922406 ps
CPU time 2.07 seconds
Started Aug 01 05:26:11 PM PDT 24
Finished Aug 01 05:26:13 PM PDT 24
Peak memory 200812 kb
Host smart-6ea45658-14a0-4a5a-b00d-69bff9ffdf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015009164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3
015009164
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2360280105
Short name T100
Test name
Test status
Simulation time 59703960318 ps
CPU time 40.58 seconds
Started Aug 01 05:26:05 PM PDT 24
Finished Aug 01 05:26:47 PM PDT 24
Peak memory 201000 kb
Host smart-7d2d8b4d-b65e-4f6c-a431-3818c077e0ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360280105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2360280105
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3742042822
Short name T592
Test name
Test status
Simulation time 28081851084 ps
CPU time 74.16 seconds
Started Aug 01 05:26:10 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 201084 kb
Host smart-80a8b662-292c-4e82-bdfb-7ecef91e8f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742042822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3742042822
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3909733887
Short name T649
Test name
Test status
Simulation time 2880707227 ps
CPU time 7.52 seconds
Started Aug 01 05:26:10 PM PDT 24
Finished Aug 01 05:26:18 PM PDT 24
Peak memory 200764 kb
Host smart-74ec02a5-8447-4708-bf30-020064422bd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909733887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.3909733887
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.1466694121
Short name T229
Test name
Test status
Simulation time 802844943548 ps
CPU time 1001.73 seconds
Started Aug 01 05:26:05 PM PDT 24
Finished Aug 01 05:42:47 PM PDT 24
Peak memory 200844 kb
Host smart-fe22bcb1-6ec0-4783-9d8c-3426702ff5f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466694121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.1466694121
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.762298722
Short name T584
Test name
Test status
Simulation time 2616611571 ps
CPU time 3.98 seconds
Started Aug 01 05:26:01 PM PDT 24
Finished Aug 01 05:26:05 PM PDT 24
Peak memory 200788 kb
Host smart-83bd99c1-fa2e-45f2-b8c4-146ee4041a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762298722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.762298722
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1163271306
Short name T220
Test name
Test status
Simulation time 2458589899 ps
CPU time 6.8 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200792 kb
Host smart-9425fee6-e178-4cf1-920e-19c05e6e860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163271306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1163271306
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.850394722
Short name T763
Test name
Test status
Simulation time 2194393562 ps
CPU time 5.62 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200716 kb
Host smart-4b3c5340-bdd2-4b44-bc65-5a438eafbe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850394722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.850394722
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1975203436
Short name T781
Test name
Test status
Simulation time 2571859562 ps
CPU time 1.49 seconds
Started Aug 01 05:25:57 PM PDT 24
Finished Aug 01 05:25:59 PM PDT 24
Peak memory 200808 kb
Host smart-c3d8b6da-1d65-4c4b-9f9f-2637603b38b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975203436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1975203436
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.916878398
Short name T559
Test name
Test status
Simulation time 2110851046 ps
CPU time 5.8 seconds
Started Aug 01 05:25:58 PM PDT 24
Finished Aug 01 05:26:04 PM PDT 24
Peak memory 200772 kb
Host smart-140c2a13-7540-4ffa-9eb0-e6dbf4b93ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916878398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.916878398
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.3541178615
Short name T750
Test name
Test status
Simulation time 12076884867 ps
CPU time 8.85 seconds
Started Aug 01 05:26:05 PM PDT 24
Finished Aug 01 05:26:13 PM PDT 24
Peak memory 200852 kb
Host smart-866967ad-1e93-48f1-95e2-b8ccb44a83c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541178615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.3541178615
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3497392574
Short name T424
Test name
Test status
Simulation time 3249545249 ps
CPU time 5.99 seconds
Started Aug 01 05:26:10 PM PDT 24
Finished Aug 01 05:26:16 PM PDT 24
Peak memory 200856 kb
Host smart-4506ca03-b5b3-4aef-ab2a-6a1603121e07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497392574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.3497392574
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.30268085
Short name T483
Test name
Test status
Simulation time 2058102264 ps
CPU time 1.2 seconds
Started Aug 01 05:26:10 PM PDT 24
Finished Aug 01 05:26:12 PM PDT 24
Peak memory 200780 kb
Host smart-34c0c5ad-08bd-4ad1-b52b-7b883d7fe117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30268085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test
.30268085
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1867671035
Short name T491
Test name
Test status
Simulation time 3311961212 ps
CPU time 9.42 seconds
Started Aug 01 05:26:06 PM PDT 24
Finished Aug 01 05:26:16 PM PDT 24
Peak memory 200788 kb
Host smart-eb98f5f8-d778-45fa-a878-960a801a74f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867671035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1
867671035
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.4041817705
Short name T777
Test name
Test status
Simulation time 104560796832 ps
CPU time 21.1 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:28 PM PDT 24
Peak memory 201032 kb
Host smart-763964e0-0d75-49d1-b5cd-b9f485cb57e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041817705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.4041817705
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1590841983
Short name T694
Test name
Test status
Simulation time 135595115017 ps
CPU time 86.52 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:27:34 PM PDT 24
Peak memory 201108 kb
Host smart-5941c860-c0fb-4624-b4ac-69b1cfa5ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590841983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1590841983
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.718357057
Short name T620
Test name
Test status
Simulation time 3510329524 ps
CPU time 2.12 seconds
Started Aug 01 05:26:09 PM PDT 24
Finished Aug 01 05:26:11 PM PDT 24
Peak memory 200832 kb
Host smart-69aa1e3b-50f5-4ef1-8fd5-3f951a70ccea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718357057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_ec_pwr_on_rst.718357057
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.17507962
Short name T9
Test name
Test status
Simulation time 2865970546 ps
CPU time 6.08 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:13 PM PDT 24
Peak memory 200836 kb
Host smart-d57c482c-0f52-46cd-9a8e-54008643f6f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17507962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl
_edge_detect.17507962
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2093924769
Short name T663
Test name
Test status
Simulation time 2632820327 ps
CPU time 2.05 seconds
Started Aug 01 05:26:10 PM PDT 24
Finished Aug 01 05:26:12 PM PDT 24
Peak memory 200748 kb
Host smart-c32dc2ce-d1ff-44ab-aabf-b70f4813f979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093924769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2093924769
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3698073425
Short name T634
Test name
Test status
Simulation time 2464776972 ps
CPU time 8.51 seconds
Started Aug 01 05:26:10 PM PDT 24
Finished Aug 01 05:26:19 PM PDT 24
Peak memory 200796 kb
Host smart-deeb40ab-4b2c-4c76-a83a-9d4883ad9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698073425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3698073425
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.481969705
Short name T740
Test name
Test status
Simulation time 2139499293 ps
CPU time 1.15 seconds
Started Aug 01 05:26:09 PM PDT 24
Finished Aug 01 05:26:11 PM PDT 24
Peak memory 200716 kb
Host smart-ec501a02-aeaf-4f29-9828-e5b2b1390f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481969705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.481969705
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.934676092
Short name T573
Test name
Test status
Simulation time 2510753739 ps
CPU time 7.25 seconds
Started Aug 01 05:26:08 PM PDT 24
Finished Aug 01 05:26:15 PM PDT 24
Peak memory 200736 kb
Host smart-42b4c32e-85aa-46be-a954-61fad50946fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934676092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.934676092
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.580421051
Short name T481
Test name
Test status
Simulation time 2112489230 ps
CPU time 5.21 seconds
Started Aug 01 05:26:08 PM PDT 24
Finished Aug 01 05:26:13 PM PDT 24
Peak memory 200732 kb
Host smart-0089f4dd-5d9b-489e-916d-e74dca35f592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580421051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.580421051
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.3685826835
Short name T429
Test name
Test status
Simulation time 11749124913 ps
CPU time 29.87 seconds
Started Aug 01 05:26:09 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200764 kb
Host smart-6b8895c9-4763-42c2-b5bd-e80090ea5587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685826835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.3685826835
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3501153815
Short name T237
Test name
Test status
Simulation time 30503476716 ps
CPU time 66.14 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:27:14 PM PDT 24
Peak memory 209308 kb
Host smart-29a8cb08-1f88-4135-a2ec-d5c34f0bcb8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501153815 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3501153815
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2808373800
Short name T409
Test name
Test status
Simulation time 3209320186 ps
CPU time 3.13 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:10 PM PDT 24
Peak memory 200848 kb
Host smart-f6060ed6-2fdb-4d62-b248-6595b76baece
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808373800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2808373800
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.2016009584
Short name T585
Test name
Test status
Simulation time 2023079956 ps
CPU time 2.96 seconds
Started Aug 01 05:24:06 PM PDT 24
Finished Aug 01 05:24:09 PM PDT 24
Peak memory 200752 kb
Host smart-240fffc0-07ca-4755-bbe6-1519de3dbf13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016009584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.2016009584
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1935768008
Short name T218
Test name
Test status
Simulation time 275134436762 ps
CPU time 186.75 seconds
Started Aug 01 05:24:07 PM PDT 24
Finished Aug 01 05:27:14 PM PDT 24
Peak memory 200904 kb
Host smart-451f0ca1-27dc-44d0-b5db-7dc6f89a8a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935768008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.1935768008
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.3970463634
Short name T282
Test name
Test status
Simulation time 30802928748 ps
CPU time 20.93 seconds
Started Aug 01 05:24:07 PM PDT 24
Finished Aug 01 05:24:28 PM PDT 24
Peak memory 201076 kb
Host smart-433c6e80-10ab-481a-8d34-1b3ec09d3b48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970463634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.3970463634
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3469136804
Short name T790
Test name
Test status
Simulation time 2138636743 ps
CPU time 5.93 seconds
Started Aug 01 05:24:08 PM PDT 24
Finished Aug 01 05:24:14 PM PDT 24
Peak memory 200740 kb
Host smart-7ec60f43-4320-4b09-806b-bbb5076fef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469136804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.3469136804
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1176858180
Short name T655
Test name
Test status
Simulation time 2517895638 ps
CPU time 6.97 seconds
Started Aug 01 05:24:05 PM PDT 24
Finished Aug 01 05:24:12 PM PDT 24
Peak memory 200724 kb
Host smart-37b4ad01-6884-44f6-a6a7-c4b3bfdeeb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176858180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1176858180
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3089997565
Short name T109
Test name
Test status
Simulation time 26584952226 ps
CPU time 62.36 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:25:06 PM PDT 24
Peak memory 201052 kb
Host smart-61d84d2e-30d3-439e-8ff3-77c9980863c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089997565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3089997565
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1734906818
Short name T686
Test name
Test status
Simulation time 2836940292 ps
CPU time 1.12 seconds
Started Aug 01 05:24:10 PM PDT 24
Finished Aug 01 05:24:12 PM PDT 24
Peak memory 200308 kb
Host smart-51f698c5-a58d-4647-8dee-5581864d27e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734906818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1734906818
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1480597639
Short name T222
Test name
Test status
Simulation time 3370009571 ps
CPU time 7.19 seconds
Started Aug 01 05:24:06 PM PDT 24
Finished Aug 01 05:24:14 PM PDT 24
Peak memory 200800 kb
Host smart-72df2497-1107-40b2-9e1e-f754f70779f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480597639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.1480597639
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.4236669212
Short name T464
Test name
Test status
Simulation time 2614169847 ps
CPU time 6.92 seconds
Started Aug 01 05:24:08 PM PDT 24
Finished Aug 01 05:24:15 PM PDT 24
Peak memory 200784 kb
Host smart-17131a62-a991-486e-b55f-dfa1f8525c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236669212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.4236669212
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3456828527
Short name T21
Test name
Test status
Simulation time 2448777747 ps
CPU time 3.67 seconds
Started Aug 01 05:24:05 PM PDT 24
Finished Aug 01 05:24:09 PM PDT 24
Peak memory 200784 kb
Host smart-d14d871b-73bf-4daa-a216-cd8faba70d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456828527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3456828527
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3960418317
Short name T410
Test name
Test status
Simulation time 2111770432 ps
CPU time 1.06 seconds
Started Aug 01 05:24:13 PM PDT 24
Finished Aug 01 05:24:14 PM PDT 24
Peak memory 200668 kb
Host smart-a0f59dca-fe8c-4a1b-be2c-8bb637d23933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960418317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3960418317
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1685365336
Short name T618
Test name
Test status
Simulation time 2509487685 ps
CPU time 6.76 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:24:10 PM PDT 24
Peak memory 200724 kb
Host smart-cc02650c-2f75-4905-998f-df3177d787f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685365336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1685365336
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1480174430
Short name T133
Test name
Test status
Simulation time 22012826682 ps
CPU time 56.44 seconds
Started Aug 01 05:24:05 PM PDT 24
Finished Aug 01 05:25:02 PM PDT 24
Peak memory 220632 kb
Host smart-45358c6b-f057-46fb-8db7-069fe0a20cc5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480174430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1480174430
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3132644061
Short name T701
Test name
Test status
Simulation time 2116702339 ps
CPU time 3.22 seconds
Started Aug 01 05:24:11 PM PDT 24
Finished Aug 01 05:24:15 PM PDT 24
Peak memory 200660 kb
Host smart-384e418c-ba26-45bb-ac29-5284c4143893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132644061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3132644061
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.326384614
Short name T181
Test name
Test status
Simulation time 150890064222 ps
CPU time 209.13 seconds
Started Aug 01 05:24:10 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 200616 kb
Host smart-1576b6d8-3037-46d6-b026-e3f95609b117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326384614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_str
ess_all.326384614
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3058981575
Short name T73
Test name
Test status
Simulation time 7972768975 ps
CPU time 3.62 seconds
Started Aug 01 05:24:03 PM PDT 24
Finished Aug 01 05:24:07 PM PDT 24
Peak memory 200856 kb
Host smart-5c4fabb0-7fc0-4f2b-bb5d-dea7223c5277
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058981575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.3058981575
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.1020012290
Short name T767
Test name
Test status
Simulation time 2039459911 ps
CPU time 1.75 seconds
Started Aug 01 05:26:03 PM PDT 24
Finished Aug 01 05:26:05 PM PDT 24
Peak memory 201044 kb
Host smart-e6a089ba-5a92-4019-9468-f9aba1effaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020012290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.1020012290
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3368583314
Short name T532
Test name
Test status
Simulation time 3240935934 ps
CPU time 2.35 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:10 PM PDT 24
Peak memory 200880 kb
Host smart-d2b5e24a-ba81-41e2-bc06-15f6d7d8b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368583314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
368583314
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.1425359942
Short name T111
Test name
Test status
Simulation time 32116461035 ps
CPU time 38.5 seconds
Started Aug 01 05:26:04 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200948 kb
Host smart-dbedf0ad-2cf0-48fc-8815-3a24548d6b4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425359942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.1425359942
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1894690268
Short name T709
Test name
Test status
Simulation time 66124894368 ps
CPU time 40.78 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:47 PM PDT 24
Peak memory 201024 kb
Host smart-7c5a9b56-22fe-467d-ba4d-6acf900e3964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894690268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.1894690268
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2614605974
Short name T674
Test name
Test status
Simulation time 3713240312 ps
CPU time 5.26 seconds
Started Aug 01 05:26:06 PM PDT 24
Finished Aug 01 05:26:12 PM PDT 24
Peak memory 200808 kb
Host smart-d851e8f2-47c6-427f-ad50-8f11e237f92f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614605974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2614605974
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.1181413633
Short name T692
Test name
Test status
Simulation time 3441679935 ps
CPU time 9.17 seconds
Started Aug 01 05:26:08 PM PDT 24
Finished Aug 01 05:26:17 PM PDT 24
Peak memory 200840 kb
Host smart-b384a777-4037-414e-89a2-c292427ea1f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181413633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.1181413633
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1238436328
Short name T151
Test name
Test status
Simulation time 2610190804 ps
CPU time 7.37 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:14 PM PDT 24
Peak memory 200776 kb
Host smart-ebade29e-17e4-4a11-a129-fdb07a504de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238436328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1238436328
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.571119537
Short name T778
Test name
Test status
Simulation time 2464276086 ps
CPU time 3.76 seconds
Started Aug 01 05:26:09 PM PDT 24
Finished Aug 01 05:26:13 PM PDT 24
Peak memory 200684 kb
Host smart-0cb06e0b-c7bd-44e6-a9a9-fac1dda9889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571119537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.571119537
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.67801272
Short name T292
Test name
Test status
Simulation time 2188551073 ps
CPU time 3.17 seconds
Started Aug 01 05:26:08 PM PDT 24
Finished Aug 01 05:26:12 PM PDT 24
Peak memory 200800 kb
Host smart-18bbdfa5-4c64-4da0-87ad-b2586b8b5165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67801272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.67801272
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3723677045
Short name T679
Test name
Test status
Simulation time 2715717814 ps
CPU time 1.17 seconds
Started Aug 01 05:26:08 PM PDT 24
Finished Aug 01 05:26:10 PM PDT 24
Peak memory 200700 kb
Host smart-5e077847-fcb3-48f3-aeae-fa5bf4fda69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723677045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3723677045
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.2076758349
Short name T751
Test name
Test status
Simulation time 2111585633 ps
CPU time 6.02 seconds
Started Aug 01 05:26:05 PM PDT 24
Finished Aug 01 05:26:12 PM PDT 24
Peak memory 200736 kb
Host smart-2929ae91-d5ec-4340-a5be-61e04f637157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076758349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2076758349
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.2549800791
Short name T503
Test name
Test status
Simulation time 13603893858 ps
CPU time 8.49 seconds
Started Aug 01 05:26:07 PM PDT 24
Finished Aug 01 05:26:16 PM PDT 24
Peak memory 200920 kb
Host smart-c1df393c-47e8-4a19-a19d-51adb0475b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549800791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.2549800791
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1054444470
Short name T176
Test name
Test status
Simulation time 40635448110 ps
CPU time 107.01 seconds
Started Aug 01 05:26:09 PM PDT 24
Finished Aug 01 05:27:57 PM PDT 24
Peak memory 209404 kb
Host smart-d3e37459-dce0-40dd-b683-2d2ce502433f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054444470 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1054444470
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3489038421
Short name T499
Test name
Test status
Simulation time 3994610825 ps
CPU time 3.36 seconds
Started Aug 01 05:26:06 PM PDT 24
Finished Aug 01 05:26:09 PM PDT 24
Peak memory 200816 kb
Host smart-17ac83e7-9bf6-43c8-a5b7-9262affc2e0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489038421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.3489038421
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.3489632006
Short name T434
Test name
Test status
Simulation time 2015852377 ps
CPU time 3.38 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200800 kb
Host smart-0f059806-044e-4760-9074-47ecb878bf99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489632006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.3489632006
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3805200068
Short name T757
Test name
Test status
Simulation time 3628542866 ps
CPU time 9.96 seconds
Started Aug 01 05:26:20 PM PDT 24
Finished Aug 01 05:26:30 PM PDT 24
Peak memory 200740 kb
Host smart-9c90ce30-a0b2-4295-b5fa-37585f5891cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805200068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3
805200068
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3936161540
Short name T203
Test name
Test status
Simulation time 132045533199 ps
CPU time 355.66 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:32:18 PM PDT 24
Peak memory 201036 kb
Host smart-f89221c4-ce99-493e-a65e-343d2837e9fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936161540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.3936161540
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.454236742
Short name T598
Test name
Test status
Simulation time 4005633611 ps
CPU time 3.15 seconds
Started Aug 01 05:26:24 PM PDT 24
Finished Aug 01 05:26:28 PM PDT 24
Peak memory 200724 kb
Host smart-b352079a-31b1-4043-ae77-ac1e5ae2b798
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454236742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.454236742
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.1879898863
Short name T443
Test name
Test status
Simulation time 2467502172 ps
CPU time 6.35 seconds
Started Aug 01 05:26:21 PM PDT 24
Finished Aug 01 05:26:28 PM PDT 24
Peak memory 200884 kb
Host smart-34b53167-aa6e-4163-a252-d9cc8b69f958
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879898863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.1879898863
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2317002479
Short name T651
Test name
Test status
Simulation time 2612777719 ps
CPU time 6.77 seconds
Started Aug 01 05:26:25 PM PDT 24
Finished Aug 01 05:26:32 PM PDT 24
Peak memory 200796 kb
Host smart-941c3f3d-adb4-4077-9e45-9208a2860af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317002479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2317002479
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3028440314
Short name T204
Test name
Test status
Simulation time 2522897025 ps
CPU time 1.18 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:23 PM PDT 24
Peak memory 200788 kb
Host smart-9e7924a5-4fc8-454f-aac0-690fbecf2aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028440314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.3028440314
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.568552760
Short name T233
Test name
Test status
Simulation time 2074482181 ps
CPU time 1.82 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200788 kb
Host smart-ec50e760-6bca-44e7-ab3d-8f9e5d6d2aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568552760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.568552760
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2538940199
Short name T728
Test name
Test status
Simulation time 2518882611 ps
CPU time 3.99 seconds
Started Aug 01 05:26:21 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200784 kb
Host smart-104a1c56-436d-4948-82f5-427c10a2d121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538940199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2538940199
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.3209740324
Short name T597
Test name
Test status
Simulation time 2113708025 ps
CPU time 3.37 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:26 PM PDT 24
Peak memory 200664 kb
Host smart-b5c6dfd6-ccf6-4ede-a805-258faeba9aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209740324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3209740324
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.3626626701
Short name T41
Test name
Test status
Simulation time 15398818450 ps
CPU time 31.25 seconds
Started Aug 01 05:26:27 PM PDT 24
Finished Aug 01 05:26:58 PM PDT 24
Peak memory 200900 kb
Host smart-f8219cef-85b0-44cd-bf5d-c3a3e7f2ea6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626626701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.3626626701
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2790320501
Short name T165
Test name
Test status
Simulation time 27004059365 ps
CPU time 61.22 seconds
Started Aug 01 05:26:24 PM PDT 24
Finished Aug 01 05:27:26 PM PDT 24
Peak memory 217496 kb
Host smart-4699e660-0500-4c9e-af88-b90a08644ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790320501 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2790320501
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.722651473
Short name T413
Test name
Test status
Simulation time 5952927026 ps
CPU time 1.18 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:24 PM PDT 24
Peak memory 200880 kb
Host smart-e434adf8-1e8d-4499-8e98-e861ac4056ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722651473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ultra_low_pwr.722651473
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.2245162630
Short name T247
Test name
Test status
Simulation time 2038120348 ps
CPU time 1.86 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:24 PM PDT 24
Peak memory 200736 kb
Host smart-4a1e066f-b234-458a-b636-01c9cc27a5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245162630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.2245162630
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1363053322
Short name T507
Test name
Test status
Simulation time 140945163131 ps
CPU time 35.83 seconds
Started Aug 01 05:26:20 PM PDT 24
Finished Aug 01 05:26:56 PM PDT 24
Peak memory 200764 kb
Host smart-27584d98-1c6f-4d68-a129-853b7dc85ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363053322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1
363053322
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1574524541
Short name T355
Test name
Test status
Simulation time 26945926933 ps
CPU time 17.52 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:41 PM PDT 24
Peak memory 201004 kb
Host smart-9aa681ef-3484-4732-9a25-aef2a7d40662
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574524541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1574524541
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1691331445
Short name T739
Test name
Test status
Simulation time 23853859810 ps
CPU time 15.49 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:37 PM PDT 24
Peak memory 201032 kb
Host smart-33b33a4c-2d2c-45d6-b6d9-ba01b2267162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691331445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.1691331445
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1768142690
Short name T720
Test name
Test status
Simulation time 2742817809 ps
CPU time 4 seconds
Started Aug 01 05:26:26 PM PDT 24
Finished Aug 01 05:26:30 PM PDT 24
Peak memory 200764 kb
Host smart-0685e358-0a4b-4181-9c9e-70c0d06ba677
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768142690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.1768142690
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1246572959
Short name T473
Test name
Test status
Simulation time 2994548787 ps
CPU time 3.58 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:26 PM PDT 24
Peak memory 200848 kb
Host smart-dc2b9bf8-bf5d-4acf-ae68-e9b1bdf31a96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246572959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.1246572959
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.845065729
Short name T565
Test name
Test status
Simulation time 2633218339 ps
CPU time 2.35 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:24 PM PDT 24
Peak memory 200744 kb
Host smart-2d25e8a5-afc8-46a0-b9dc-367d8d51cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845065729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.845065729
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2582290750
Short name T23
Test name
Test status
Simulation time 2479680414 ps
CPU time 2.28 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200724 kb
Host smart-764f34df-6a87-490b-9057-ab6cbaeda3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582290750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.2582290750
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4069795968
Short name T153
Test name
Test status
Simulation time 2112442026 ps
CPU time 5.61 seconds
Started Aug 01 05:26:20 PM PDT 24
Finished Aug 01 05:26:26 PM PDT 24
Peak memory 200720 kb
Host smart-b32ea40d-bd50-4c6c-a7dd-a78bc0691768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069795968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.4069795968
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3455821584
Short name T715
Test name
Test status
Simulation time 2513976225 ps
CPU time 7.38 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:29 PM PDT 24
Peak memory 200776 kb
Host smart-4bd3bcae-6ff0-4d46-9f71-46f946ae66ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455821584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3455821584
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.3363167799
Short name T648
Test name
Test status
Simulation time 2187493646 ps
CPU time 0.91 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:24 PM PDT 24
Peak memory 200776 kb
Host smart-eaec3929-a656-4da8-854c-5c9518024c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363167799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.3363167799
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1076394078
Short name T378
Test name
Test status
Simulation time 107748217774 ps
CPU time 143.8 seconds
Started Aug 01 05:26:21 PM PDT 24
Finished Aug 01 05:28:45 PM PDT 24
Peak memory 200932 kb
Host smart-6f0b3abb-1773-44b5-b100-5c820b922593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076394078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1076394078
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2368815986
Short name T146
Test name
Test status
Simulation time 1483442648317 ps
CPU time 553.29 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:35:37 PM PDT 24
Peak memory 209444 kb
Host smart-817a2be4-d163-4239-9389-88f9c693580d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368815986 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2368815986
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.4205493317
Short name T537
Test name
Test status
Simulation time 5497486100 ps
CPU time 2.13 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200816 kb
Host smart-b90bd4bf-aec2-4da5-a0e1-b660c6a59af2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205493317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.4205493317
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.4225969469
Short name T154
Test name
Test status
Simulation time 2020587707 ps
CPU time 2.95 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200704 kb
Host smart-303c2283-8794-409a-8b5c-0e53c2cb8158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225969469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.4225969469
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1096289951
Short name T563
Test name
Test status
Simulation time 3424631061 ps
CPU time 9.71 seconds
Started Aug 01 05:26:21 PM PDT 24
Finished Aug 01 05:26:31 PM PDT 24
Peak memory 200728 kb
Host smart-f11535ae-cb61-4005-b16a-c2ba5eff53e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096289951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1
096289951
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.2962927420
Short name T376
Test name
Test status
Simulation time 56242235879 ps
CPU time 40.85 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:27:03 PM PDT 24
Peak memory 200984 kb
Host smart-7925ae82-76f9-4512-8e44-e121075a6043
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962927420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.2962927420
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1642456237
Short name T388
Test name
Test status
Simulation time 51525006314 ps
CPU time 68.93 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:27:31 PM PDT 24
Peak memory 201060 kb
Host smart-a5b4897d-c40e-4aeb-9c51-bba994aa4938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642456237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.1642456237
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1577116687
Short name T723
Test name
Test status
Simulation time 2786350424 ps
CPU time 2.63 seconds
Started Aug 01 05:26:20 PM PDT 24
Finished Aug 01 05:26:23 PM PDT 24
Peak memory 200820 kb
Host smart-bc186cc5-33e0-462a-ba41-795f3526510f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577116687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1577116687
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.263698609
Short name T37
Test name
Test status
Simulation time 4998262300 ps
CPU time 3.39 seconds
Started Aug 01 05:26:21 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200844 kb
Host smart-6bc26bf7-59bc-404b-b083-59045e7b8beb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263698609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctr
l_edge_detect.263698609
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.566944546
Short name T68
Test name
Test status
Simulation time 2621616713 ps
CPU time 4.12 seconds
Started Aug 01 05:26:24 PM PDT 24
Finished Aug 01 05:26:29 PM PDT 24
Peak memory 200728 kb
Host smart-4489a6cc-c105-4a9b-a0db-c793c7e93900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566944546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.566944546
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.601971886
Short name T485
Test name
Test status
Simulation time 2464155168 ps
CPU time 7.71 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:31 PM PDT 24
Peak memory 200768 kb
Host smart-06b1fffe-01c9-46a1-b6e0-6757c1ae23f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601971886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.601971886
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3968315090
Short name T635
Test name
Test status
Simulation time 2056320019 ps
CPU time 3.22 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:26 PM PDT 24
Peak memory 200736 kb
Host smart-c3caaa5e-dacb-4dd8-97ca-f6971ee63a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968315090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.3968315090
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.819699316
Short name T724
Test name
Test status
Simulation time 2513671296 ps
CPU time 6.99 seconds
Started Aug 01 05:26:21 PM PDT 24
Finished Aug 01 05:26:28 PM PDT 24
Peak memory 200788 kb
Host smart-a98edea3-65cd-48a0-adb8-a54098ad5b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819699316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.819699316
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2241930344
Short name T776
Test name
Test status
Simulation time 2109519096 ps
CPU time 6.07 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:29 PM PDT 24
Peak memory 200688 kb
Host smart-4b4fb292-b414-4b6f-a608-dd5f099bf605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241930344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2241930344
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3727544305
Short name T705
Test name
Test status
Simulation time 64921699354 ps
CPU time 159.55 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:29:02 PM PDT 24
Peak memory 201008 kb
Host smart-29f3ca07-5196-4c27-ac19-55131f07253d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727544305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3727544305
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2231828152
Short name T308
Test name
Test status
Simulation time 42512062319 ps
CPU time 101.96 seconds
Started Aug 01 05:26:25 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 209444 kb
Host smart-36797a88-02f1-452e-9f96-3b5d6aff7266
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231828152 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2231828152
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3689848898
Short name T748
Test name
Test status
Simulation time 5201879974 ps
CPU time 2.29 seconds
Started Aug 01 05:26:26 PM PDT 24
Finished Aug 01 05:26:28 PM PDT 24
Peak memory 200816 kb
Host smart-63d9785e-b665-4ee5-9829-70bb2755e050
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689848898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.3689848898
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2141118915
Short name T506
Test name
Test status
Simulation time 2014576018 ps
CPU time 5.47 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200832 kb
Host smart-f012c16d-fa78-4dbd-a574-291b5ff0189b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141118915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2141118915
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3674165994
Short name T120
Test name
Test status
Simulation time 3842404493 ps
CPU time 1.9 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:26:35 PM PDT 24
Peak memory 200856 kb
Host smart-e664b5d7-0be4-4bd0-99eb-1e26360f37a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674165994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3
674165994
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.977649757
Short name T791
Test name
Test status
Simulation time 20025054628 ps
CPU time 14.86 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:26:48 PM PDT 24
Peak memory 201012 kb
Host smart-9b3f0288-7b1a-45a8-b2f5-48378b39e55c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977649757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_combo_detect.977649757
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.4109786615
Short name T639
Test name
Test status
Simulation time 123516325135 ps
CPU time 85.95 seconds
Started Aug 01 05:26:35 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 201048 kb
Host smart-37015d42-ee8a-4430-8c75-3eb4761c1edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109786615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.4109786615
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.229067700
Short name T589
Test name
Test status
Simulation time 2965112289 ps
CPU time 2.48 seconds
Started Aug 01 05:26:23 PM PDT 24
Finished Aug 01 05:26:26 PM PDT 24
Peak memory 200772 kb
Host smart-ce992283-99d2-47e6-ac91-4941df87fb72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229067700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_ec_pwr_on_rst.229067700
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.1660554813
Short name T667
Test name
Test status
Simulation time 4005430068 ps
CPU time 9.22 seconds
Started Aug 01 05:26:35 PM PDT 24
Finished Aug 01 05:26:45 PM PDT 24
Peak memory 200864 kb
Host smart-095d4a06-06e4-477c-9280-62e3fc3b710d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660554813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.1660554813
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1161023969
Short name T478
Test name
Test status
Simulation time 2608671422 ps
CPU time 7.45 seconds
Started Aug 01 05:26:21 PM PDT 24
Finished Aug 01 05:26:29 PM PDT 24
Peak memory 200772 kb
Host smart-e905f777-06b9-4ad7-b766-820f2e4fef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161023969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1161023969
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.751891060
Short name T150
Test name
Test status
Simulation time 2483322712 ps
CPU time 2.36 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200860 kb
Host smart-deb39291-387c-45f8-8984-4da258c630a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751891060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.751891060
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3339871675
Short name T519
Test name
Test status
Simulation time 2115147640 ps
CPU time 4.35 seconds
Started Aug 01 05:26:20 PM PDT 24
Finished Aug 01 05:26:25 PM PDT 24
Peak memory 200760 kb
Host smart-068001fc-ac1d-43f3-9054-5310cd837caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339871675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3339871675
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2564330527
Short name T408
Test name
Test status
Simulation time 2509924853 ps
CPU time 6.73 seconds
Started Aug 01 05:26:22 PM PDT 24
Finished Aug 01 05:26:29 PM PDT 24
Peak memory 200744 kb
Host smart-d9969d20-e006-477d-9025-4f51e8587fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564330527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2564330527
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.827272795
Short name T774
Test name
Test status
Simulation time 2113724089 ps
CPU time 5.98 seconds
Started Aug 01 05:26:24 PM PDT 24
Finished Aug 01 05:26:30 PM PDT 24
Peak memory 200720 kb
Host smart-c9193056-9965-446c-aeaa-ba5eebf8121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827272795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.827272795
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.1554518551
Short name T258
Test name
Test status
Simulation time 129744702016 ps
CPU time 168.68 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:29:22 PM PDT 24
Peak memory 201000 kb
Host smart-faf8c300-6682-45f0-94f6-8e73f57b6362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554518551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.1554518551
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3788147198
Short name T251
Test name
Test status
Simulation time 4410363040 ps
CPU time 1.31 seconds
Started Aug 01 05:26:36 PM PDT 24
Finished Aug 01 05:26:37 PM PDT 24
Peak memory 200784 kb
Host smart-2ef96a6f-ad6a-44c1-89ab-9f5554cc0122
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788147198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.3788147198
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.971382324
Short name T653
Test name
Test status
Simulation time 2019135810 ps
CPU time 3 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:26:40 PM PDT 24
Peak memory 200800 kb
Host smart-83f0107a-ad1d-433b-9339-fd5aef99f4bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971382324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_tes
t.971382324
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.536969564
Short name T475
Test name
Test status
Simulation time 3437592694 ps
CPU time 2.32 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:37 PM PDT 24
Peak memory 200876 kb
Host smart-2fe4ba1e-db4f-4be1-8739-f1d323b2ed09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536969564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.536969564
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.1535302607
Short name T377
Test name
Test status
Simulation time 199225557365 ps
CPU time 476.37 seconds
Started Aug 01 05:26:35 PM PDT 24
Finished Aug 01 05:34:32 PM PDT 24
Peak memory 201008 kb
Host smart-739f9771-7502-441b-be6e-ff762aede6a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535302607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.1535302607
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1522572100
Short name T372
Test name
Test status
Simulation time 91576971296 ps
CPU time 60.55 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:27:34 PM PDT 24
Peak memory 201120 kb
Host smart-f154544a-9940-4087-bf56-bdd5a80bf70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522572100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.1522572100
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2272284578
Short name T780
Test name
Test status
Simulation time 3753873183 ps
CPU time 1.66 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200740 kb
Host smart-dcede9c8-228e-4723-8dab-7edfa7df144a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272284578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2272284578
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.755054817
Short name T206
Test name
Test status
Simulation time 5134762090 ps
CPU time 11.08 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:45 PM PDT 24
Peak memory 200816 kb
Host smart-372ddfd8-d267-4625-ad45-f671c65b84df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755054817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctr
l_edge_detect.755054817
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1328350403
Short name T746
Test name
Test status
Simulation time 2609560316 ps
CPU time 5.7 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:26:38 PM PDT 24
Peak memory 200808 kb
Host smart-c8266d46-6b4b-4e63-b33c-64c47bcd68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328350403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.1328350403
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1529430494
Short name T486
Test name
Test status
Simulation time 2465186430 ps
CPU time 2.47 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:26:36 PM PDT 24
Peak memory 200692 kb
Host smart-a7416fa0-58d1-4273-8fc6-2c53aa790a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529430494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1529430494
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.521379166
Short name T495
Test name
Test status
Simulation time 2160749208 ps
CPU time 3.96 seconds
Started Aug 01 05:26:35 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200784 kb
Host smart-dbca9d9a-ea3a-4f84-91e1-6b1a5aa84649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521379166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.521379166
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1469281364
Short name T7
Test name
Test status
Simulation time 2512947039 ps
CPU time 5.65 seconds
Started Aug 01 05:26:32 PM PDT 24
Finished Aug 01 05:26:38 PM PDT 24
Peak memory 200808 kb
Host smart-b67495f8-bf7c-4ae4-99a1-b9a971b94ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469281364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.1469281364
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2622529075
Short name T427
Test name
Test status
Simulation time 2131872457 ps
CPU time 1.92 seconds
Started Aug 01 05:26:32 PM PDT 24
Finished Aug 01 05:26:34 PM PDT 24
Peak memory 200748 kb
Host smart-10b89a4d-5154-429d-bee2-8c7e7e1d1b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622529075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2622529075
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1505703934
Short name T325
Test name
Test status
Simulation time 49233069794 ps
CPU time 111.53 seconds
Started Aug 01 05:26:36 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 209288 kb
Host smart-1593e018-7c3e-421f-a57c-f141104b542c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505703934 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.1505703934
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1763214385
Short name T673
Test name
Test status
Simulation time 9855263889 ps
CPU time 2.71 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200888 kb
Host smart-e230b5b1-65d1-4dcc-ab4f-8a7b9d8a26a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763214385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.1763214385
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.1079731346
Short name T687
Test name
Test status
Simulation time 2011136307 ps
CPU time 5.82 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:40 PM PDT 24
Peak memory 200684 kb
Host smart-8743cbbe-b895-42af-9780-194df822b905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079731346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.1079731346
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2927059407
Short name T400
Test name
Test status
Simulation time 3312727053 ps
CPU time 5.04 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200960 kb
Host smart-dc628c24-9996-4436-bb16-def57f265525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927059407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2
927059407
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1766823087
Short name T669
Test name
Test status
Simulation time 155130180841 ps
CPU time 204.72 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:29:58 PM PDT 24
Peak memory 201068 kb
Host smart-85eae184-305f-4dec-b6e1-c98d3d874f19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766823087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.1766823087
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2524947755
Short name T115
Test name
Test status
Simulation time 28118829240 ps
CPU time 14.16 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:48 PM PDT 24
Peak memory 201128 kb
Host smart-556c351d-ce97-49ff-b431-0be2fd76d530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524947755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.2524947755
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.232395997
Short name T604
Test name
Test status
Simulation time 4591403600 ps
CPU time 3.46 seconds
Started Aug 01 05:26:32 PM PDT 24
Finished Aug 01 05:26:35 PM PDT 24
Peak memory 200780 kb
Host smart-d788d298-3b26-49c7-a634-e9b6f47b91be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232395997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.232395997
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3334342072
Short name T42
Test name
Test status
Simulation time 3538507865 ps
CPU time 2.79 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:26:36 PM PDT 24
Peak memory 200772 kb
Host smart-6e6d6e35-adff-4a8e-a451-777a0399979c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334342072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3334342072
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.615429102
Short name T201
Test name
Test status
Simulation time 2630653519 ps
CPU time 2.23 seconds
Started Aug 01 05:26:41 PM PDT 24
Finished Aug 01 05:26:44 PM PDT 24
Peak memory 200784 kb
Host smart-0892b371-ab47-435b-a61b-3e7741d008c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615429102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.615429102
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3450367866
Short name T63
Test name
Test status
Simulation time 2467449525 ps
CPU time 3.84 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:38 PM PDT 24
Peak memory 200732 kb
Host smart-a857820c-5f3a-4845-ae8a-10bf3581e8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450367866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3450367866
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1986662770
Short name T304
Test name
Test status
Simulation time 2232784650 ps
CPU time 2.13 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:36 PM PDT 24
Peak memory 200796 kb
Host smart-c7f5e20e-692b-4cec-b987-19ad85bd0773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986662770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1986662770
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2142225850
Short name T71
Test name
Test status
Simulation time 2520681773 ps
CPU time 3.86 seconds
Started Aug 01 05:26:36 PM PDT 24
Finished Aug 01 05:26:40 PM PDT 24
Peak memory 200728 kb
Host smart-3ecd5535-da10-4384-95b6-97e2cfbcaec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142225850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2142225850
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.1660620840
Short name T421
Test name
Test status
Simulation time 2109386828 ps
CPU time 5.16 seconds
Started Aug 01 05:26:32 PM PDT 24
Finished Aug 01 05:26:37 PM PDT 24
Peak memory 200748 kb
Host smart-30fa9976-b89d-4a0d-82ba-2df3e9094598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660620840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1660620840
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.3097696059
Short name T140
Test name
Test status
Simulation time 10517235416 ps
CPU time 25.32 seconds
Started Aug 01 05:26:36 PM PDT 24
Finished Aug 01 05:27:01 PM PDT 24
Peak memory 200836 kb
Host smart-b00a665c-c224-46b8-85dd-6b27011190be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097696059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.3097696059
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.720853321
Short name T487
Test name
Test status
Simulation time 3732198003 ps
CPU time 2.13 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:36 PM PDT 24
Peak memory 200884 kb
Host smart-b64454ea-3f6d-4d48-8a6e-6942a2bd1ef9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720853321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.720853321
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.1278897477
Short name T511
Test name
Test status
Simulation time 2016375550 ps
CPU time 3.19 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:26:44 PM PDT 24
Peak memory 200848 kb
Host smart-d71f1b77-76da-466e-9a9f-26eade2ecf83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278897477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.1278897477
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.407151860
Short name T25
Test name
Test status
Simulation time 4135152235 ps
CPU time 1.75 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200896 kb
Host smart-4c19c26e-a107-4f35-8e9f-ef0e497db3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407151860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.407151860
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.1271901357
Short name T99
Test name
Test status
Simulation time 130578407129 ps
CPU time 325.54 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:32:02 PM PDT 24
Peak memory 200892 kb
Host smart-83dec419-8019-4e3f-9e14-9bf2f17be388
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271901357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.1271901357
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3213231486
Short name T623
Test name
Test status
Simulation time 2797326124 ps
CPU time 3.65 seconds
Started Aug 01 05:26:35 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200796 kb
Host smart-a1035ffa-df1d-4744-bd22-3e711092faeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213231486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3213231486
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.168543815
Short name T743
Test name
Test status
Simulation time 5954454770 ps
CPU time 1.19 seconds
Started Aug 01 05:26:33 PM PDT 24
Finished Aug 01 05:26:34 PM PDT 24
Peak memory 200816 kb
Host smart-3322a5de-287f-4cb2-a5f7-7c2362446cc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168543815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctr
l_edge_detect.168543815
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1562306919
Short name T465
Test name
Test status
Simulation time 2641684275 ps
CPU time 2.21 seconds
Started Aug 01 05:26:35 PM PDT 24
Finished Aug 01 05:26:37 PM PDT 24
Peak memory 200780 kb
Host smart-85c7199c-a3a7-4e47-8a44-8390c711d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562306919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.1562306919
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2246714579
Short name T450
Test name
Test status
Simulation time 2482540845 ps
CPU time 4 seconds
Started Aug 01 05:26:39 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200784 kb
Host smart-c398faf2-2f73-43e6-848f-e9880470c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246714579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2246714579
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2327231201
Short name T399
Test name
Test status
Simulation time 2158667852 ps
CPU time 3.45 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:26:41 PM PDT 24
Peak memory 200740 kb
Host smart-d644491c-8926-46c7-ab61-964d7540073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327231201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2327231201
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1606807150
Short name T440
Test name
Test status
Simulation time 2511941911 ps
CPU time 7.14 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:26:41 PM PDT 24
Peak memory 200776 kb
Host smart-ba1c2e35-6734-4dfb-a86e-311fe93d3909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606807150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1606807150
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3826919068
Short name T695
Test name
Test status
Simulation time 2116191497 ps
CPU time 3.31 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:26:40 PM PDT 24
Peak memory 200608 kb
Host smart-0890e087-ba80-4260-89eb-bcdf21464f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826919068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3826919068
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.442761656
Short name T350
Test name
Test status
Simulation time 144822887090 ps
CPU time 92.3 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:28:13 PM PDT 24
Peak memory 201080 kb
Host smart-40003135-c038-4f98-a247-4170635bb198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442761656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_st
ress_all.442761656
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2263218993
Short name T352
Test name
Test status
Simulation time 100253928012 ps
CPU time 67.84 seconds
Started Aug 01 05:26:41 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 209440 kb
Host smart-e7e8f15f-bf0c-49b4-9020-238c936c7492
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263218993 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.2263218993
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2482476147
Short name T531
Test name
Test status
Simulation time 850094318705 ps
CPU time 19.53 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:27:00 PM PDT 24
Peak memory 200864 kb
Host smart-a06a6f24-7310-4fb7-a7f4-fcfc2ae54752
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482476147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.2482476147
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.4255572479
Short name T587
Test name
Test status
Simulation time 2013556004 ps
CPU time 5.44 seconds
Started Aug 01 05:26:36 PM PDT 24
Finished Aug 01 05:26:42 PM PDT 24
Peak memory 200796 kb
Host smart-5eed54c2-6541-4f52-9579-fe3bfbc7d22f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255572479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.4255572479
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.40663202
Short name T513
Test name
Test status
Simulation time 3380655789 ps
CPU time 2.18 seconds
Started Aug 01 05:26:39 PM PDT 24
Finished Aug 01 05:26:42 PM PDT 24
Peak memory 200808 kb
Host smart-a6cb39ad-cad5-4d4d-979b-9d0d5fbca0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40663202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.40663202
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.763496820
Short name T239
Test name
Test status
Simulation time 55927823959 ps
CPU time 146.31 seconds
Started Aug 01 05:26:34 PM PDT 24
Finished Aug 01 05:29:00 PM PDT 24
Peak memory 200956 kb
Host smart-796c1cd1-6ab4-4312-a9ed-5d98d1e6f3f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763496820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_combo_detect.763496820
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3483396799
Short name T402
Test name
Test status
Simulation time 3375185125 ps
CPU time 1.52 seconds
Started Aug 01 05:26:41 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200792 kb
Host smart-c044407b-2ac9-4927-a5a2-fafe49933ce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483396799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3483396799
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2636334129
Short name T232
Test name
Test status
Simulation time 3975346594 ps
CPU time 8.19 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:26:48 PM PDT 24
Peak memory 200852 kb
Host smart-82af7ed7-c85f-4745-b3a7-2be2f23e229c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636334129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.2636334129
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1391157865
Short name T575
Test name
Test status
Simulation time 2607988227 ps
CPU time 7.55 seconds
Started Aug 01 05:26:36 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200728 kb
Host smart-2711ba77-2cf4-4517-a53a-dc794f64431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391157865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1391157865
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2760758859
Short name T553
Test name
Test status
Simulation time 2498860094 ps
CPU time 2.04 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:26:40 PM PDT 24
Peak memory 200724 kb
Host smart-d1927272-1f59-4823-bf98-3688b896a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760758859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2760758859
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1047903545
Short name T700
Test name
Test status
Simulation time 2054691283 ps
CPU time 4 seconds
Started Aug 01 05:26:39 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200780 kb
Host smart-e5fa6f08-0600-4ec2-b277-7e34d401fab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047903545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1047903545
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.110405322
Short name T588
Test name
Test status
Simulation time 2514271404 ps
CPU time 3.73 seconds
Started Aug 01 05:26:32 PM PDT 24
Finished Aug 01 05:26:36 PM PDT 24
Peak memory 200728 kb
Host smart-025c05c4-9ec8-4337-a58d-05607e85e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110405322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.110405322
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.2108975294
Short name T581
Test name
Test status
Simulation time 2114821699 ps
CPU time 3.22 seconds
Started Aug 01 05:26:36 PM PDT 24
Finished Aug 01 05:26:40 PM PDT 24
Peak memory 200736 kb
Host smart-6d3a3c35-dd6f-4d41-9809-2d3efc633a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108975294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2108975294
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.3355713469
Short name T193
Test name
Test status
Simulation time 16425554557 ps
CPU time 11.63 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:26:50 PM PDT 24
Peak memory 200840 kb
Host smart-04141a2c-bb53-4206-a02f-be7a06940461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355713469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.3355713469
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.757063709
Short name T256
Test name
Test status
Simulation time 216129442437 ps
CPU time 138.55 seconds
Started Aug 01 05:26:39 PM PDT 24
Finished Aug 01 05:28:58 PM PDT 24
Peak memory 209424 kb
Host smart-fbe84965-149b-4b16-93c2-d6c79257e3c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757063709 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.757063709
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2454685353
Short name T269
Test name
Test status
Simulation time 706134423699 ps
CPU time 26.1 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 200904 kb
Host smart-6c887ac0-9518-484f-85d7-0387f8ce4255
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454685353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2454685353
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.1337132918
Short name T788
Test name
Test status
Simulation time 2030591598 ps
CPU time 2.89 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:26:40 PM PDT 24
Peak memory 200784 kb
Host smart-a84566bf-7c90-42cd-b969-90de410a3d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337132918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.1337132918
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1670842420
Short name T614
Test name
Test status
Simulation time 2953515901 ps
CPU time 2.38 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:26:41 PM PDT 24
Peak memory 200788 kb
Host smart-c0585c94-57c0-40a4-ac2f-6a6f456d4be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670842420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.1
670842420
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1325599751
Short name T753
Test name
Test status
Simulation time 157986771143 ps
CPU time 393.11 seconds
Started Aug 01 05:26:44 PM PDT 24
Finished Aug 01 05:33:17 PM PDT 24
Peak memory 201064 kb
Host smart-391cd674-9074-4fd4-96d2-c8a72d866301
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325599751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.1325599751
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2434386905
Short name T364
Test name
Test status
Simulation time 65467282635 ps
CPU time 68.98 seconds
Started Aug 01 05:26:44 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 201200 kb
Host smart-b30a73ba-1999-4f99-ae2c-076dd5751c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434386905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.2434386905
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1461520868
Short name T196
Test name
Test status
Simulation time 3223990900 ps
CPU time 4.49 seconds
Started Aug 01 05:26:39 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200692 kb
Host smart-f4dff149-80b7-41fa-8645-f5bb9baa182d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461520868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1461520868
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2660502701
Short name T471
Test name
Test status
Simulation time 2540425652 ps
CPU time 1.14 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 200796 kb
Host smart-cc37d4ce-433b-45d6-bb6a-543fd4b6180e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660502701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2660502701
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.540553168
Short name T606
Test name
Test status
Simulation time 2628736422 ps
CPU time 2.26 seconds
Started Aug 01 05:26:39 PM PDT 24
Finished Aug 01 05:26:41 PM PDT 24
Peak memory 200792 kb
Host smart-78b4c0e1-23a1-441d-8eea-1735a6d9bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540553168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.540553168
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1594221506
Short name T580
Test name
Test status
Simulation time 2492080361 ps
CPU time 2.29 seconds
Started Aug 01 05:26:44 PM PDT 24
Finished Aug 01 05:26:46 PM PDT 24
Peak memory 200804 kb
Host smart-e3e1d0b0-b9be-4684-b5ea-76dd84eed5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594221506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.1594221506
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1239992900
Short name T67
Test name
Test status
Simulation time 2172967222 ps
CPU time 5.95 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:26:45 PM PDT 24
Peak memory 200812 kb
Host smart-1787784e-15cb-438f-8b11-820811eb414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239992900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1239992900
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2390472714
Short name T631
Test name
Test status
Simulation time 2517405419 ps
CPU time 4.62 seconds
Started Aug 01 05:26:39 PM PDT 24
Finished Aug 01 05:26:43 PM PDT 24
Peak memory 200712 kb
Host smart-295b64ac-9edd-47c4-8eb9-fb69d9114f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390472714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2390472714
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.4257364941
Short name T65
Test name
Test status
Simulation time 2111074945 ps
CPU time 5.77 seconds
Started Aug 01 05:26:38 PM PDT 24
Finished Aug 01 05:26:44 PM PDT 24
Peak memory 200764 kb
Host smart-48b76944-a78f-4e0a-90de-7e497aadacf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257364941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.4257364941
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.1253584685
Short name T761
Test name
Test status
Simulation time 12157694812 ps
CPU time 33.38 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:27:11 PM PDT 24
Peak memory 200712 kb
Host smart-956c4231-f28b-4aeb-928f-86fbcabd2e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253584685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.1253584685
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3265949725
Short name T30
Test name
Test status
Simulation time 2610412549 ps
CPU time 1.79 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:26:42 PM PDT 24
Peak memory 200840 kb
Host smart-a806ef03-a268-49a2-b892-5fdab5eadb59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265949725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3265949725
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1232433599
Short name T784
Test name
Test status
Simulation time 2025316332 ps
CPU time 1.84 seconds
Started Aug 01 05:24:21 PM PDT 24
Finished Aug 01 05:24:23 PM PDT 24
Peak memory 200760 kb
Host smart-8d8b6747-4189-4698-ab48-cb7ce53f829f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232433599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1232433599
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2576927888
Short name T274
Test name
Test status
Simulation time 3225832045 ps
CPU time 8.27 seconds
Started Aug 01 05:24:18 PM PDT 24
Finished Aug 01 05:24:27 PM PDT 24
Peak memory 200880 kb
Host smart-da2c0a5d-329e-45b4-ba86-9d15e15b41d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576927888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2576927888
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3725293941
Short name T16
Test name
Test status
Simulation time 69627881659 ps
CPU time 170.34 seconds
Started Aug 01 05:24:28 PM PDT 24
Finished Aug 01 05:27:18 PM PDT 24
Peak memory 200996 kb
Host smart-2779149d-3b20-434b-b923-c1bb36603185
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725293941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3725293941
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.4091261573
Short name T474
Test name
Test status
Simulation time 385873692204 ps
CPU time 89.97 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:25:56 PM PDT 24
Peak memory 200732 kb
Host smart-36c0c0e8-5198-4104-8c1f-9eacbc7af5ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091261573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.4091261573
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3357415318
Short name T717
Test name
Test status
Simulation time 2818787826 ps
CPU time 4.37 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 200768 kb
Host smart-1bdfa7eb-66ab-4371-a471-d7c126ac9cd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357415318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3357415318
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2659745182
Short name T333
Test name
Test status
Simulation time 2630192912 ps
CPU time 2.2 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:24:29 PM PDT 24
Peak memory 200792 kb
Host smart-373fe6ff-1c98-43a4-a254-0156dfb3b477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659745182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2659745182
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.9350030
Short name T61
Test name
Test status
Simulation time 2487117296 ps
CPU time 2.08 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:24:29 PM PDT 24
Peak memory 200808 kb
Host smart-3fb7f528-024b-44be-b721-ae37cc54bb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9350030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.9350030
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2551760055
Short name T453
Test name
Test status
Simulation time 2141680382 ps
CPU time 5.49 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 200748 kb
Host smart-9b20996c-228b-4646-8fa8-8ccda21b40c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551760055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2551760055
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1123330334
Short name T683
Test name
Test status
Simulation time 2513046600 ps
CPU time 7.36 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:24:36 PM PDT 24
Peak memory 200724 kb
Host smart-92455ad5-9541-47ca-8900-e086a36ec7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123330334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1123330334
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.86643182
Short name T514
Test name
Test status
Simulation time 2121396524 ps
CPU time 3.14 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 200660 kb
Host smart-fadd636f-717d-42d8-9389-0b26b8cf6c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86643182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.86643182
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2515032814
Short name T568
Test name
Test status
Simulation time 6714139938 ps
CPU time 18.25 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:24:47 PM PDT 24
Peak memory 200680 kb
Host smart-74567cdb-80ac-4bf4-b721-a206e6714b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515032814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2515032814
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.157785833
Short name T141
Test name
Test status
Simulation time 667805253331 ps
CPU time 205.61 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 210664 kb
Host smart-24c545b7-bc9d-48cc-a557-6669a3110504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157785833 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.157785833
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.416188791
Short name T625
Test name
Test status
Simulation time 3870900126 ps
CPU time 6.09 seconds
Started Aug 01 05:24:22 PM PDT 24
Finished Aug 01 05:24:28 PM PDT 24
Peak memory 200720 kb
Host smart-66238848-73ba-4a14-86f2-00b1dbf755bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416188791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ultra_low_pwr.416188791
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2094335211
Short name T277
Test name
Test status
Simulation time 48580899577 ps
CPU time 119.07 seconds
Started Aug 01 05:26:41 PM PDT 24
Finished Aug 01 05:28:41 PM PDT 24
Peak memory 201164 kb
Host smart-1c9e407d-4f99-4b21-b052-758995d19f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094335211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.2094335211
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.674833759
Short name T368
Test name
Test status
Simulation time 145829703850 ps
CPU time 85.75 seconds
Started Aug 01 05:26:43 PM PDT 24
Finished Aug 01 05:28:09 PM PDT 24
Peak memory 201092 kb
Host smart-cfb263eb-cda5-41b8-afda-8a7a6c28f6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674833759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_wi
th_pre_cond.674833759
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4269708162
Short name T454
Test name
Test status
Simulation time 89573479061 ps
CPU time 234.53 seconds
Started Aug 01 05:26:40 PM PDT 24
Finished Aug 01 05:30:35 PM PDT 24
Peak memory 201064 kb
Host smart-6095d72b-7b27-48d0-89fd-44e266cf6977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269708162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.4269708162
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.890616101
Short name T245
Test name
Test status
Simulation time 103509431018 ps
CPU time 267.11 seconds
Started Aug 01 05:26:37 PM PDT 24
Finished Aug 01 05:31:04 PM PDT 24
Peak memory 201064 kb
Host smart-c22afe2e-d82a-4d8a-b01b-e6aafb4b72b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890616101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_wi
th_pre_cond.890616101
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2362182988
Short name T371
Test name
Test status
Simulation time 72263663781 ps
CPU time 47.18 seconds
Started Aug 01 05:26:46 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 201128 kb
Host smart-fb748da0-e953-4e6f-8336-2d66047d2a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362182988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.2362182988
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3906037436
Short name T727
Test name
Test status
Simulation time 87244426911 ps
CPU time 62.18 seconds
Started Aug 01 05:26:44 PM PDT 24
Finished Aug 01 05:27:47 PM PDT 24
Peak memory 201092 kb
Host smart-dec3e8df-499a-4040-a315-c3b8babe87ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906037436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.3906037436
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.438967947
Short name T186
Test name
Test status
Simulation time 2015483704 ps
CPU time 3.04 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 200744 kb
Host smart-d4821880-0ab9-41f1-85e0-0d9f1c98095a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438967947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test
.438967947
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1584322433
Short name T310
Test name
Test status
Simulation time 3396985573 ps
CPU time 2.87 seconds
Started Aug 01 05:24:21 PM PDT 24
Finished Aug 01 05:24:24 PM PDT 24
Peak memory 200872 kb
Host smart-88b1573d-896d-4680-9780-94810b4d743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584322433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1584322433
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.3843298380
Short name T569
Test name
Test status
Simulation time 38888667267 ps
CPU time 47.23 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:25:14 PM PDT 24
Peak memory 200968 kb
Host smart-53acf729-45e3-4832-9e67-73c46149b8a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843298380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.3843298380
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.354107462
Short name T480
Test name
Test status
Simulation time 773608696163 ps
CPU time 1880.08 seconds
Started Aug 01 05:24:28 PM PDT 24
Finished Aug 01 05:55:48 PM PDT 24
Peak memory 200680 kb
Host smart-fe9fc623-b38e-4f55-9180-3a8b93d7554e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354107462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_ec_pwr_on_rst.354107462
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.2449711544
Short name T36
Test name
Test status
Simulation time 3344642389 ps
CPU time 2.79 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:24:30 PM PDT 24
Peak memory 200840 kb
Host smart-55c34b54-446a-408b-a871-21e9a57836b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449711544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.2449711544
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1566921804
Short name T438
Test name
Test status
Simulation time 2613539699 ps
CPU time 6.7 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:24:33 PM PDT 24
Peak memory 200676 kb
Host smart-0e5d78c4-3ed4-4fb5-a7f1-3a8e2a8344b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566921804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1566921804
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2683703084
Short name T456
Test name
Test status
Simulation time 2455669503 ps
CPU time 7.93 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:24:34 PM PDT 24
Peak memory 200764 kb
Host smart-e5e87fb2-0cf4-4997-a7fd-0e8fd2191c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683703084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2683703084
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2224723209
Short name T447
Test name
Test status
Simulation time 2029464131 ps
CPU time 5.7 seconds
Started Aug 01 05:24:32 PM PDT 24
Finished Aug 01 05:24:37 PM PDT 24
Peak memory 200676 kb
Host smart-1f58ec4e-5b74-45cf-b095-31dd33e8db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224723209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.2224723209
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2174156519
Short name T293
Test name
Test status
Simulation time 2509640696 ps
CPU time 6.94 seconds
Started Aug 01 05:24:30 PM PDT 24
Finished Aug 01 05:24:37 PM PDT 24
Peak memory 200732 kb
Host smart-16ffd640-669d-4f8f-9632-3b7c8f26dc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174156519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2174156519
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.742347805
Short name T406
Test name
Test status
Simulation time 2112892912 ps
CPU time 5.81 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:24:35 PM PDT 24
Peak memory 200728 kb
Host smart-1be73e7b-18de-4f38-bb63-facbac600081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742347805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.742347805
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1098023054
Short name T296
Test name
Test status
Simulation time 110180555954 ps
CPU time 144.27 seconds
Started Aug 01 05:26:48 PM PDT 24
Finished Aug 01 05:29:12 PM PDT 24
Peak memory 201156 kb
Host smart-75e0b52f-5f84-41f7-b319-423e18ed3322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098023054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.1098023054
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3185679045
Short name T43
Test name
Test status
Simulation time 59537854492 ps
CPU time 37.83 seconds
Started Aug 01 05:26:45 PM PDT 24
Finished Aug 01 05:27:23 PM PDT 24
Peak memory 201172 kb
Host smart-c7cc9a32-f60b-44c5-80b5-46cea8f7728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185679045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.3185679045
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2186606775
Short name T348
Test name
Test status
Simulation time 155155094891 ps
CPU time 101.85 seconds
Started Aug 01 05:26:44 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 201108 kb
Host smart-5cf03b27-2187-4231-98a5-02b0fff247ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186606775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2186606775
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.557166501
Short name T112
Test name
Test status
Simulation time 26592293410 ps
CPU time 17.43 seconds
Started Aug 01 05:26:43 PM PDT 24
Finished Aug 01 05:27:01 PM PDT 24
Peak memory 201132 kb
Host smart-7ffba550-5dd5-410d-9ea4-60a7ab6db8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557166501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_wi
th_pre_cond.557166501
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3051995356
Short name T787
Test name
Test status
Simulation time 48384076463 ps
CPU time 99.36 seconds
Started Aug 01 05:26:51 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 201156 kb
Host smart-e8c3e055-2172-4576-9e56-7fed1ec02c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051995356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3051995356
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3066946182
Short name T520
Test name
Test status
Simulation time 73941118254 ps
CPU time 173.3 seconds
Started Aug 01 05:26:46 PM PDT 24
Finished Aug 01 05:29:39 PM PDT 24
Peak memory 201216 kb
Host smart-859f125a-0735-4cf2-b419-0014ff641582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066946182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.3066946182
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1756286323
Short name T276
Test name
Test status
Simulation time 23084048920 ps
CPU time 59.29 seconds
Started Aug 01 05:26:42 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 200992 kb
Host smart-c3fa8d69-2b69-4e92-b08c-5147fabd1518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756286323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.1756286323
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1061707790
Short name T349
Test name
Test status
Simulation time 104039961597 ps
CPU time 68.81 seconds
Started Aug 01 05:26:51 PM PDT 24
Finished Aug 01 05:28:00 PM PDT 24
Peak memory 201060 kb
Host smart-afd8dbac-e25c-4a2d-9b18-f61f1f7574cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061707790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.1061707790
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1597763799
Short name T668
Test name
Test status
Simulation time 28095185883 ps
CPU time 21.05 seconds
Started Aug 01 05:26:47 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 201144 kb
Host smart-85be27f6-b8ae-4169-a9a9-0640d691919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597763799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.1597763799
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3460304719
Short name T366
Test name
Test status
Simulation time 113209471498 ps
CPU time 270.1 seconds
Started Aug 01 05:26:43 PM PDT 24
Finished Aug 01 05:31:14 PM PDT 24
Peak memory 201152 kb
Host smart-ba9a0990-6c8a-4659-a5ea-fc8a32c85651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460304719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.3460304719
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.4183882065
Short name T455
Test name
Test status
Simulation time 2038234553 ps
CPU time 1.55 seconds
Started Aug 01 05:24:30 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 200708 kb
Host smart-6821c87b-40f2-44b3-8b04-862792709bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183882065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.4183882065
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.867202339
Short name T730
Test name
Test status
Simulation time 3257386066 ps
CPU time 8.85 seconds
Started Aug 01 05:24:19 PM PDT 24
Finished Aug 01 05:24:28 PM PDT 24
Peak memory 200872 kb
Host smart-ba015517-18d5-4b18-ac95-2196c6731cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867202339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.867202339
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.2909465619
Short name T283
Test name
Test status
Simulation time 189225037148 ps
CPU time 227.35 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:28:13 PM PDT 24
Peak memory 200880 kb
Host smart-050d3322-733c-4fb8-9ed6-e784e55a7c2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909465619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.2909465619
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.4010719221
Short name T664
Test name
Test status
Simulation time 41758211986 ps
CPU time 11.05 seconds
Started Aug 01 05:24:28 PM PDT 24
Finished Aug 01 05:24:39 PM PDT 24
Peak memory 201116 kb
Host smart-f0b76c0d-e786-4ba5-ad28-770bfba3affe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010719221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.4010719221
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3257136661
Short name T579
Test name
Test status
Simulation time 4714104994 ps
CPU time 3.67 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:24:30 PM PDT 24
Peak memory 200784 kb
Host smart-191a952c-3c00-401c-87b6-10a788c79cd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257136661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.3257136661
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.113266709
Short name T177
Test name
Test status
Simulation time 3038322561 ps
CPU time 1.49 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:24:28 PM PDT 24
Peak memory 200784 kb
Host smart-da5b6ab9-0f71-47af-be83-a64cdc7b3656
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113266709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl
_edge_detect.113266709
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3330105360
Short name T617
Test name
Test status
Simulation time 2614440465 ps
CPU time 7.41 seconds
Started Aug 01 05:24:28 PM PDT 24
Finished Aug 01 05:24:35 PM PDT 24
Peak memory 200760 kb
Host smart-0c936f28-576a-4889-a945-09382c4cb7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330105360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.3330105360
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3169907340
Short name T534
Test name
Test status
Simulation time 2447768141 ps
CPU time 7.41 seconds
Started Aug 01 05:24:26 PM PDT 24
Finished Aug 01 05:24:33 PM PDT 24
Peak memory 200724 kb
Host smart-59222822-a9d5-4fd9-89c5-c85665d63ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169907340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3169907340
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1675233701
Short name T773
Test name
Test status
Simulation time 2109972019 ps
CPU time 3.28 seconds
Started Aug 01 05:24:28 PM PDT 24
Finished Aug 01 05:24:31 PM PDT 24
Peak memory 200744 kb
Host smart-ffbf33a7-2e5d-4143-9bc1-ed9397d2e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675233701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1675233701
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.333233567
Short name T407
Test name
Test status
Simulation time 2513376760 ps
CPU time 7.27 seconds
Started Aug 01 05:24:32 PM PDT 24
Finished Aug 01 05:24:39 PM PDT 24
Peak memory 200732 kb
Host smart-e0f1d742-0961-4ff0-9812-5b455f72b45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333233567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.333233567
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.3458851871
Short name T768
Test name
Test status
Simulation time 2120930064 ps
CPU time 1.93 seconds
Started Aug 01 05:24:25 PM PDT 24
Finished Aug 01 05:24:27 PM PDT 24
Peak memory 200740 kb
Host smart-c7701d90-3a68-4ed5-80fb-367f8602bb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458851871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3458851871
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.3633115106
Short name T309
Test name
Test status
Simulation time 16619015767 ps
CPU time 22.36 seconds
Started Aug 01 05:24:31 PM PDT 24
Finished Aug 01 05:24:53 PM PDT 24
Peak memory 200808 kb
Host smart-a22ff695-a408-4302-86eb-6f69aab3bf34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633115106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.3633115106
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3741033935
Short name T215
Test name
Test status
Simulation time 221593070874 ps
CPU time 129.52 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:26:39 PM PDT 24
Peak memory 209424 kb
Host smart-5b53719c-4c89-4c38-ac18-5d1ebd0ec367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741033935 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.3741033935
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.182330828
Short name T609
Test name
Test status
Simulation time 5950911464 ps
CPU time 6.69 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:24:34 PM PDT 24
Peak memory 200792 kb
Host smart-0e3dc0d3-4c2d-419b-9388-f9a3fa97537e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182330828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ultra_low_pwr.182330828
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3412096641
Short name T555
Test name
Test status
Simulation time 24107454633 ps
CPU time 15.21 seconds
Started Aug 01 05:26:50 PM PDT 24
Finished Aug 01 05:27:05 PM PDT 24
Peak memory 201060 kb
Host smart-2a7f574c-e072-4f46-ab32-06f21f059fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412096641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.3412096641
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3408644436
Short name T287
Test name
Test status
Simulation time 28945675485 ps
CPU time 74.28 seconds
Started Aug 01 05:26:45 PM PDT 24
Finished Aug 01 05:27:59 PM PDT 24
Peak memory 201180 kb
Host smart-d1691625-89d4-4096-a8b8-74e34ffbb065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408644436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.3408644436
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.500371788
Short name T678
Test name
Test status
Simulation time 24579671277 ps
CPU time 59.57 seconds
Started Aug 01 05:26:42 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 201088 kb
Host smart-9a31ad87-6af1-493b-906d-d70fe2d3d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500371788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_wi
th_pre_cond.500371788
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2800718750
Short name T385
Test name
Test status
Simulation time 52381866518 ps
CPU time 128.58 seconds
Started Aug 01 05:26:43 PM PDT 24
Finished Aug 01 05:28:51 PM PDT 24
Peak memory 201152 kb
Host smart-e15f3a3b-2c74-47b6-8d01-5899256cdeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800718750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.2800718750
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2022349017
Short name T713
Test name
Test status
Simulation time 144966310738 ps
CPU time 88.61 seconds
Started Aug 01 05:26:44 PM PDT 24
Finished Aug 01 05:28:12 PM PDT 24
Peak memory 201140 kb
Host smart-cd221656-f5e2-4d41-8238-9ec8aef4464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022349017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.2022349017
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.554778017
Short name T363
Test name
Test status
Simulation time 87016244208 ps
CPU time 13.64 seconds
Started Aug 01 05:26:49 PM PDT 24
Finished Aug 01 05:27:03 PM PDT 24
Peak memory 201056 kb
Host smart-24a85c36-afdc-46d8-a49e-b63b939ab19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554778017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_wi
th_pre_cond.554778017
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.529474311
Short name T114
Test name
Test status
Simulation time 47343553097 ps
CPU time 31.42 seconds
Started Aug 01 05:26:49 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 201112 kb
Host smart-35d19fe8-89e3-4f67-9cbf-094a572111e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529474311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_wi
th_pre_cond.529474311
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2648132681
Short name T759
Test name
Test status
Simulation time 82766195301 ps
CPU time 56.46 seconds
Started Aug 01 05:26:43 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 200340 kb
Host smart-4702f808-2d50-43e2-825e-31cd06b4d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648132681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.2648132681
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.3936280395
Short name T89
Test name
Test status
Simulation time 2107783447 ps
CPU time 1.05 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:36 PM PDT 24
Peak memory 201044 kb
Host smart-83b0ea04-8a03-45ed-8511-0f0733d88e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936280395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.3936280395
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2232142573
Short name T240
Test name
Test status
Simulation time 3475073579 ps
CPU time 2.61 seconds
Started Aug 01 05:24:30 PM PDT 24
Finished Aug 01 05:24:33 PM PDT 24
Peak memory 200804 kb
Host smart-7d1fa58d-8fd4-4b0d-a8fb-0140d110ead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232142573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2232142573
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.2896890892
Short name T238
Test name
Test status
Simulation time 79608582894 ps
CPU time 212.38 seconds
Started Aug 01 05:24:20 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 201004 kb
Host smart-3783ddc7-2876-4865-af27-c21258fa5f5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896890892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.2896890892
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.4199226322
Short name T386
Test name
Test status
Simulation time 74554494276 ps
CPU time 94.89 seconds
Started Aug 01 05:24:20 PM PDT 24
Finished Aug 01 05:25:55 PM PDT 24
Peak memory 201168 kb
Host smart-d61cfac5-9e6a-4943-b919-d793c3c311b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199226322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.4199226322
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1601403345
Short name T149
Test name
Test status
Simulation time 3767842456 ps
CPU time 1.05 seconds
Started Aug 01 05:24:31 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 200760 kb
Host smart-638a000f-2f3f-450a-9350-97a61e2a8e70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601403345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1601403345
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.1395966163
Short name T174
Test name
Test status
Simulation time 5296560234 ps
CPU time 3.13 seconds
Started Aug 01 05:24:30 PM PDT 24
Finished Aug 01 05:24:34 PM PDT 24
Peak memory 200840 kb
Host smart-3b34fda6-4a6c-4d09-8a01-5f626d6c20bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395966163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.1395966163
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3798391738
Short name T677
Test name
Test status
Simulation time 2612581590 ps
CPU time 7.64 seconds
Started Aug 01 05:24:31 PM PDT 24
Finished Aug 01 05:24:39 PM PDT 24
Peak memory 200728 kb
Host smart-242fec69-2269-4830-a092-b8165434b87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798391738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3798391738
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2335186961
Short name T654
Test name
Test status
Simulation time 2475528493 ps
CPU time 2.37 seconds
Started Aug 01 05:24:29 PM PDT 24
Finished Aug 01 05:24:32 PM PDT 24
Peak memory 200740 kb
Host smart-8eb7b460-1cf6-488a-9720-ec900c10749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335186961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2335186961
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2261019889
Short name T273
Test name
Test status
Simulation time 2274236299 ps
CPU time 2.06 seconds
Started Aug 01 05:24:27 PM PDT 24
Finished Aug 01 05:24:29 PM PDT 24
Peak memory 200760 kb
Host smart-eecf1eee-9515-4802-855e-70b18873f052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261019889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.2261019889
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3790577225
Short name T688
Test name
Test status
Simulation time 2511114284 ps
CPU time 7.43 seconds
Started Aug 01 05:24:28 PM PDT 24
Finished Aug 01 05:24:36 PM PDT 24
Peak memory 200760 kb
Host smart-62d36513-e40e-4af4-b0b0-89d6a9349c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790577225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3790577225
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.1402573903
Short name T699
Test name
Test status
Simulation time 2136855646 ps
CPU time 1.98 seconds
Started Aug 01 05:24:28 PM PDT 24
Finished Aug 01 05:24:30 PM PDT 24
Peak memory 200676 kb
Host smart-e6e82702-7829-41d0-ac09-a6b72483249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402573903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1402573903
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.3042901554
Short name T772
Test name
Test status
Simulation time 208230660662 ps
CPU time 36.09 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:25:14 PM PDT 24
Peak memory 200792 kb
Host smart-ecfa8856-4a39-47dc-a1c6-46553dee257f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042901554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.3042901554
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1499401626
Short name T255
Test name
Test status
Simulation time 84187370519 ps
CPU time 45.63 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:25:24 PM PDT 24
Peak memory 217536 kb
Host smart-62461490-2a4b-4908-8132-d2ce21711b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499401626 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.1499401626
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.318831769
Short name T207
Test name
Test status
Simulation time 68130120034 ps
CPU time 54.54 seconds
Started Aug 01 05:26:47 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 201076 kb
Host smart-7bf49ac8-cd92-4822-99b9-0f66a6602e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318831769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_wi
th_pre_cond.318831769
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.98768860
Short name T295
Test name
Test status
Simulation time 87973021437 ps
CPU time 55.2 seconds
Started Aug 01 05:26:43 PM PDT 24
Finished Aug 01 05:27:38 PM PDT 24
Peak memory 201152 kb
Host smart-266a6db7-86b3-4ce7-971d-057d15cf5056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98768860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_wit
h_pre_cond.98768860
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3312388610
Short name T530
Test name
Test status
Simulation time 59219974444 ps
CPU time 144.38 seconds
Started Aug 01 05:26:52 PM PDT 24
Finished Aug 01 05:29:16 PM PDT 24
Peak memory 201092 kb
Host smart-29cd6144-34fe-4fc7-9c72-bf3c5d8a5c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312388610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.3312388610
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2837391573
Short name T278
Test name
Test status
Simulation time 57089503048 ps
CPU time 75.69 seconds
Started Aug 01 05:26:48 PM PDT 24
Finished Aug 01 05:28:04 PM PDT 24
Peak memory 200968 kb
Host smart-c203520f-0bda-4700-8721-d45e3d05324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837391573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.2837391573
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.3516970513
Short name T249
Test name
Test status
Simulation time 2021823999 ps
CPU time 3.41 seconds
Started Aug 01 05:24:37 PM PDT 24
Finished Aug 01 05:24:41 PM PDT 24
Peak memory 200788 kb
Host smart-9e06de51-1422-4dc5-a72e-c669cd9d7e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516970513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.3516970513
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.58764455
Short name T391
Test name
Test status
Simulation time 321923690758 ps
CPU time 199.95 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:27:59 PM PDT 24
Peak memory 200872 kb
Host smart-e9453a08-8548-4f44-a72d-a758db855d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58764455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.58764455
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3317862164
Short name T117
Test name
Test status
Simulation time 97168532466 ps
CPU time 133.84 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:26:50 PM PDT 24
Peak memory 201152 kb
Host smart-cf4fb2d1-839c-4e49-b0a8-56aadf249088
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317862164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3317862164
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2840765367
Short name T72
Test name
Test status
Simulation time 65741284882 ps
CPU time 166.81 seconds
Started Aug 01 05:24:41 PM PDT 24
Finished Aug 01 05:27:28 PM PDT 24
Peak memory 201112 kb
Host smart-271ba0cf-9071-4b6f-bb9d-8b2cdfc850c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840765367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.2840765367
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3187297309
Short name T636
Test name
Test status
Simulation time 3336612217 ps
CPU time 3.47 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:38 PM PDT 24
Peak memory 200796 kb
Host smart-2c4bd691-eef4-437d-a183-37de585ca962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187297309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3187297309
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3170474086
Short name T38
Test name
Test status
Simulation time 806959776248 ps
CPU time 475.01 seconds
Started Aug 01 05:24:34 PM PDT 24
Finished Aug 01 05:32:29 PM PDT 24
Peak memory 200808 kb
Host smart-8be80c04-828f-4da5-94ec-2789c6c35dd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170474086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3170474086
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.7903041
Short name T789
Test name
Test status
Simulation time 2644540355 ps
CPU time 1.9 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:40 PM PDT 24
Peak memory 200856 kb
Host smart-75679cf2-80f2-4511-b7ff-a71479f7f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7903041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.7903041
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3635870751
Short name T488
Test name
Test status
Simulation time 2469877487 ps
CPU time 6.64 seconds
Started Aug 01 05:24:39 PM PDT 24
Finished Aug 01 05:24:46 PM PDT 24
Peak memory 200836 kb
Host smart-59b0b404-868b-46df-b132-3f212a7d61ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635870751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3635870751
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2833119756
Short name T542
Test name
Test status
Simulation time 2268426429 ps
CPU time 2.11 seconds
Started Aug 01 05:24:36 PM PDT 24
Finished Aug 01 05:24:38 PM PDT 24
Peak memory 200856 kb
Host smart-ccdfdfaf-ab37-45d4-b181-33b4feb51e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833119756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2833119756
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.52645487
Short name T449
Test name
Test status
Simulation time 2523899928 ps
CPU time 2.36 seconds
Started Aug 01 05:24:33 PM PDT 24
Finished Aug 01 05:24:35 PM PDT 24
Peak memory 200812 kb
Host smart-8d5da9b7-cdb1-44d7-8369-58ff86726a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52645487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.52645487
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.204550059
Short name T498
Test name
Test status
Simulation time 2133152765 ps
CPU time 1.66 seconds
Started Aug 01 05:24:35 PM PDT 24
Finished Aug 01 05:24:38 PM PDT 24
Peak memory 200720 kb
Host smart-da51b09e-603b-4b89-8463-3b0caa2baa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204550059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.204550059
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.3447533178
Short name T586
Test name
Test status
Simulation time 6920601029 ps
CPU time 3.07 seconds
Started Aug 01 05:24:38 PM PDT 24
Finished Aug 01 05:24:41 PM PDT 24
Peak memory 200744 kb
Host smart-861ee72c-395d-48d2-a07c-9ca44e3affd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447533178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.3447533178
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1055229
Short name T326
Test name
Test status
Simulation time 62762160279 ps
CPU time 69.12 seconds
Started Aug 01 05:24:40 PM PDT 24
Finished Aug 01 05:25:49 PM PDT 24
Peak memory 213396 kb
Host smart-92b8ca0d-4cd8-44cb-9b3b-f20f55438c6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055229 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1055229
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.4229718046
Short name T3
Test name
Test status
Simulation time 53629281304 ps
CPU time 13.48 seconds
Started Aug 01 05:26:48 PM PDT 24
Finished Aug 01 05:27:01 PM PDT 24
Peak memory 201048 kb
Host smart-21ab1c64-1f92-4089-a277-a80be9c736f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229718046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.4229718046
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2459184531
Short name T661
Test name
Test status
Simulation time 31915770078 ps
CPU time 82.03 seconds
Started Aug 01 05:26:49 PM PDT 24
Finished Aug 01 05:28:11 PM PDT 24
Peak memory 201124 kb
Host smart-3fa57640-e426-4027-9e1e-0e4062b20f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459184531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.2459184531
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.664845758
Short name T591
Test name
Test status
Simulation time 70172800410 ps
CPU time 191.99 seconds
Started Aug 01 05:26:51 PM PDT 24
Finished Aug 01 05:30:03 PM PDT 24
Peak memory 201020 kb
Host smart-81e17acb-7770-46a6-8981-12e2bbbdc6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664845758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_wi
th_pre_cond.664845758
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2355667013
Short name T32
Test name
Test status
Simulation time 144217121439 ps
CPU time 177.07 seconds
Started Aug 01 05:26:51 PM PDT 24
Finished Aug 01 05:29:48 PM PDT 24
Peak memory 201100 kb
Host smart-4d4c8261-33bc-423a-a2ef-2190b9987b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355667013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.2355667013
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.991500585
Short name T539
Test name
Test status
Simulation time 30581715320 ps
CPU time 81.66 seconds
Started Aug 01 05:26:51 PM PDT 24
Finished Aug 01 05:28:12 PM PDT 24
Peak memory 201116 kb
Host smart-56289c62-e2ed-4a61-9895-2d15b4309364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991500585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_wi
th_pre_cond.991500585
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1627266202
Short name T361
Test name
Test status
Simulation time 103904045411 ps
CPU time 265.32 seconds
Started Aug 01 05:26:50 PM PDT 24
Finished Aug 01 05:31:16 PM PDT 24
Peak memory 201088 kb
Host smart-d799890c-5fe6-420c-af28-0b92572be334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627266202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.1627266202
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1193414265
Short name T383
Test name
Test status
Simulation time 85343734030 ps
CPU time 53.86 seconds
Started Aug 01 05:26:48 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 201084 kb
Host smart-6d67d55a-0207-4f28-a473-c5d42bd69307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193414265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1193414265
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.631197174
Short name T8
Test name
Test status
Simulation time 56660302339 ps
CPU time 138.83 seconds
Started Aug 01 05:26:45 PM PDT 24
Finished Aug 01 05:29:04 PM PDT 24
Peak memory 201056 kb
Host smart-f58b38d3-01e0-4c46-9bca-7c5cb7f72662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631197174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_wi
th_pre_cond.631197174
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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