Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2217

1

T1

4

T7

13

T8

29

auto[1]

515

1

T7

3

T8

3

T29

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2027

1

T1

3

T7

3

T8

25

auto[1]

705

1

T1

1

T7

13

T8

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2093

1

T1

1

T7

13

T8

32

auto[1]

639

1

T1

3

T7

3

T12

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2058

1

T7

14

T8

32

T9

10

auto[1]

674

1

T1

4

T7

2

T29

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2517

1

T1

4

T7

16

T8

32

auto[1]

215

1

T65

3

T73

2

T86

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2519

1

T1

4

T7

16

T8

29

auto[1]

213

1

T8

3

T12

5

T31

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2546

1

T1

4

T7

16

T8

29

auto[1]

186

1

T8

3

T29

2

T30

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2444

1

T1

4

T7

16

T8

25

auto[1]

288

1

T8

7

T12

1

T29

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2476

1

T1

4

T7

16

T8

22

auto[1]

256

1

T8

10

T12

1

T29

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2120

1

T1

4

T7

11

T8

32

auto[1]

612

1

T7

5

T32

9

T69

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	900	1			T1	4		T7	13		T9	10
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	93	1			T282	7		T318	5		T309	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	74	1			T29	6		T66	2		T282	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	15	1			T65	3		T315	7		T319	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	91	1			T29	3		T31	3		T66	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	50	1			T282	6		T224	4		T320	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	46	1			T8	7		T12	1		T321	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	59	1			T30	6		T65	6		T322	8
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	10	1			T73	1		T308	1		T76	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	28	1			T29	2		T31	3		T73	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	7	1			T86	3		T315	4		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T323	5		T324	9		T325	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T312	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T282	6		T315	2		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	68	1			T65	7		T88	13		T90	12
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	4	1			T322	1		T326	3		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	40	1			T68	2		T73	1		T90	8
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	2	1			T327	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	31	1			T109	6		T90	3		T312	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	10	1			T328	8		T329	2		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T31	2		T319	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	24	1			T66	2		T68	3		T330	4
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T331	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	7	1			T8	3		T31	3		T74	1
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T88	1		T332	2		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

72

1

T8

3

T31

3

T90

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

123

1

T32

9

T66

4

T304

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

51

1

T69

2

T65

6

T70

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

138

1

T31

3

T68

3

T73

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

57

1

T90

8

T322

8

T204

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

88

1

T73

1

T153

1

T326

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T102

2

T333

2

T81

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

80

1

T12

1

T104

9

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

65

1

T29

3

T31

2

T70

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

66

1

T85

6

T65

7

T118

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T69

1

T230

2

T70

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

107

1

T1

3

T85

9

T242

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T282

6

T81

2

T334

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T173

4

T216

4

T233

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T87

1

T153

1

T216

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

214

1

T7

11

T8

7

T9

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

49

1

T29

3

T42

1

T282

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T42

1

T242

6

T153

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T42

1

T109

7

T173

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T1

1

T29

2

T30

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T304

4

T305

6

T316

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T7

2

T304

5

T309

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T70

2

T92

2

T317

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

80

1

T29

3

T31

3

T104

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T32

2

T66

2

T232

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T304

4

T282

6

T335

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T230

2

T333

3

T81

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

19

1

T153

1

T92

3

T333

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T321

5

T98

2

T336

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T97

1

T234

1

T240

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T204

1

T81

1

T95

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded