Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T17

8

T46

13

T60

10

auto[1]

1207

1

T17

12

T46

7

T60

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

575

1

T17

3

T46

5

T60

7

from_0to1

570

1

T17

3

T46

5

T60

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T17

10

T46

8

T60

14

auto[1]

1202

1

T17

10

T46

12

T60

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1190

1

T17

7

T46

10

T60

8

auto[1]

1170

1

T17

13

T46

10

T60

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T61

1

T33

1

T39

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T60

2

T61

1

T100

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T17

1

T46

1

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T46

1

T61

1

T38

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T46

1

T61

2

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T46

1

T60

2

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T60

1

T61

1

T45

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T17

1

T46

1

T61

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T17

1

T46

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T17

1

T60

1

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

87

1

T33

2

T39

3

T45

4

auto[1]

from_1to0

auto[1]

auto[1]

83

1

T46

2

T60

2

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T17

1

T46

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T60

1

T38

1

T33

2

auto[1]

from_0to1

auto[1]

auto[0]

85

1

T46

1

T39

3

T45

4

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T17

1

T60

1

T38

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1202

1

T17

8

T46

9

T60

8

auto[1]

1158

1

T17

12

T46

11

T60

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

572

1

T17

5

T46

6

T60

5

from_0to1

577

1

T17

5

T46

5

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T17

12

T46

8

T60

9

auto[1]

1182

1

T17

8

T46

12

T60

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1187

1

T17

11

T46

8

T60

11

auto[1]

1173

1

T17

9

T46

12

T60

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T17

1

T46

1

T100

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T46

1

T61

1

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T46

2

T60

1

T100

1

auto[0]

from_1to0

auto[1]

auto[1]

82

1

T100

1

T33

1

T39

3

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T17

1

T60

1

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T60

1

T61

2

T33

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T60

1

T38

2

T39

4

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T17

1

T100

1

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T60

3

T33

3

T39

3

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T17

2

T46

1

T61

2

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T17

2

T38

1

T100

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T46

1

T60

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T17

1

T46

2

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T17

1

T46

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T17

1

T60

1

T38

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T46

2

T60

1

T38

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T17

12

T46

12

T60

10

auto[1]

1207

1

T17

8

T46

8

T60

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

571

1

T17

6

T46

5

T60

5

from_0to1

573

1

T17

5

T46

5

T60

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1181

1

T17

9

T46

8

T60

13

auto[1]

1179

1

T17

11

T46

12

T60

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1201

1

T17

7

T46

10

T60

12

auto[1]

1159

1

T17

13

T46

10

T60

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T46

2

T33

1

T39

2

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T17

1

T60

1

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T17

2

T60

1

T61

2

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T17

1

T46

2

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T46

1

T60

1

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T46

1

T60

1

T38

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T17

2

T46

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T33

4

T39

1

T45

5

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T46

1

T60

1

T61

2

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T17

2

T100

2

T33

3

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T100

2

T33

1

T39

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T60

1

T61

1

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T61

1

T38

1

T33

1

auto[1]

from_0to1

auto[0]

auto[1]

91

1

T17

3

T60

1

T61

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T60

1

T61

1

T100

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T46

2

T38

1

T100

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1222

1

T17

9

T46

11

T60

13

auto[1]

1138

1

T17

11

T46

9

T60

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

592

1

T17

5

T46

6

T60

6

from_0to1

587

1

T17

5

T46

6

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T17

5

T46

13

T60

13

auto[1]

1187

1

T17

15

T46

7

T60

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T17

6

T46

13

T60

8

auto[1]

1203

1

T17

14

T46

7

T60

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T46

1

T38

1

T100

1

auto[0]

from_1to0

auto[0]

auto[1]

89

1

T46

1

T60

3

T100

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T17

1

T38

2

T33

2

auto[0]

from_1to0

auto[1]

auto[1]

83

1

T17

1

T61

4

T100

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T46

2

T60

1

T61

2

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T17

2

T38

1

T39

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T60

1

T61

2

T38

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T46

1

T60

1

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

85

1

T46

1

T60

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T17

1

T46

2

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T17

1

T46

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T17

1

T60

1

T33

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T46

2

T60

1

T33

2

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T33

1

T39

1

T45

3

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T17

1

T46

1

T38

2

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T17

2

T60

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1171

1

T17

13

T46

9

T60

12

auto[1]

1189

1

T17

7

T46

11

T60

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

581

1

T17

6

T46

3

T60

4

from_0to1

577

1

T17

5

T46

3

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1201

1

T17

8

T46

14

T60

12

auto[1]

1159

1

T17

12

T46

6

T60

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T17

10

T46

12

T60

11

auto[1]

1230

1

T17

10

T46

8

T60

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T17

2

T60

2

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T33

2

T39

3

T275

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T17

2

T60

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T17

2

T46

1

T100

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T46

1

T39

1

T45

3

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T17

2

T46

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T46

1

T60

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T100

1

T33

3

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T46

1

T33

1

T39

4

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T60

1

T61

1

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T46

1

T61

2

T100

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T61

2

T100

1

T33

2

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T17

1

T61

2

T39

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T17

1

T60

2

T61

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T60

1

T38

1

T39

5

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T17

1

T61

1

T38

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T17

11

T46

8

T60

9

auto[1]

1202

1

T17

9

T46

12

T60

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

557

1

T17

5

T46

6

T60

6

from_0to1

559

1

T17

6

T46

5

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T17

9

T46

9

T60

10

auto[1]

1209

1

T17

11

T46

11

T60

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1145

1

T17

8

T46

6

T60

10

auto[1]

1215

1

T17

12

T46

14

T60

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T61

1

T38

1

T100

3

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T17

1

T38

1

T33

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T46

2

T61

1

T38

2

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T17

1

T46

1

T60

2

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T17

1

T38

1

T100

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T17

1

T46

1

T60

2

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T17

1

T60

1

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T17

2

T46

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T46

2

T60

2

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T46

1

T60

1

T100

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T17

2

T61

2

T38

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T17

1

T60

1

T39

3

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T46

1

T60

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T17

1

T46

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

84

1

T60

1

T61

1

T38

4

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T46

1

T33

1

T39

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T17

5

T46

9

T60

14

auto[1]

1240

1

T17

15

T46

11

T60

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T17

5

T46

5

T60

5

from_0to1

566

1

T17

5

T46

4

T60

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T17

10

T46

11

T60

10

auto[1]

1164

1

T17

10

T46

9

T60

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T17

6

T46

11

T60

11

auto[1]

1214

1

T17

14

T46

9

T60

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T38

1

T39

1

T45

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T46

2

T60

2

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T46

1

T61

2

T33

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T17

1

T61

1

T39

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T17

1

T46

1

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T17

1

T60

1

T38

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T60

1

T100

1

T33

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T61

3

T38

1

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T17

1

T60

2

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T17

1

T60

1

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T46

1

T38

1

T33

2

auto[1]

from_1to0

auto[1]

auto[1]

83

1

T17

2

T46

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T38

1

T100

1

T33

1

auto[1]

from_0to1

auto[0]

auto[1]

86

1

T17

2

T33

1

T39

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T46

2

T61

1

T38

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T17

1

T46

1

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T17

8

T46

7

T60

5

auto[1]

1208

1

T17

12

T46

13

T60

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

563

1

T17

5

T46

3

T60

5

from_0to1

560

1

T17

6

T46

2

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T17

11

T46

8

T60

10

auto[1]

1187

1

T17

9

T46

12

T60

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1212

1

T17

9

T46

11

T60

11

auto[1]

1148

1

T17

11

T46

9

T60

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

88

1

T33

2

T45

3

T275

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T60

2

T61

1

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T61

1

T39

2

T45

4

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T46

1

T33

2

T39

3

auto[0]

from_0to1

auto[0]

auto[0]

88

1

T17

1

T61

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T17

1

T46

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T60

1

T100

1

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T17

2

T60

1

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T17

2

T46

2

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T17

1

T100

3

T33

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T17

1

T60

2

T100

3

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T17

1

T38

1

T100

1

auto[1]

from_0to1

auto[0]

auto[0]

80

1

T17

1

T60

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T17

1

T61

1

T33

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T46

1

T60

1

T33

1

auto[1]

from_0to1

auto[1]

auto[1]

80

1

T60

1

T38

1

T33

2