Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121517

1

T4

19

T5

19

T1

367

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143909	1			T4	22		T5	22		T1	471
values[0x0]	67267	1			T4	12		T5	11		T1	135
values[0x1]	68329	1			T4	11		T5	11		T1	112

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151613

1

T4

24

T5

22

T1

444

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	992	1			T19	2		T46	2		T8	4
valid_sources[0x01]	1043	1			T4	2		T19	4		T7	3
valid_sources[0x02]	1903	1			T1	16		T19	3		T46	2
valid_sources[0x03]	1699	1			T1	2		T3	1		T19	5
valid_sources[0x04]	1110	1			T46	1		T7	1		T8	6
valid_sources[0x05]	927	1			T19	5		T46	1		T7	2
valid_sources[0x06]	1668	1			T4	2		T19	2		T8	7
valid_sources[0x07]	892	1			T19	4		T6	2		T46	3
valid_sources[0x08]	814	1			T4	1		T1	5		T19	3
valid_sources[0x09]	884	1			T19	6		T6	4		T8	5
valid_sources[0x0a]	785	1			T19	1		T6	1		T8	5
valid_sources[0x0b]	994	1			T1	2		T19	4		T46	1
valid_sources[0x0c]	1071	1			T14	1		T17	65		T19	8
valid_sources[0x0d]	880	1			T4	1		T1	1		T19	5
valid_sources[0x0e]	909	1			T1	4		T14	1		T19	6
valid_sources[0x0f]	1090	1			T19	2		T8	3		T29	10
valid_sources[0x10]	1194	1			T13	2		T14	1		T6	1
valid_sources[0x11]	1348	1			T19	4		T8	9		T32	10
valid_sources[0x12]	987	1			T14	1		T19	5		T8	8
valid_sources[0x13]	1352	1			T19	1		T7	4		T8	1
valid_sources[0x14]	815	1			T4	1		T14	1		T19	10
valid_sources[0x15]	861	1			T1	2		T19	7		T46	2
valid_sources[0x16]	1714	1			T4	1		T1	9		T19	4
valid_sources[0x17]	1370	1			T1	4		T19	2		T8	8
valid_sources[0x18]	893	1			T1	5		T14	1		T19	1
valid_sources[0x19]	951	1			T1	9		T19	5		T46	1
valid_sources[0x1a]	1027	1			T4	1		T1	1		T19	5
valid_sources[0x1b]	1047	1			T19	1		T6	1		T46	1
valid_sources[0x1c]	962	1			T1	4		T19	3		T46	4
valid_sources[0x1d]	862	1			T8	4		T32	3		T208	9
valid_sources[0x1e]	1008	1			T4	1		T19	4		T6	1
valid_sources[0x1f]	1925	1			T19	3		T46	2		T7	3
valid_sources[0x20]	988	1			T3	1		T19	6		T8	2
valid_sources[0x21]	1110	1			T19	3		T46	2		T8	5
valid_sources[0x22]	758	1			T19	1		T46	1		T7	3
valid_sources[0x23]	998	1			T1	1		T19	1		T8	2
valid_sources[0x24]	1054	1			T1	24		T19	2		T8	8
valid_sources[0x25]	1795	1			T1	6		T19	2		T8	1
valid_sources[0x26]	1191	1			T2	11		T19	2		T8	2
valid_sources[0x27]	1717	1			T19	3		T46	1		T8	2
valid_sources[0x28]	857	1			T1	5		T19	7		T8	4
valid_sources[0x29]	962	1			T19	3		T6	1		T8	5
valid_sources[0x2a]	1169	1			T4	1		T1	1		T19	2
valid_sources[0x2b]	1169	1			T3	1		T19	5		T7	12
valid_sources[0x2c]	890	1			T19	1		T7	11		T8	1
valid_sources[0x2d]	1033	1			T1	10		T19	6		T7	8
valid_sources[0x2e]	1349	1			T19	6		T8	4		T62	6
valid_sources[0x2f]	912	1			T1	2		T19	1		T8	3
valid_sources[0x30]	1131	1			T4	1		T19	1		T7	6
valid_sources[0x31]	990	1			T19	4		T6	3		T46	1
valid_sources[0x32]	1029	1			T19	2		T8	6		T60	2
valid_sources[0x33]	840	1			T3	2		T19	1		T8	4
valid_sources[0x34]	1243	1			T15	1		T19	2		T46	1
valid_sources[0x35]	873	1			T1	1		T19	4		T8	3
valid_sources[0x36]	863	1			T19	1		T6	1		T7	8
valid_sources[0x37]	825	1			T19	5		T6	1		T8	3
valid_sources[0x38]	929	1			T1	7		T19	3		T8	4
valid_sources[0x39]	1879	1			T1	2		T19	3		T6	3
valid_sources[0x3a]	1013	1			T19	4		T8	3		T60	1
valid_sources[0x3b]	981	1			T19	6		T8	5		T60	1
valid_sources[0x3c]	1234	1			T2	5		T19	2		T7	7
valid_sources[0x3d]	887	1			T1	7		T19	4		T6	1
valid_sources[0x3e]	1198	1			T19	1		T7	15		T8	4
valid_sources[0x3f]	1197	1			T19	1		T6	3		T7	8
valid_sources[0x40]	882	1			T1	3		T19	2		T7	12
valid_sources[0x41]	870	1			T19	1		T7	1		T8	4
valid_sources[0x42]	1280	1			T1	4		T19	3		T6	2
valid_sources[0x43]	923	1			T14	1		T19	9		T6	2
valid_sources[0x44]	1107	1			T19	3		T46	2		T8	9
valid_sources[0x45]	950	1			T19	4		T46	1		T7	3
valid_sources[0x46]	769	1			T1	3		T19	1		T46	3
valid_sources[0x47]	730	1			T1	7		T14	1		T19	3
valid_sources[0x48]	715	1			T19	2		T46	1		T8	9
valid_sources[0x49]	915	1			T1	17		T19	3		T8	4
valid_sources[0x4a]	769	1			T1	2		T7	4		T8	5
valid_sources[0x4b]	819	1			T19	2		T8	1		T62	2
valid_sources[0x4c]	1272	1			T1	1		T3	1		T14	2
valid_sources[0x4d]	1059	1			T19	3		T6	1		T7	3
valid_sources[0x4e]	801	1			T1	21		T19	4		T8	4
valid_sources[0x4f]	1086	1			T4	1		T1	15		T19	3
valid_sources[0x50]	848	1			T1	4		T19	7		T6	1
valid_sources[0x51]	877	1			T1	1		T2	1		T19	2
valid_sources[0x52]	880	1			T4	2		T14	1		T19	1
valid_sources[0x53]	934	1			T4	1		T1	5		T19	7
valid_sources[0x54]	1136	1			T3	1		T19	10		T8	3
valid_sources[0x55]	900	1			T1	2		T19	2		T6	1
valid_sources[0x56]	992	1			T4	2		T1	16		T19	3
valid_sources[0x57]	1012	1			T19	7		T6	2		T46	1
valid_sources[0x58]	1849	1			T4	1		T1	1		T19	5
valid_sources[0x59]	845	1			T19	1		T7	7		T8	5
valid_sources[0x5a]	954	1			T2	7		T18	45		T19	3
valid_sources[0x5b]	897	1			T14	3		T8	5		T10	6
valid_sources[0x5c]	829	1			T19	3		T6	1		T8	2
valid_sources[0x5d]	1015	1			T19	4		T8	8		T60	3
valid_sources[0x5e]	808	1			T19	7		T8	6		T12	1
valid_sources[0x5f]	998	1			T19	1		T46	2		T8	7
valid_sources[0x60]	1012	1			T19	2		T8	4		T12	3
valid_sources[0x61]	755	1			T1	3		T19	2		T8	3
valid_sources[0x62]	770	1			T1	8		T14	1		T8	1
valid_sources[0x63]	856	1			T19	4		T8	6		T60	2
valid_sources[0x64]	1235	1			T14	1		T19	6		T6	1
valid_sources[0x65]	970	1			T4	1		T1	4		T19	7
valid_sources[0x66]	937	1			T1	25		T19	1		T46	2
valid_sources[0x67]	1940	1			T1	9		T19	3		T8	4
valid_sources[0x68]	1735	1			T19	2		T6	1		T46	1
valid_sources[0x69]	868	1			T19	1		T8	8		T58	2
valid_sources[0x6a]	1029	1			T19	5		T6	1		T46	1
valid_sources[0x6b]	1153	1			T19	2		T8	6		T60	1
valid_sources[0x6c]	1308	1			T17	6		T19	6		T50	2
valid_sources[0x6d]	886	1			T1	3		T19	3		T46	2
valid_sources[0x6e]	1197	1			T1	9		T8	8		T32	1
valid_sources[0x6f]	924	1			T19	3		T6	1		T8	4
valid_sources[0x70]	1050	1			T19	1		T7	2		T8	1
valid_sources[0x71]	1002	1			T1	3		T19	3		T6	1
valid_sources[0x72]	798	1			T19	5		T6	1		T50	3
valid_sources[0x73]	970	1			T19	5		T46	2		T7	9
valid_sources[0x74]	956	1			T7	5		T8	5		T12	25
valid_sources[0x75]	1930	1			T4	1		T19	3		T7	4
valid_sources[0x76]	826	1			T19	4		T8	4		T12	5
valid_sources[0x77]	1735	1			T4	1		T19	1		T8	5
valid_sources[0x78]	967	1			T14	2		T19	2		T46	2
valid_sources[0x79]	891	1			T19	3		T8	1		T53	1
valid_sources[0x7a]	893	1			T1	4		T19	3		T6	1
valid_sources[0x7b]	1106	1			T19	3		T8	11		T62	8
valid_sources[0x7c]	1392	1			T4	1		T1	4		T19	1
valid_sources[0x7d]	896	1			T19	1		T6	1		T8	7
valid_sources[0x7e]	1069	1			T1	1		T19	5		T6	1
valid_sources[0x7f]	1086	1			T19	4		T8	3		T60	1
valid_sources[0x80]	774	1			T19	2		T6	1		T47	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65506

1

T4

11

T5

11

T1

253

values[0x0]

all_enables

biggest_size

32701

1

T4

6

T5

5

T1

75

values[0x1]

all_enables

biggest_size

23310

1

T4

2

T5

3

T1

39