Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T24,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T16,T24,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T24,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T24,T36
1	0	Covered	T4,T5,T1
1	1	Covered	T16,T24,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T24,T36
0	1	Covered	T75,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T24,T36
0	1	Covered	T16,T24,T36
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T24,T36
1	-	Covered	T16,T24,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T24,T36
DetectSt	168	Covered	T16,T24,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T16,T24,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T24,T36
DebounceSt->IdleSt	163	Covered	T16,T42,T43
DetectSt->IdleSt	186	Covered	T75,T95,T117
DetectSt->StableSt	191	Covered	T16,T24,T36
IdleSt->DebounceSt	148	Covered	T16,T24,T36
StableSt->IdleSt	206	Covered	T16,T24,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T24,T36
0	1	Covered	T16,T24,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T24,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T24,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T24,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T43,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T24,T36
DetectSt	-	-	-	-	1	-	-	Covered	T75,T95
DetectSt	-	-	-	-	0	1	-	Covered	T16,T24,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T24,T36
StableSt	-	-	-	-	-	-	0	Covered	T16,T24,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	268	0	0
CntIncr_A	7650645	162250	0	0
CntNoWrap_A	7650645	6984713	0	0
DetectStDropOut_A	7650645	2	0	0
DetectedOut_A	7650645	820	0	0
DetectedPulseOut_A	7650645	122	0	0
DisabledIdleSt_A	7650645	6816396	0	0
DisabledNoDetection_A	7650645	6818794	0	0
EnterDebounceSt_A	7650645	150	0	0
EnterDetectSt_A	7650645	124	0	0
EnterStableSt_A	7650645	122	0	0
PulseIsPulse_A	7650645	122	0	0
StayInStableSt	7650645	698	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	7021	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	268	0	0
T6	2309	0	0	0
T16	674	3	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	4	0	0
T36	0	6	0	0
T41	0	4	0	0
T42	0	4	0	0
T43	0	3	0	0
T44	0	2	0	0
T45	0	6	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	3	0	0
T84	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	162250	0	0
T6	2309	0	0	0
T16	674	86	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	103	0	0
T36	0	26091	0	0
T41	0	45	0	0
T42	0	2016	0	0
T43	0	89	0	0
T44	0	10	0	0
T45	0	104	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	103	0	0
T84	0	135	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984713	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	270	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2	0	0
T34	617	0	0	0
T75	630	1	0	0
T77	198403	0	0	0
T95	0	1	0	0
T105	404	0	0	0
T106	524	0	0	0
T107	737	0	0	0
T108	44647	0	0	0
T109	17658	0	0	0
T110	545	0	0	0
T111	501	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	820	0	0
T6	2309	0	0	0
T16	674	4	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	16	0	0
T36	0	26	0	0
T41	0	15	0	0
T42	0	14	0	0
T43	0	11	0	0
T44	0	2	0	0
T45	0	22	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	4	0	0
T84	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	122	0	0
T6	2309	0	0	0
T16	674	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	2	0	0
T36	0	3	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	1	0	0
T84	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6816396	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	104	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6818794	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	104	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	150	0	0
T6	2309	0	0	0
T16	674	2	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	2	0	0
T36	0	3	0	0
T41	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	2	0	0
T84	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	124	0	0
T6	2309	0	0	0
T16	674	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	2	0	0
T36	0	3	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	1	0	0
T84	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	122	0	0
T6	2309	0	0	0
T16	674	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	2	0	0
T36	0	3	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	1	0	0
T84	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	122	0	0
T6	2309	0	0	0
T16	674	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	2	0	0
T36	0	3	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	1	0	0
T84	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	698	0	0
T6	2309	0	0	0
T16	674	3	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	14	0	0
T36	0	23	0	0
T41	0	13	0	0
T42	0	12	0	0
T43	0	10	0	0
T44	0	1	0	0
T45	0	19	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	3	0	0
T84	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	7021	0	0
T1	17251	44	0	0
T2	1263	5	0	0
T3	681	2	0	0
T4	495	7	0	0
T5	498	9	0	0
T13	8419	0	0	0
T14	439	5	0	0
T15	422	3	0	0
T16	674	3	0	0
T17	502	5	0	0
T18	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	121	0	0
T6	2309	0	0	0
T16	674	1	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T24	702	2	0	0
T36	0	3	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T83	0	1	0	0
T84	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T2,T45,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Unreachable
1	0	Covered	T1,T3,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T77,T80,T51
DetectSt->IdleSt	186	Covered	T2,T45,T81
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T80,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T45,T81
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	177	0	0
CntIncr_A	7650645	5614	0	0
CntNoWrap_A	7650645	6984804	0	0
DetectStDropOut_A	7650645	19	0	0
DetectedOut_A	7650645	8768	0	0
DetectedPulseOut_A	7650645	52	0	0
DisabledIdleSt_A	7650645	6208236	0	0
DisabledNoDetection_A	7650645	6210680	0	0
EnterDebounceSt_A	7650645	106	0	0
EnterDetectSt_A	7650645	71	0	0
EnterStableSt_A	7650645	52	0	0
PulseIsPulse_A	7650645	52	0	0
StayInStableSt	7650645	8716	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	7021	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_sticky_sva.StableStDropOut_A	7650645	753573	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	177	0	0
T1	17251	2	0	0
T2	1263	2	0	0
T3	681	2	0	0
T11	0	2	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	6	0	0
T43	0	2	0	0
T45	0	6	0	0
T52	0	2	0	0
T70	0	2	0	0
T71	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	5614	0	0
T1	17251	41	0	0
T2	1263	25	0	0
T3	681	39	0	0
T11	0	62	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	118	0	0
T43	0	16	0	0
T45	0	111	0	0
T52	0	90	0	0
T70	0	61	0	0
T71	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984804	0	0
T1	17251	11168	0	0
T2	1263	860	0	0
T3	681	278	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	19	0	0
T2	1263	1	0	0
T3	681	0	0	0
T6	2309	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T45	0	2	0	0
T81	0	4	0	0
T95	0	1	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	3	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	8768	0	0
T1	17251	188	0	0
T2	1263	0	0	0
T3	681	60	0	0
T11	0	272	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	308	0	0
T43	0	68	0	0
T45	0	1	0	0
T52	0	343	0	0
T70	0	72	0	0
T71	0	146	0	0
T112	0	155	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	52	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	1	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6208236	0	0
T1	17251	10768	0	0
T2	1263	683	0	0
T3	681	28	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6210680	0	0
T1	17251	10787	0	0
T2	1263	684	0	0
T3	681	29	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	106	0	0
T1	17251	1	0	0
T2	1263	1	0	0
T3	681	1	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	71	0	0
T1	17251	1	0	0
T2	1263	1	0	0
T3	681	1	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	52	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	1	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	52	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	1	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	8716	0	0
T1	17251	187	0	0
T2	1263	0	0	0
T3	681	59	0	0
T11	0	271	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	305	0	0
T43	0	67	0	0
T52	0	342	0	0
T70	0	71	0	0
T71	0	144	0	0
T112	0	154	0	0
T124	0	184	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	7021	0	0
T1	17251	44	0	0
T2	1263	5	0	0
T3	681	2	0	0
T4	495	7	0	0
T5	498	9	0	0
T13	8419	0	0	0
T14	439	5	0	0
T15	422	3	0	0
T16	674	3	0	0
T17	502	5	0	0
T18	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	753573	0	0
T1	17251	149	0	0
T2	1263	0	0	0
T3	681	130	0	0
T11	0	275	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	211628	0	0
T43	0	357	0	0
T45	0	29	0	0
T52	0	78	0	0
T70	0	36	0	0
T71	0	1219	0	0
T112	0	84	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T1,T45,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Unreachable
1	0	Covered	T1,T2,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T2,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T11
DebounceSt->IdleSt	163	Covered	T1,T3,T33
DetectSt->IdleSt	186	Covered	T1,T45,T80
DetectSt->StableSt	191	Covered	T1,T2,T11
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T1,T45,T80
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	174	0	0
CntIncr_A	7650645	25873	0	0
CntNoWrap_A	7650645	6984807	0	0
DetectStDropOut_A	7650645	18	0	0
DetectedOut_A	7650645	82356	0	0
DetectedPulseOut_A	7650645	50	0	0
DisabledIdleSt_A	7650645	6208236	0	0
DisabledNoDetection_A	7650645	6210680	0	0
EnterDebounceSt_A	7650645	106	0	0
EnterDetectSt_A	7650645	68	0	0
EnterStableSt_A	7650645	50	0	0
PulseIsPulse_A	7650645	50	0	0
StayInStableSt	7650645	82306	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_sticky_sva.StableStDropOut_A	7650645	219005	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	174	0	0
T1	17251	5	0	0
T2	1263	2	0	0
T3	681	2	0	0
T11	0	2	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	5	0	0
T43	0	2	0	0
T45	0	6	0	0
T52	0	2	0	0
T70	0	3	0	0
T71	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	25873	0	0
T1	17251	162	0	0
T2	1263	82	0	0
T3	681	164	0	0
T11	0	14	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	155	0	0
T43	0	78	0	0
T45	0	144	0	0
T52	0	47	0	0
T70	0	56	0	0
T71	0	176	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984807	0	0
T1	17251	11165	0	0
T2	1263	860	0	0
T3	681	278	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	18	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T45	0	3	0	0
T80	0	4	0	0
T118	0	2	0	0
T123	0	1	0	0
T125	0	2	0	0
T126	0	1	0	0
T127	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	82356	0	0
T1	17251	1	0	0
T2	1263	58	0	0
T3	681	0	0	0
T11	0	79	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	495	0	0
T43	0	283	0	0
T52	0	146	0	0
T70	0	1	0	0
T71	0	829	0	0
T77	0	39	0	0
T112	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	50	0	0
T1	17251	1	0	0
T2	1263	1	0	0
T3	681	0	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	2	0	0
T43	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6208236	0	0
T1	17251	10768	0	0
T2	1263	683	0	0
T3	681	28	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6210680	0	0
T1	17251	10787	0	0
T2	1263	684	0	0
T3	681	29	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	106	0	0
T1	17251	3	0	0
T2	1263	1	0	0
T3	681	2	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	3	0	0
T52	0	1	0	0
T70	0	2	0	0
T71	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	68	0	0
T1	17251	2	0	0
T2	1263	1	0	0
T3	681	0	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	2	0	0
T43	0	1	0	0
T45	0	3	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	50	0	0
T1	17251	1	0	0
T2	1263	1	0	0
T3	681	0	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	2	0	0
T43	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	50	0	0
T1	17251	1	0	0
T2	1263	1	0	0
T3	681	0	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	2	0	0
T43	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	82306	0	0
T2	1263	57	0	0
T3	681	0	0	0
T6	2309	0	0	0
T11	0	78	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	493	0	0
T43	0	282	0	0
T52	0	145	0	0
T71	0	827	0	0
T77	0	38	0	0
T112	0	107	0	0
T114	0	216	0	0
T128	0	267	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	219005	0	0
T1	17251	70	0	0
T2	1263	28	0	0
T3	681	0	0	0
T11	0	519	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	211273	0	0
T43	0	80	0	0
T52	0	311	0	0
T70	0	60	0	0
T71	0	400	0	0
T77	0	33	0	0
T112	0	158	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T11,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T52,T33
0	1	Covered	T2,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T52,T33
0	1	Unreachable
1	0	Covered	T11,T52,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T2,T11,T52
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T52,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T11,T52
DebounceSt->IdleSt	163	Covered	T1,T3,T80
DetectSt->IdleSt	186	Covered	T2,T77,T78
DetectSt->StableSt	191	Covered	T11,T52,T33
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T11,T52,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T52
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T11,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T77,T78
DetectSt	-	-	-	-	0	1	-	Covered	T11,T52,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T52,T33
StableSt	-	-	-	-	-	-	0	Covered	T11,T52,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	149	0	0
CntIncr_A	7650645	106226	0	0
CntNoWrap_A	7650645	6984832	0	0
DetectStDropOut_A	7650645	4	0	0
DetectedOut_A	7650645	563468	0	0
DetectedPulseOut_A	7650645	49	0	0
DisabledIdleSt_A	7650645	6208236	0	0
DisabledNoDetection_A	7650645	6210680	0	0
EnterDebounceSt_A	7650645	96	0	0
EnterDetectSt_A	7650645	53	0	0
EnterStableSt_A	7650645	49	0	0
PulseIsPulse_A	7650645	49	0	0
StayInStableSt	7650645	563419	0	0
gen_high_event_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_sticky_sva.StableStDropOut_A	7650645	102263	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	149	0	0
T1	17251	3	0	0
T2	1263	2	0	0
T3	681	2	0	0
T11	0	2	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	6	0	0
T43	0	2	0	0
T45	0	2	0	0
T52	0	2	0	0
T70	0	2	0	0
T71	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	106226	0	0
T1	17251	177	0	0
T2	1263	57	0	0
T3	681	36	0	0
T11	0	80	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	33201	0	0
T43	0	19	0	0
T45	0	24	0	0
T52	0	25	0	0
T70	0	10	0	0
T71	0	172	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984832	0	0
T1	17251	11167	0	0
T2	1263	860	0	0
T3	681	278	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	4	0	0
T2	1263	1	0	0
T3	681	0	0	0
T6	2309	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T129	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	563468	0	0
T11	1698	503	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	178574	0	0
T40	466	0	0	0
T43	0	76	0	0
T45	0	115	0	0
T52	1775	68	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	17	0	0
T71	0	1146	0	0
T112	0	150	0	0
T113	0	89	0	0
T114	0	108	0	0
T115	404	0	0	0
T116	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	49	0	0
T11	1698	1	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	3	0	0
T40	466	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	1775	1	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6208236	0	0
T1	17251	10768	0	0
T2	1263	683	0	0
T3	681	28	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6210680	0	0
T1	17251	10787	0	0
T2	1263	684	0	0
T3	681	29	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	96	0	0
T1	17251	3	0	0
T2	1263	1	0	0
T3	681	2	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	53	0	0
T2	1263	1	0	0
T3	681	0	0	0
T6	2309	0	0	0
T11	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T77	0	1	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	49	0	0
T11	1698	1	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	3	0	0
T40	466	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	1775	1	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	49	0	0
T11	1698	1	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	3	0	0
T40	466	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	1775	1	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	563419	0	0
T11	1698	502	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	178571	0	0
T40	466	0	0	0
T43	0	75	0	0
T45	0	114	0	0
T52	1775	67	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	16	0	0
T71	0	1144	0	0
T112	0	149	0	0
T113	0	88	0	0
T114	0	107	0	0
T115	404	0	0	0
T116	421	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	102263	0	0
T11	1698	44	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	290	0	0
T40	466	0	0	0
T43	0	361	0	0
T45	0	91	0	0
T52	1775	424	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	150	0	0
T71	0	97	0	0
T112	0	104	0	0
T113	0	178	0	0
T114	0	384	0	0
T115	404	0	0	0
T116	421	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T23,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T36
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T23,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T36
0	1	Covered	T130
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T36
0	1	Covered	T23,T36,T33
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T23,T36
1	-	Covered	T23,T36,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T23,T36
DetectSt	168	Covered	T1,T23,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T23,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T23,T36
DebounceSt->IdleSt	163	Covered	T33,T131,T132
DetectSt->IdleSt	186	Covered	T130
DetectSt->StableSt	191	Covered	T1,T23,T36
IdleSt->DebounceSt	148	Covered	T1,T23,T36
StableSt->IdleSt	206	Covered	T1,T23,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T23,T36
0	1	Covered	T1,T23,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T23,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T23,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T23,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T132
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T23,T36
DetectSt	-	-	-	-	1	-	-	Covered	T130
DetectSt	-	-	-	-	0	1	-	Covered	T1,T23,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T36,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T23,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	85	0	0
CntIncr_A	7650645	2433	0	0
CntNoWrap_A	7650645	6984896	0	0
DetectStDropOut_A	7650645	1	0	0
DetectedOut_A	7650645	2708	0	0
DetectedPulseOut_A	7650645	40	0	0
DisabledIdleSt_A	7650645	6858559	0	0
DisabledNoDetection_A	7650645	6860937	0	0
EnterDebounceSt_A	7650645	45	0	0
EnterDetectSt_A	7650645	41	0	0
EnterStableSt_A	7650645	40	0	0
PulseIsPulse_A	7650645	40	0	0
StayInStableSt	7650645	2649	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	85	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	5	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T45	0	2	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2433	0	0
T1	17251	36	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	57	0	0
T33	0	188	0	0
T35	0	36	0	0
T36	0	168	0	0
T37	0	61	0	0
T45	0	92	0	0
T133	0	43	0	0
T134	0	91	0	0
T135	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984896	0	0
T1	17251	11168	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1	0	0
T130	5764	1	0	0
T136	641	0	0	0
T137	9685	0	0	0
T138	422	0	0	0
T139	423	0	0	0
T140	694	0	0	0
T141	6039	0	0	0
T142	508	0	0	0
T143	762	0	0	0
T144	800	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2708	0	0
T1	17251	204	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	137	0	0
T33	0	159	0	0
T35	0	74	0	0
T36	0	83	0	0
T37	0	44	0	0
T45	0	131	0	0
T133	0	177	0	0
T134	0	43	0	0
T135	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	40	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T45	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6858559	0	0
T1	17251	10791	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6860937	0	0
T1	17251	10809	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	45	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	3	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T45	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	41	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T45	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	40	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T45	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	40	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T45	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2649	0	0
T1	17251	202	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	136	0	0
T33	0	156	0	0
T35	0	72	0	0
T36	0	81	0	0
T37	0	42	0	0
T45	0	129	0	0
T133	0	175	0	0
T134	0	42	0	0
T135	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	20	0	0
T23	933	1	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T134	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T23,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T23
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T23,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T38
0	1	Covered	T23,T122
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T38
0	1	Covered	T1,T33,T45
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T23,T38
1	-	Covered	T1,T33,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T23,T38
DetectSt	168	Covered	T1,T23,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T23,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T23,T38
DebounceSt->IdleSt	163	Covered	T134,T145,T147
DetectSt->IdleSt	186	Covered	T23,T122
DetectSt->StableSt	191	Covered	T1,T23,T38
IdleSt->DebounceSt	148	Covered	T1,T23,T38
StableSt->IdleSt	206	Covered	T1,T38,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T23,T38
0	1	Covered	T1,T23,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T23,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T23,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T23,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T134,T145,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T23,T38
DetectSt	-	-	-	-	1	-	-	Covered	T23,T122
DetectSt	-	-	-	-	0	1	-	Covered	T1,T23,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T33,T45
StableSt	-	-	-	-	-	-	0	Covered	T1,T23,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	146	0	0
CntIncr_A	7650645	72782	0	0
CntNoWrap_A	7650645	6984835	0	0
DetectStDropOut_A	7650645	2	0	0
DetectedOut_A	7650645	27154	0	0
DetectedPulseOut_A	7650645	66	0	0
DisabledIdleSt_A	7650645	6752453	0	0
DisabledNoDetection_A	7650645	6754839	0	0
EnterDebounceSt_A	7650645	79	0	0
EnterDetectSt_A	7650645	68	0	0
EnterStableSt_A	7650645	66	0	0
PulseIsPulse_A	7650645	66	0	0
StayInStableSt	7650645	27054	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	2701	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	146	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	4	0	0
T33	0	10	0	0
T38	0	2	0	0
T39	0	2	0	0
T45	0	4	0	0
T70	0	4	0	0
T133	0	2	0	0
T134	0	3	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	72782	0	0
T1	17251	36	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	114	0	0
T33	0	304	0	0
T38	0	77	0	0
T39	0	51	0	0
T45	0	110	0	0
T70	0	162	0	0
T133	0	43	0	0
T134	0	182	0	0
T151	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984835	0	0
T1	17251	11168	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2	0	0
T23	933	1	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T122	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	27154	0	0
T1	17251	83	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	214	0	0
T33	0	339	0	0
T38	0	129	0	0
T39	0	251	0	0
T45	0	154	0	0
T70	0	321	0	0
T133	0	84	0	0
T134	0	121	0	0
T151	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	66	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	2	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6752453	0	0
T1	17251	10791	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6754839	0	0
T1	17251	10809	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	79	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	2	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	68	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	2	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	66	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	2	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	66	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	2	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	27054	0	0
T1	17251	82	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	212	0	0
T33	0	332	0	0
T38	0	127	0	0
T39	0	249	0	0
T45	0	151	0	0
T70	0	318	0	0
T133	0	83	0	0
T134	0	119	0	0
T151	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2701	0	0
T1	17251	28	0	0
T2	1263	0	0	0
T3	681	0	0	0
T4	495	5	0	0
T5	498	5	0	0
T6	0	12	0	0
T13	8419	0	0	0
T14	439	3	0	0
T15	422	4	0	0
T16	674	0	0	0
T17	502	4	0	0
T18	0	8	0	0
T46	0	6	0	0
T48	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	31	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	3	0	0
T35	0	1	0	0
T45	0	1	0	0
T70	0	1	0	0
T81	0	1	0	0
T133	0	1	0	0
T135	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0