Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T23,T37,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T23,T37,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T23,T37,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T23,T37
1	0	Covered	T4,T5,T1
1	1	Covered	T23,T37,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T37,T39
0	1	Covered	T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T37,T39
0	1	Covered	T23,T133,T35
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T37,T39
1	-	Covered	T23,T133,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T37,T39
DetectSt	168	Covered	T23,T37,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T23,T37,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T37,T39
DebounceSt->IdleSt	163	Covered	T72
DetectSt->IdleSt	186	Covered	T152
DetectSt->StableSt	191	Covered	T23,T37,T39
IdleSt->DebounceSt	148	Covered	T23,T37,T39
StableSt->IdleSt	206	Covered	T23,T39,T133

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T37,T39
0	1	Covered	T23,T37,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T37,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T37,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T37,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T37,T39
DetectSt	-	-	-	-	1	-	-	Covered	T152
DetectSt	-	-	-	-	0	1	-	Covered	T23,T37,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T133,T35
StableSt	-	-	-	-	-	-	0	Covered	T23,T37,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	65	0	0
CntIncr_A	7650645	17576	0	0
CntNoWrap_A	7650645	6984916	0	0
DetectStDropOut_A	7650645	1	0	0
DetectedOut_A	7650645	2111	0	0
DetectedPulseOut_A	7650645	31	0	0
DisabledIdleSt_A	7650645	6863403	0	0
DisabledNoDetection_A	7650645	6865806	0	0
EnterDebounceSt_A	7650645	33	0	0
EnterDetectSt_A	7650645	32	0	0
EnterStableSt_A	7650645	31	0	0
PulseIsPulse_A	7650645	31	0	0
StayInStableSt	7650645	2062	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	65	0	0
T23	933	4	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	8	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	466	0	0	0
T51	0	2	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	4	0	0
T135	0	4	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	17576	0	0
T23	933	114	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	194	0	0
T37	0	61	0	0
T39	0	51	0	0
T40	466	0	0	0
T51	0	21	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	86	0	0
T135	0	130	0	0
T153	0	60	0	0
T154	0	83	0	0
T155	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984916	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1	0	0
T93	36467	0	0	0
T152	646	1	0	0
T156	522	0	0	0
T157	491	0	0	0
T158	35596	0	0	0
T159	406	0	0	0
T160	422	0	0	0
T161	4866	0	0	0
T162	402	0	0	0
T163	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2111	0	0
T23	933	154	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	158	0	0
T37	0	129	0	0
T39	0	188	0	0
T40	466	0	0	0
T51	0	7	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	84	0	0
T135	0	87	0	0
T153	0	250	0	0
T154	0	37	0	0
T155	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	31	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	4	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	466	0	0	0
T51	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6863403	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6865806	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	33	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	4	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	466	0	0	0
T51	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	32	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	4	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	466	0	0	0
T51	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	31	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	4	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	466	0	0	0
T51	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	31	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	4	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	466	0	0	0
T51	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2062	0	0
T23	933	151	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	152	0	0
T37	0	127	0	0
T39	0	186	0	0
T40	466	0	0	0
T51	0	6	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	81	0	0
T135	0	85	0	0
T153	0	248	0	0
T154	0	35	0	0
T155	0	46	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	12	0	0
T23	933	1	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	2	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T23,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T23,T33,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T23
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T23,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T33,T37
0	1	Covered	T35,T169,T130
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T33,T37
0	1	Covered	T23,T33,T37
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T33,T37
1	-	Covered	T23,T33,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T23,T33
DetectSt	168	Covered	T23,T33,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T23,T33,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T33,T37
DebounceSt->IdleSt	163	Covered	T1,T133,T35
DetectSt->IdleSt	186	Covered	T35,T169,T130
DetectSt->StableSt	191	Covered	T23,T33,T37
IdleSt->DebounceSt	148	Covered	T1,T23,T33
StableSt->IdleSt	206	Covered	T23,T33,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T23,T33
0	1	Covered	T1,T23,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T33,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T23,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T33,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T133,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T23,T33
DetectSt	-	-	-	-	1	-	-	Covered	T35,T169,T130
DetectSt	-	-	-	-	0	1	-	Covered	T23,T33,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T33,T37
StableSt	-	-	-	-	-	-	0	Covered	T23,T33,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	131	0	0
CntIncr_A	7650645	141886	0	0
CntNoWrap_A	7650645	6984850	0	0
DetectStDropOut_A	7650645	3	0	0
DetectedOut_A	7650645	209280	0	0
DetectedPulseOut_A	7650645	59	0	0
DisabledIdleSt_A	7650645	6413311	0	0
DisabledNoDetection_A	7650645	6415698	0	0
EnterDebounceSt_A	7650645	69	0	0
EnterDetectSt_A	7650645	62	0	0
EnterStableSt_A	7650645	59	0	0
PulseIsPulse_A	7650645	59	0	0
StayInStableSt	7650645	209200	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	3062	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	131	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	4	0	0
T33	0	6	0	0
T34	0	4	0	0
T35	0	5	0	0
T37	0	2	0	0
T70	0	2	0	0
T108	0	2	0	0
T133	0	3	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	141886	0	0
T1	17251	36	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	114	0	0
T33	0	214	0	0
T34	0	60	0	0
T35	0	116	0	0
T37	0	61	0	0
T70	0	81	0	0
T108	0	30267	0	0
T133	0	86	0	0
T151	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984850	0	0
T1	17251	11169	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3	0	0
T35	205975	1	0	0
T80	812	0	0	0
T89	5216	0	0	0
T90	42811	0	0	0
T130	0	1	0	0
T169	0	1	0	0
T170	540	0	0	0
T171	427	0	0	0
T172	450	0	0	0
T173	29972	0	0	0
T174	501	0	0	0
T175	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	209280	0	0
T23	933	80	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	285	0	0
T34	0	87	0	0
T35	0	37	0	0
T37	0	39	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	48	0	0
T108	0	13971	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	90	0	0
T135	0	214	0	0
T151	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	59	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T108	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	1	0	0
T135	0	3	0	0
T151	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6413311	0	0
T1	17251	10791	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6415698	0	0
T1	17251	10809	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	69	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	3	0	0
T37	0	1	0	0
T70	0	1	0	0
T108	0	1	0	0
T133	0	2	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	62	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	1	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T108	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	1	0	0
T135	0	3	0	0
T151	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	59	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T108	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	1	0	0
T135	0	3	0	0
T151	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	59	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T108	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	1	0	0
T135	0	3	0	0
T151	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	209200	0	0
T23	933	78	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	281	0	0
T34	0	84	0	0
T35	0	35	0	0
T37	0	38	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	47	0	0
T108	0	13969	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	89	0	0
T135	0	210	0	0
T151	0	82	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3062	0	0
T1	17251	23	0	0
T2	1263	0	0	0
T3	681	0	0	0
T4	495	6	0	0
T5	498	3	0	0
T6	0	11	0	0
T13	8419	0	0	0
T14	439	3	0	0
T15	422	3	0	0
T16	674	0	0	0
T17	502	4	0	0
T18	0	5	0	0
T46	0	5	0	0
T47	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	37	0	0
T23	933	2	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T151	0	1	0	0
T155	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T23,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T36
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T23,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T36
0	1	Covered	T23,T177,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T36
0	1	Covered	T1,T36,T38
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T23,T36
1	-	Covered	T1,T36,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T23,T36
DetectSt	168	Covered	T1,T23,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T23,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T23,T36
DebounceSt->IdleSt	163	Covered	T45,T79,T133
DetectSt->IdleSt	186	Covered	T23,T177,T96
DetectSt->StableSt	191	Covered	T1,T23,T36
IdleSt->DebounceSt	148	Covered	T1,T23,T36
StableSt->IdleSt	206	Covered	T1,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T23,T36
0	1	Covered	T1,T23,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T23,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T23,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T23,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T79,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T23,T36
DetectSt	-	-	-	-	1	-	-	Covered	T23,T177,T96
DetectSt	-	-	-	-	0	1	-	Covered	T1,T23,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T36,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T23,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	157	0	0
CntIncr_A	7650645	76447	0	0
CntNoWrap_A	7650645	6984824	0	0
DetectStDropOut_A	7650645	5	0	0
DetectedOut_A	7650645	21297	0	0
DetectedPulseOut_A	7650645	70	0	0
DisabledIdleSt_A	7650645	6827733	0	0
DisabledNoDetection_A	7650645	6830119	0	0
EnterDebounceSt_A	7650645	82	0	0
EnterDetectSt_A	7650645	75	0	0
EnterStableSt_A	7650645	70	0	0
PulseIsPulse_A	7650645	70	0	0
StayInStableSt	7650645	21202	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	157	0	0
T1	17251	4	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	4	0	0
T33	0	4	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	4	0	0
T45	0	3	0	0
T70	0	2	0	0
T79	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	76447	0	0
T1	17251	72	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	114	0	0
T33	0	116	0	0
T36	0	84	0	0
T37	0	122	0	0
T38	0	77	0	0
T39	0	102	0	0
T45	0	36	0	0
T70	0	81	0	0
T79	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984824	0	0
T1	17251	11166	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	5	0	0
T23	933	1	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T96	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	21297	0	0
T1	17251	230	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	116	0	0
T33	0	371	0	0
T36	0	40	0	0
T37	0	82	0	0
T38	0	26	0	0
T39	0	85	0	0
T45	0	51	0	0
T70	0	42	0	0
T79	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	70	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T45	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6827733	0	0
T1	17251	10791	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6830119	0	0
T1	17251	10809	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	82	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T45	0	2	0	0
T70	0	1	0	0
T79	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	75	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T45	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	70	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T45	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	70	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T45	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	21202	0	0
T1	17251	227	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	114	0	0
T33	0	368	0	0
T36	0	39	0	0
T37	0	80	0	0
T38	0	25	0	0
T39	0	82	0	0
T45	0	49	0	0
T70	0	41	0	0
T79	0	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	44	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T23,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T23,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T23,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T23,T36
1	0	Covered	T4,T5,T1
1	1	Covered	T10,T23,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T36
0	1	Covered	T23,T33,T37
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T23,T36
1	-	Covered	T23,T33,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T23,T36
DetectSt	168	Covered	T10,T23,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T23,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T23,T36
DebounceSt->IdleSt	163	Covered	T180,T144,T72
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T23,T36
IdleSt->DebounceSt	148	Covered	T10,T23,T36
StableSt->IdleSt	206	Covered	T23,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T23,T36
0	1	Covered	T10,T23,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T23,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T23,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T23,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T180,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T23,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T23,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T33,T37
StableSt	-	-	-	-	-	-	0	Covered	T10,T23,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	79	0	0
CntIncr_A	7650645	30069	0	0
CntNoWrap_A	7650645	6984902	0	0
DetectStDropOut_A	7650645	0	0	0
DetectedOut_A	7650645	22041	0	0
DetectedPulseOut_A	7650645	38	0	0
DisabledIdleSt_A	7650645	6876929	0	0
DisabledNoDetection_A	7650645	6879323	0	0
EnterDebounceSt_A	7650645	41	0	0
EnterDetectSt_A	7650645	38	0	0
EnterStableSt_A	7650645	38	0	0
PulseIsPulse_A	7650645	38	0	0
StayInStableSt	7650645	21981	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	6667	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	79	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T45	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	6	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	30069	0	0
T10	673	38	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	57	0	0
T29	14170	0	0	0
T33	0	117	0	0
T35	0	36	0	0
T36	0	84	0	0
T37	0	122	0	0
T38	0	77	0	0
T45	0	18	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	129	0	0
T181	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984902	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	22041	0	0
T10	673	48	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	234	0	0
T29	14170	0	0	0
T33	0	48	0	0
T35	0	37	0	0
T36	0	146	0	0
T37	0	83	0	0
T38	0	129	0	0
T45	0	41	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	126	0	0
T181	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	38	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	1	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	3	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6876929	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6879323	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	41	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	1	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	3	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	38	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	1	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	3	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	38	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	1	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	3	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	38	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	1	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	3	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	21981	0	0
T10	673	46	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	233	0	0
T29	14170	0	0	0
T33	0	45	0	0
T35	0	35	0	0
T36	0	144	0	0
T37	0	80	0	0
T38	0	127	0	0
T45	0	40	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T133	0	122	0	0
T181	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6667	0	0
T1	17251	48	0	0
T2	1263	5	0	0
T3	681	2	0	0
T4	495	8	0	0
T5	498	4	0	0
T13	8419	0	0	0
T14	439	4	0	0
T15	422	3	0	0
T16	674	0	0	0
T17	502	5	0	0
T18	0	6	0	0
T19	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	15	0	0
T23	933	1	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	466	0	0	0
T45	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T115	404	0	0	0
T116	421	0	0	0
T132	0	1	0	0
T133	0	2	0	0
T164	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T33,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T33,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T33,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T33,T37
1	0	Covered	T4,T5,T1
1	1	Covered	T10,T33,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T33,T37
0	1	Covered	T79,T180,T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T33,T37
0	1	Covered	T10,T33,T39
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T33,T37
1	-	Covered	T10,T33,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T33,T37
DetectSt	168	Covered	T10,T33,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T33,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T33,T37
DebounceSt->IdleSt	163	Covered	T81,T146,T148
DetectSt->IdleSt	186	Covered	T79,T180,T185
DetectSt->StableSt	191	Covered	T10,T33,T37
IdleSt->DebounceSt	148	Covered	T10,T33,T37
StableSt->IdleSt	206	Covered	T10,T33,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T33,T37
0	1	Covered	T10,T33,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T33,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T33,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T33,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T146,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T33,T37
DetectSt	-	-	-	-	1	-	-	Covered	T79,T180,T185
DetectSt	-	-	-	-	0	1	-	Covered	T10,T33,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T33,T39
StableSt	-	-	-	-	-	-	0	Covered	T10,T33,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	132	0	0
CntIncr_A	7650645	131638	0	0
CntNoWrap_A	7650645	6984849	0	0
DetectStDropOut_A	7650645	3	0	0
DetectedOut_A	7650645	70035	0	0
DetectedPulseOut_A	7650645	60	0	0
DisabledIdleSt_A	7650645	6538468	0	0
DisabledNoDetection_A	7650645	6540856	0	0
EnterDebounceSt_A	7650645	69	0	0
EnterDetectSt_A	7650645	63	0	0
EnterStableSt_A	7650645	60	0	0
PulseIsPulse_A	7650645	60	0	0
StayInStableSt	7650645	69949	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	132	0	0
T10	673	4	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	2	0	0
T39	0	2	0	0
T45	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	6	0	0
T176	0	4	0	0
T186	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	131638	0	0
T10	673	76	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	71	0	0
T34	0	30	0	0
T35	0	105	0	0
T37	0	61	0	0
T39	0	51	0	0
T45	0	92	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	36	0	0
T176	0	136	0	0
T186	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984849	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3	0	0
T34	617	0	0	0
T75	630	0	0	0
T79	615	1	0	0
T105	404	0	0	0
T106	524	0	0	0
T107	737	0	0	0
T108	44647	0	0	0
T109	17658	0	0	0
T133	7672	0	0	0
T180	0	1	0	0
T185	0	1	0	0
T187	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	70035	0	0
T10	673	107	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	41	0	0
T34	0	177	0	0
T35	0	269	0	0
T37	0	231	0	0
T39	0	103	0	0
T45	0	174	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	60	0	0
T176	0	138	0	0
T186	0	205	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	60	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	2	0	0
T176	0	2	0	0
T186	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6538468	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6540856	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	69	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	3	0	0
T176	0	2	0	0
T186	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	63	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	3	0	0
T176	0	2	0	0
T186	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	60	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	2	0	0
T176	0	2	0	0
T186	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	60	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	2	0	0
T176	0	2	0	0
T186	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	69949	0	0
T10	673	104	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	40	0	0
T34	0	175	0	0
T35	0	267	0	0
T37	0	229	0	0
T39	0	102	0	0
T45	0	173	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	57	0	0
T176	0	135	0	0
T186	0	204	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	33	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T29	14170	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T39	0	1	0	0
T45	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T79	0	1	0	0
T146	0	1	0	0
T153	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T23,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T36
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T23,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T36
0	1	Covered	T1,T23,T36
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T23,T36
1	-	Covered	T1,T23,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T23,T36
DetectSt	168	Covered	T1,T23,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T23,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T23,T36
DebounceSt->IdleSt	163	Covered	T122,T72
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T23,T36
IdleSt->DebounceSt	148	Covered	T1,T23,T36
StableSt->IdleSt	206	Covered	T1,T23,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T23,T36
0	1	Covered	T1,T23,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T23,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T23,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T23,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T122
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T23,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T23,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T23,T36
StableSt	-	-	-	-	-	-	0	Covered	T1,T23,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	98	0	0
CntIncr_A	7650645	3000	0	0
CntNoWrap_A	7650645	6984883	0	0
DetectStDropOut_A	7650645	0	0	0
DetectedOut_A	7650645	3480	0	0
DetectedPulseOut_A	7650645	48	0	0
DisabledIdleSt_A	7650645	6843306	0	0
DisabledNoDetection_A	7650645	6845688	0	0
EnterDebounceSt_A	7650645	50	0	0
EnterDetectSt_A	7650645	48	0	0
EnterStableSt_A	7650645	48	0	0
PulseIsPulse_A	7650645	48	0	0
StayInStableSt	7650645	3407	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	6335	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	98	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	4	0	0
T33	0	6	0	0
T36	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T45	0	6	0	0
T70	0	2	0	0
T133	0	2	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3000	0	0
T1	17251	36	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	114	0	0
T33	0	215	0	0
T36	0	168	0	0
T38	0	77	0	0
T39	0	51	0	0
T45	0	128	0	0
T70	0	81	0	0
T133	0	43	0	0
T151	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984883	0	0
T1	17251	11168	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3480	0	0
T1	17251	6	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	251	0	0
T33	0	173	0	0
T36	0	316	0	0
T38	0	11	0	0
T39	0	96	0	0
T45	0	213	0	0
T70	0	48	0	0
T133	0	178	0	0
T151	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	48	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	3	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	3	0	0
T70	0	1	0	0
T133	0	1	0	0
T151	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6843306	0	0
T1	17251	10791	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6845688	0	0
T1	17251	10809	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	50	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	3	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	3	0	0
T70	0	1	0	0
T133	0	1	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	48	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	3	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	3	0	0
T70	0	1	0	0
T133	0	1	0	0
T151	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	48	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	3	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	3	0	0
T70	0	1	0	0
T133	0	1	0	0
T151	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	48	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	3	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	3	0	0
T70	0	1	0	0
T133	0	1	0	0
T151	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3407	0	0
T1	17251	5	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	248	0	0
T33	0	168	0	0
T36	0	313	0	0
T38	0	9	0	0
T39	0	94	0	0
T45	0	208	0	0
T70	0	47	0	0
T133	0	176	0	0
T151	0	82	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6335	0	0
T1	17251	37	0	0
T2	1263	0	0	0
T3	681	0	0	0
T4	495	7	0	0
T5	498	10	0	0
T6	0	16	0	0
T13	8419	0	0	0
T14	439	3	0	0
T15	422	1	0	0
T16	674	0	0	0
T17	502	4	0	0
T18	0	8	0	0
T19	0	30	0	0
T46	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	22	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	1	0	0
T33	0	1	0	0
T36	0	1	0	0
T45	0	1	0	0
T70	0	1	0	0
T146	0	1	0	0
T151	0	1	0	0
T164	0	1	0	0
T176	0	1	0	0