Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T23,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T23,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T23,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T23,T63
1	0	Covered	T4,T5,T1
1	1	Covered	T10,T23,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T33
0	1	Covered	T188,T178,T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T33
0	1	Covered	T10,T23,T33
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T23,T33
1	-	Covered	T10,T23,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T23,T33
DetectSt	168	Covered	T10,T23,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T23,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T23,T33
DebounceSt->IdleSt	163	Covered	T152,T190,T191
DetectSt->IdleSt	186	Covered	T188,T178,T189
DetectSt->StableSt	191	Covered	T10,T23,T33
IdleSt->DebounceSt	148	Covered	T10,T23,T33
StableSt->IdleSt	206	Covered	T10,T23,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T23,T33
0	1	Covered	T10,T23,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T23,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T23,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T23,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T152,T190,T191
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T23,T33
DetectSt	-	-	-	-	1	-	-	Covered	T188,T178,T189
DetectSt	-	-	-	-	0	1	-	Covered	T10,T23,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T23,T33
StableSt	-	-	-	-	-	-	0	Covered	T10,T23,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	158	0	0
CntIncr_A	7650645	206154	0	0
CntNoWrap_A	7650645	6984823	0	0
DetectStDropOut_A	7650645	4	0	0
DetectedOut_A	7650645	44931	0	0
DetectedPulseOut_A	7650645	71	0	0
DisabledIdleSt_A	7650645	6414933	0	0
DisabledNoDetection_A	7650645	6417322	0	0
EnterDebounceSt_A	7650645	83	0	0
EnterDetectSt_A	7650645	75	0	0
EnterStableSt_A	7650645	71	0	0
PulseIsPulse_A	7650645	71	0	0
StayInStableSt	7650645	44831	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	158	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	4	0	0
T29	14170	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	4	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	2	0	0
T108	0	2	0	0
T133	0	4	0	0
T151	0	2	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	206154	0	0
T10	673	38	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	114	0	0
T29	14170	0	0	0
T33	0	144	0	0
T34	0	30	0	0
T35	0	122	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	33	0	0
T108	0	30267	0	0
T133	0	86	0	0
T151	0	31	0	0
T181	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984823	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	4	0	0
T130	0	1	0	0
T178	0	1	0	0
T188	623	1	0	0
T189	0	1	0	0
T192	11817	0	0	0
T193	25514	0	0	0
T194	512	0	0	0
T195	502	0	0	0
T196	729	0	0	0
T197	19394	0	0	0
T198	993	0	0	0
T199	11768	0	0	0
T200	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	44931	0	0
T10	673	86	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	153	0	0
T29	14170	0	0	0
T33	0	58	0	0
T34	0	147	0	0
T35	0	171	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	76	0	0
T108	0	45	0	0
T133	0	86	0	0
T151	0	79	0	0
T181	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	71	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T108	0	1	0	0
T133	0	2	0	0
T151	0	1	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6414933	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6417322	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	83	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T108	0	1	0	0
T133	0	2	0	0
T151	0	1	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	75	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T108	0	1	0	0
T133	0	2	0	0
T151	0	1	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	71	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T108	0	1	0	0
T133	0	2	0	0
T151	0	1	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	71	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T108	0	1	0	0
T133	0	2	0	0
T151	0	1	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	44831	0	0
T10	673	85	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	151	0	0
T29	14170	0	0	0
T33	0	55	0	0
T34	0	145	0	0
T35	0	168	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	75	0	0
T108	0	43	0	0
T133	0	83	0	0
T151	0	78	0	0
T181	0	17	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	41	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T133	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T181	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T23,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T63
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T23,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T33
0	1	Covered	T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T33
0	1	Covered	T23,T33,T70
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T23,T33
1	-	Covered	T23,T33,T70

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T23,T33
DetectSt	168	Covered	T1,T23,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T23,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T23,T33
DebounceSt->IdleSt	163	Covered	T45,T134,T146
DetectSt->IdleSt	186	Covered	T169
DetectSt->StableSt	191	Covered	T1,T23,T33
IdleSt->DebounceSt	148	Covered	T1,T23,T33
StableSt->IdleSt	206	Covered	T1,T23,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T23,T33
0	1	Covered	T1,T23,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T23,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T23,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T23,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T134,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T23,T33
DetectSt	-	-	-	-	1	-	-	Covered	T169
DetectSt	-	-	-	-	0	1	-	Covered	T1,T23,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T33,T70
StableSt	-	-	-	-	-	-	0	Covered	T1,T23,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	81	0	0
CntIncr_A	7650645	130172	0	0
CntNoWrap_A	7650645	6984900	0	0
DetectStDropOut_A	7650645	1	0	0
DetectedOut_A	7650645	130844	0	0
DetectedPulseOut_A	7650645	36	0	0
DisabledIdleSt_A	7650645	6577780	0	0
DisabledNoDetection_A	7650645	6580172	0	0
EnterDebounceSt_A	7650645	44	0	0
EnterDetectSt_A	7650645	37	0	0
EnterStableSt_A	7650645	36	0	0
PulseIsPulse_A	7650645	36	0	0
StayInStableSt	7650645	130793	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	6265	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	81	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	4	0	0
T33	0	4	0	0
T35	0	2	0	0
T37	0	2	0	0
T45	0	1	0	0
T64	0	2	0	0
T70	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	130172	0	0
T1	17251	36	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	114	0	0
T33	0	117	0	0
T35	0	44	0	0
T37	0	61	0	0
T45	0	18	0	0
T64	0	33	0	0
T70	0	162	0	0
T133	0	43	0	0
T134	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984900	0	0
T1	17251	11168	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1	0	0
T81	29889	0	0	0
T128	1863	0	0	0
T169	1026	1	0	0
T201	426	0	0	0
T202	516	0	0	0
T203	495	0	0	0
T204	19972	0	0	0
T205	448	0	0	0
T206	916	0	0	0
T207	9644	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	130844	0	0
T1	17251	124	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	81	0	0
T33	0	160	0	0
T35	0	88	0	0
T37	0	45	0	0
T64	0	54	0	0
T70	0	362	0	0
T133	0	87	0	0
T135	0	40	0	0
T153	0	95	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	36	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T133	0	1	0	0
T135	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6577780	0	0
T1	17251	10791	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6580172	0	0
T1	17251	10809	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	44	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T45	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	37	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T133	0	1	0	0
T135	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	36	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T133	0	1	0	0
T135	0	1	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	36	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T37	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T133	0	1	0	0
T135	0	1	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	130793	0	0
T1	17251	122	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	78	0	0
T33	0	157	0	0
T35	0	87	0	0
T37	0	43	0	0
T64	0	52	0	0
T70	0	359	0	0
T133	0	86	0	0
T135	0	38	0	0
T153	0	94	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6265	0	0
T1	17251	39	0	0
T2	1263	0	0	0
T3	681	0	0	0
T4	495	7	0	0
T5	498	6	0	0
T6	0	14	0	0
T13	8419	0	0	0
T14	439	4	0	0
T15	422	1	0	0
T16	674	0	0	0
T17	502	3	0	0
T18	0	5	0	0
T19	0	29	0	0
T46	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	20	0	0
T23	933	1	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T81	0	1	0	0
T97	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T133	0	1	0	0
T153	0	1	0	0
T169	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T36,T33,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T36,T33,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T36,T33,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T63,T33
1	0	Covered	T4,T5,T1
1	1	Covered	T36,T33,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T33,T37
0	1	Covered	T79,T169,T167
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T33,T37
0	1	Covered	T33,T37,T39
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T33,T37
1	-	Covered	T33,T37,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T33,T37
DetectSt	168	Covered	T36,T33,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T36,T33,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T33,T37
DebounceSt->IdleSt	163	Covered	T151,T79,T133
DetectSt->IdleSt	186	Covered	T79,T169,T167
DetectSt->StableSt	191	Covered	T36,T33,T37
IdleSt->DebounceSt	148	Covered	T36,T33,T37
StableSt->IdleSt	206	Covered	T36,T33,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T33,T37
0	1	Covered	T36,T33,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T33,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T33,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T33,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T79,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T33,T37
DetectSt	-	-	-	-	1	-	-	Covered	T79,T169,T167
DetectSt	-	-	-	-	0	1	-	Covered	T36,T33,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T37,T39
StableSt	-	-	-	-	-	-	0	Covered	T36,T33,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	163	0	0
CntIncr_A	7650645	78799	0	0
CntNoWrap_A	7650645	6984818	0	0
DetectStDropOut_A	7650645	3	0	0
DetectedOut_A	7650645	26353	0	0
DetectedPulseOut_A	7650645	75	0	0
DisabledIdleSt_A	7650645	6792196	0	0
DisabledNoDetection_A	7650645	6794580	0	0
EnterDebounceSt_A	7650645	85	0	0
EnterDetectSt_A	7650645	78	0	0
EnterStableSt_A	7650645	75	0	0
PulseIsPulse_A	7650645	75	0	0
StayInStableSt	7650645	26245	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	163	0	0
T30	19927	0	0	0
T33	0	4	0	0
T34	0	2	0	0
T36	28592	2	0	0
T37	0	2	0	0
T38	6512	0	0	0
T39	0	4	0	0
T41	614	0	0	0
T45	0	2	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	5	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	2	0	0
T133	0	3	0	0
T151	0	3	0	0
T208	416	0	0	0
T209	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	78799	0	0
T30	19927	0	0	0
T33	0	143	0	0
T34	0	30	0	0
T36	28592	84	0	0
T37	0	61	0	0
T38	6512	0	0	0
T39	0	102	0	0
T41	614	0	0	0
T45	0	18	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	36	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	30267	0	0
T133	0	86	0	0
T151	0	62	0	0
T208	416	0	0	0
T209	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984818	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3	0	0
T34	617	0	0	0
T75	630	0	0	0
T79	615	1	0	0
T105	404	0	0	0
T106	524	0	0	0
T107	737	0	0	0
T108	44647	0	0	0
T109	17658	0	0	0
T133	7672	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T187	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	26353	0	0
T30	19927	0	0	0
T33	0	158	0	0
T34	0	72	0	0
T36	28592	43	0	0
T37	0	160	0	0
T38	6512	0	0	0
T39	0	147	0	0
T41	614	0	0	0
T45	0	60	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	6	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	45	0	0
T133	0	43	0	0
T151	0	43	0	0
T208	416	0	0	0
T209	424	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	75	0	0
T30	19927	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	28592	1	0	0
T37	0	1	0	0
T38	6512	0	0	0
T39	0	2	0	0
T41	614	0	0	0
T45	0	1	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	1	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	1	0	0
T133	0	1	0	0
T151	0	1	0	0
T208	416	0	0	0
T209	424	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6792196	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6794580	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	85	0	0
T30	19927	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	28592	1	0	0
T37	0	1	0	0
T38	6512	0	0	0
T39	0	2	0	0
T41	614	0	0	0
T45	0	1	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	3	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	1	0	0
T133	0	2	0	0
T151	0	2	0	0
T208	416	0	0	0
T209	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	78	0	0
T30	19927	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	28592	1	0	0
T37	0	1	0	0
T38	6512	0	0	0
T39	0	2	0	0
T41	614	0	0	0
T45	0	1	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	2	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	1	0	0
T133	0	1	0	0
T151	0	1	0	0
T208	416	0	0	0
T209	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	75	0	0
T30	19927	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	28592	1	0	0
T37	0	1	0	0
T38	6512	0	0	0
T39	0	2	0	0
T41	614	0	0	0
T45	0	1	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	1	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	1	0	0
T133	0	1	0	0
T151	0	1	0	0
T208	416	0	0	0
T209	424	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	75	0	0
T30	19927	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	28592	1	0	0
T37	0	1	0	0
T38	6512	0	0	0
T39	0	2	0	0
T41	614	0	0	0
T45	0	1	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	1	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	1	0	0
T133	0	1	0	0
T151	0	1	0	0
T208	416	0	0	0
T209	424	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	26245	0	0
T30	19927	0	0	0
T33	0	155	0	0
T34	0	71	0	0
T36	28592	41	0	0
T37	0	159	0	0
T38	6512	0	0	0
T39	0	144	0	0
T41	614	0	0	0
T45	0	59	0	0
T63	491	0	0	0
T69	8747	0	0	0
T79	0	5	0	0
T82	489	0	0	0
T100	502	0	0	0
T108	0	43	0	0
T133	0	42	0	0
T151	0	41	0	0
T208	416	0	0	0
T209	424	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	41	0	0
T33	229451	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	821	1	0	0
T39	0	1	0	0
T43	56764	0	0	0
T45	0	1	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T79	0	1	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T133	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0
T210	523	0	0	0
T211	408	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T38,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T33,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T38,T63
1	0	Covered	T4,T5,T1
1	1	Covered	T38,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T35,T130
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T35
0	1	Covered	T35,T145,T169
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T34,T35
1	-	Covered	T35,T145,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T33,T34
DetectSt	168	Covered	T33,T34,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T33,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T34,T35
DebounceSt->IdleSt	163	Covered	T38,T72
DetectSt->IdleSt	186	Covered	T35,T130
DetectSt->StableSt	191	Covered	T33,T34,T35
IdleSt->DebounceSt	148	Covered	T38,T33,T34
StableSt->IdleSt	206	Covered	T33,T35,T153

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T33,T34,T35
0	1	Covered	T38,T33,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T34,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T35,T130
DetectSt	-	-	-	-	0	1	-	Covered	T33,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T51,T145
StableSt	-	-	-	-	-	-	0	Covered	T33,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	87	0	0
CntIncr_A	7650645	38249	0	0
CntNoWrap_A	7650645	6984894	0	0
DetectStDropOut_A	7650645	2	0	0
DetectedOut_A	7650645	2710	0	0
DetectedPulseOut_A	7650645	41	0	0
DisabledIdleSt_A	7650645	6812931	0	0
DisabledNoDetection_A	7650645	6815322	0	0
EnterDebounceSt_A	7650645	45	0	0
EnterDetectSt_A	7650645	43	0	0
EnterStableSt_A	7650645	41	0	0
PulseIsPulse_A	7650645	41	0	0
StayInStableSt	7650645	2652	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	6261	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	87	0	0
T33	229451	2	0	0
T34	0	2	0	0
T35	0	8	0	0
T37	821	0	0	0
T43	56764	0	0	0
T51	0	2	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T145	0	2	0	0
T153	0	2	0	0
T155	0	4	0	0
T169	0	4	0	0
T180	0	4	0	0
T210	523	0	0	0
T211	408	0	0	0
T212	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	38249	0	0
T30	19927	0	0	0
T33	0	71	0	0
T34	0	30	0	0
T35	0	177	0	0
T38	6512	9	0	0
T41	614	0	0	0
T51	0	21	0	0
T63	491	0	0	0
T69	8747	0	0	0
T82	489	0	0	0
T100	502	0	0	0
T101	645	0	0	0
T102	9965	0	0	0
T145	0	53	0	0
T153	0	43	0	0
T155	0	129	0	0
T169	0	144	0	0
T209	424	0	0	0
T212	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984894	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2	0	0
T35	205975	1	0	0
T80	812	0	0	0
T89	5216	0	0	0
T90	42811	0	0	0
T130	0	1	0	0
T170	540	0	0	0
T171	427	0	0	0
T172	450	0	0	0
T173	29972	0	0	0
T174	501	0	0	0
T175	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2710	0	0
T33	229451	90	0	0
T34	0	43	0	0
T35	0	202	0	0
T37	821	0	0	0
T43	56764	0	0	0
T51	0	5	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T145	0	8	0	0
T153	0	52	0	0
T155	0	88	0	0
T169	0	305	0	0
T180	0	100	0	0
T210	523	0	0	0
T211	408	0	0	0
T212	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	41	0	0
T33	229451	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	821	0	0	0
T43	56764	0	0	0
T51	0	1	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T145	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0
T169	0	2	0	0
T180	0	2	0	0
T210	523	0	0	0
T211	408	0	0	0
T212	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6812931	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6815322	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	45	0	0
T30	19927	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T38	6512	1	0	0
T41	614	0	0	0
T51	0	1	0	0
T63	491	0	0	0
T69	8747	0	0	0
T82	489	0	0	0
T100	502	0	0	0
T101	645	0	0	0
T102	9965	0	0	0
T145	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0
T169	0	2	0	0
T209	424	0	0	0
T212	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	43	0	0
T33	229451	1	0	0
T34	0	1	0	0
T35	0	4	0	0
T37	821	0	0	0
T43	56764	0	0	0
T51	0	1	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T145	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0
T169	0	2	0	0
T180	0	2	0	0
T210	523	0	0	0
T211	408	0	0	0
T212	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	41	0	0
T33	229451	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	821	0	0	0
T43	56764	0	0	0
T51	0	1	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T145	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0
T169	0	2	0	0
T180	0	2	0	0
T210	523	0	0	0
T211	408	0	0	0
T212	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	41	0	0
T33	229451	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	821	0	0	0
T43	56764	0	0	0
T51	0	1	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T145	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0
T169	0	2	0	0
T180	0	2	0	0
T210	523	0	0	0
T211	408	0	0	0
T212	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2652	0	0
T33	229451	88	0	0
T34	0	41	0	0
T35	0	198	0	0
T37	821	0	0	0
T43	56764	0	0	0
T51	0	4	0	0
T55	559	0	0	0
T56	500	0	0	0
T57	495	0	0	0
T85	28329	0	0	0
T104	23794	0	0	0
T145	0	7	0	0
T153	0	50	0	0
T155	0	84	0	0
T169	0	302	0	0
T180	0	97	0	0
T210	523	0	0	0
T211	408	0	0	0
T212	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6261	0	0
T1	17251	39	0	0
T2	1263	0	0	0
T3	681	0	0	0
T4	495	6	0	0
T5	498	6	0	0
T6	0	15	0	0
T13	8419	0	0	0
T14	439	5	0	0
T15	422	1	0	0
T16	674	0	0	0
T17	502	4	0	0
T18	0	5	0	0
T19	0	31	0	0
T46	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	23	0	0
T35	205975	2	0	0
T80	812	0	0	0
T89	5216	0	0	0
T90	42811	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T132	0	1	0	0
T145	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0
T169	0	1	0	0
T170	540	0	0	0
T171	427	0	0	0
T172	450	0	0	0
T173	29972	0	0	0
T174	501	0	0	0
T175	402	0	0	0
T180	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T23,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T23,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T23,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T23,T33
1	0	Covered	T4,T5,T1
1	1	Covered	T10,T23,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T33
0	1	Covered	T23,T70,T35
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T33
0	1	Covered	T10,T23,T33
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T23,T33
1	-	Covered	T10,T23,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T23,T33
DetectSt	168	Covered	T10,T23,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T23,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T23,T33
DebounceSt->IdleSt	163	Covered	T64,T213,T150
DetectSt->IdleSt	186	Covered	T23,T70,T35
DetectSt->StableSt	191	Covered	T10,T23,T33
IdleSt->DebounceSt	148	Covered	T10,T23,T33
StableSt->IdleSt	206	Covered	T10,T23,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T23,T33
0	1	Covered	T10,T23,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T23,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T23,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T23,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T213,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T23,T33
DetectSt	-	-	-	-	1	-	-	Covered	T23,T70,T35
DetectSt	-	-	-	-	0	1	-	Covered	T10,T23,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T23,T33
StableSt	-	-	-	-	-	-	0	Covered	T10,T23,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	141	0	0
CntIncr_A	7650645	69583	0	0
CntNoWrap_A	7650645	6984840	0	0
DetectStDropOut_A	7650645	5	0	0
DetectedOut_A	7650645	5408	0	0
DetectedPulseOut_A	7650645	63	0	0
DisabledIdleSt_A	7650645	6850486	0	0
DisabledNoDetection_A	7650645	6852872	0	0
EnterDebounceSt_A	7650645	73	0	0
EnterDetectSt_A	7650645	68	0	0
EnterStableSt_A	7650645	63	0	0
PulseIsPulse_A	7650645	63	0	0
StayInStableSt	7650645	5321	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	141	0	0
T10	673	2	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	6	0	0
T29	14170	0	0	0
T33	0	4	0	0
T35	0	8	0	0
T39	0	2	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T70	0	4	0	0
T108	0	2	0	0
T151	0	2	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	69583	0	0
T10	673	38	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	171	0	0
T29	14170	0	0	0
T33	0	143	0	0
T35	0	202	0	0
T39	0	51	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	33	0	0
T70	0	162	0	0
T108	0	30267	0	0
T151	0	31	0	0
T181	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984840	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	5	0	0
T23	933	1	0	0
T25	733	0	0	0
T29	14170	0	0	0
T32	30695	0	0	0
T35	0	1	0	0
T40	466	0	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T115	404	0	0	0
T116	421	0	0	0
T153	0	1	0	0
T176	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	5408	0	0
T10	673	138	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	54	0	0
T29	14170	0	0	0
T33	0	547	0	0
T35	0	209	0	0
T39	0	103	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T70	0	44	0	0
T108	0	44	0	0
T151	0	154	0	0
T153	0	387	0	0
T181	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	63	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	3	0	0
T39	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T108	0	1	0	0
T151	0	1	0	0
T153	0	2	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6850486	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6852872	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	73	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	3	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T39	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T64	0	1	0	0
T70	0	2	0	0
T108	0	1	0	0
T151	0	1	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	68	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	3	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T39	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T70	0	2	0	0
T108	0	1	0	0
T151	0	1	0	0
T176	0	1	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	63	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	3	0	0
T39	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T108	0	1	0	0
T151	0	1	0	0
T153	0	2	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	63	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	2	0	0
T35	0	3	0	0
T39	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T108	0	1	0	0
T151	0	1	0	0
T153	0	2	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	5321	0	0
T10	673	137	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	52	0	0
T29	14170	0	0	0
T33	0	544	0	0
T35	0	204	0	0
T39	0	102	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T70	0	43	0	0
T108	0	42	0	0
T151	0	152	0	0
T153	0	383	0	0
T181	0	17	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	38	0	0
T10	673	1	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	2	0	0
T29	14170	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T53	481	0	0	0
T54	993	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T62	525	0	0	0
T70	0	1	0	0
T81	0	1	0	0
T145	0	2	0	0
T169	0	2	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T23
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T10,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T23
0	1	Covered	T38
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T23
0	1	Covered	T1,T23,T36
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T23
1	-	Covered	T1,T23,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T23
DetectSt	168	Covered	T1,T10,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T10,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T23
DebounceSt->IdleSt	163	Covered	T35,T214,T215
DetectSt->IdleSt	186	Covered	T38
DetectSt->StableSt	191	Covered	T1,T10,T23
IdleSt->DebounceSt	148	Covered	T1,T10,T23
StableSt->IdleSt	206	Covered	T1,T23,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T23
0	1	Covered	T1,T10,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T214,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T23
DetectSt	-	-	-	-	1	-	-	Covered	T38
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T23,T36
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	91	0	0
CntIncr_A	7650645	38534	0	0
CntNoWrap_A	7650645	6984890	0	0
DetectStDropOut_A	7650645	1	0	0
DetectedOut_A	7650645	3357	0	0
DetectedPulseOut_A	7650645	42	0	0
DisabledIdleSt_A	7650645	6818102	0	0
DisabledNoDetection_A	7650645	6820493	0	0
EnterDebounceSt_A	7650645	48	0	0
EnterDetectSt_A	7650645	43	0	0
EnterStableSt_A	7650645	42	0	0
PulseIsPulse_A	7650645	42	0	0
StayInStableSt	7650645	3290	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7650645	7021	0	0
gen_low_level_sva.LowLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	91	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	2	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	6	0	0
T35	0	3	0	0
T36	0	2	0	0
T38	0	2	0	0
T70	0	4	0	0
T135	0	2	0	0
T176	0	2	0	0
T186	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	38534	0	0
T1	17251	36	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	38	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	171	0	0
T35	0	97	0	0
T36	0	84	0	0
T38	0	77	0	0
T70	0	162	0	0
T135	0	65	0	0
T176	0	68	0	0
T186	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984890	0	0
T1	17251	11168	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1	0	0
T30	19927	0	0	0
T38	6512	1	0	0
T41	614	0	0	0
T63	491	0	0	0
T69	8747	0	0	0
T82	489	0	0	0
T100	502	0	0	0
T101	645	0	0	0
T102	9965	0	0	0
T209	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3357	0	0
T1	17251	31	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	49	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	123	0	0
T35	0	151	0	0
T36	0	145	0	0
T70	0	370	0	0
T135	0	40	0	0
T153	0	145	0	0
T176	0	36	0	0
T186	0	220	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	42	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T70	0	2	0	0
T135	0	1	0	0
T153	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6818102	0	0
T1	17251	10791	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6820493	0	0
T1	17251	10809	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	48	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	3	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T70	0	2	0	0
T135	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	43	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T70	0	2	0	0
T135	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	42	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T70	0	2	0	0
T135	0	1	0	0
T153	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	42	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	1	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	3	0	0
T35	0	1	0	0
T36	0	1	0	0
T70	0	2	0	0
T135	0	1	0	0
T153	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3290	0	0
T1	17251	30	0	0
T2	1263	0	0	0
T3	681	0	0	0
T10	0	47	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	119	0	0
T35	0	149	0	0
T36	0	144	0	0
T70	0	367	0	0
T135	0	38	0	0
T153	0	143	0	0
T176	0	34	0	0
T186	0	218	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	7021	0	0
T1	17251	44	0	0
T2	1263	5	0	0
T3	681	2	0	0
T4	495	7	0	0
T5	498	9	0	0
T13	8419	0	0	0
T14	439	5	0	0
T15	422	3	0	0
T16	674	3	0	0
T17	502	5	0	0
T18	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	16	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T23	0	2	0	0
T36	0	1	0	0
T70	0	1	0	0
T97	0	1	0	0
T145	0	1	0	0
T169	0	1	0	0
T188	0	1	0	0
T212	0	1	0	0
T216	0	1	0	0