Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T8,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T8,T12
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T8,T12
0	1	Covered	T30,T67,T68
1	0	Covered	T30,T68,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T8,T12
0	1	Covered	T19,T8,T12
1	0	Covered	T217

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T8,T12
1	-	Covered	T19,T8,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T8,T12
DetectSt	168	Covered	T19,T8,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T19,T8,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T8,T12
DebounceSt->IdleSt	163	Covered	T51,T218,T219
DetectSt->IdleSt	186	Covered	T30,T67,T68
DetectSt->StableSt	191	Covered	T19,T8,T12
IdleSt->DebounceSt	148	Covered	T19,T8,T12
StableSt->IdleSt	206	Covered	T19,T8,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T8,T12
0	1	Covered	T19,T8,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T8,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T19,T8,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T30,T67,T68
DetectSt	-	-	-	-	0	1	-	Covered	T19,T8,T12
DetectSt	-	-	-	-	0	0	-	Covered	T19,T8,T12
StableSt	-	-	-	-	-	-	1	Covered	T19,T8,T12
StableSt	-	-	-	-	-	-	0	Covered	T19,T8,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	3136	0	0
CntIncr_A	7650645	103769	0	0
CntNoWrap_A	7650645	6981845	0	0
DetectStDropOut_A	7650645	379	0	0
DetectedOut_A	7650645	71342	0	0
DetectedPulseOut_A	7650645	931	0	0
DisabledIdleSt_A	7650645	6542109	0	0
DisabledNoDetection_A	7650645	6544350	0	0
EnterDebounceSt_A	7650645	1579	0	0
EnterDetectSt_A	7650645	1558	0	0
EnterStableSt_A	7650645	931	0	0
PulseIsPulse_A	7650645	931	0	0
StayInStableSt	7650645	70297	0	0
gen_high_event_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	816	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3136	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	22	0	0
T12	0	26	0	0
T19	5999	32	0	0
T24	702	0	0	0
T29	0	56	0	0
T30	0	20	0	0
T31	0	20	0	0
T40	0	2	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	50	0	0
T66	0	38	0	0
T67	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	103769	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	693	0	0
T12	0	1053	0	0
T19	5999	528	0	0
T24	702	0	0	0
T29	0	1036	0	0
T30	0	596	0	0
T31	0	310	0	0
T40	0	21	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	2000	0	0
T66	0	931	0	0
T67	0	831	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6981845	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	379	0	0
T30	19927	3	0	0
T41	614	0	0	0
T42	8334	0	0	0
T51	0	1	0	0
T63	491	0	0	0
T67	0	17	0	0
T68	0	13	0	0
T69	8747	0	0	0
T82	489	0	0	0
T86	0	6	0	0
T88	0	9	0	0
T89	0	3	0	0
T90	0	5	0	0
T91	0	14	0	0
T100	502	0	0	0
T101	645	0	0	0
T102	9965	0	0	0
T209	424	0	0	0
T220	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	71342	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	1105	0	0
T12	0	590	0	0
T19	5999	231	0	0
T24	702	0	0	0
T29	0	2159	0	0
T31	0	751	0	0
T40	0	40	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	3132	0	0
T66	0	1405	0	0
T109	0	2334	0	0
T221	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	931	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	11	0	0
T12	0	13	0	0
T19	5999	16	0	0
T24	702	0	0	0
T29	0	28	0	0
T31	0	10	0	0
T40	0	1	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	25	0	0
T66	0	19	0	0
T109	0	31	0	0
T221	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6542109	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6544350	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1579	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	11	0	0
T12	0	13	0	0
T19	5999	16	0	0
T24	702	0	0	0
T29	0	28	0	0
T30	0	10	0	0
T31	0	10	0	0
T40	0	1	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	25	0	0
T66	0	19	0	0
T67	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1558	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	11	0	0
T12	0	13	0	0
T19	5999	16	0	0
T24	702	0	0	0
T29	0	28	0	0
T30	0	10	0	0
T31	0	10	0	0
T40	0	1	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	25	0	0
T66	0	19	0	0
T67	0	17	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	931	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	11	0	0
T12	0	13	0	0
T19	5999	16	0	0
T24	702	0	0	0
T29	0	28	0	0
T31	0	10	0	0
T40	0	1	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	25	0	0
T66	0	19	0	0
T109	0	31	0	0
T221	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	931	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	11	0	0
T12	0	13	0	0
T19	5999	16	0	0
T24	702	0	0	0
T29	0	28	0	0
T31	0	10	0	0
T40	0	1	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	25	0	0
T66	0	19	0	0
T109	0	31	0	0
T221	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	70297	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	1091	0	0
T12	0	577	0	0
T19	5999	215	0	0
T24	702	0	0	0
T29	0	2129	0	0
T31	0	739	0	0
T40	0	38	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	3102	0	0
T66	0	1384	0	0
T109	0	2298	0	0
T221	0	82	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	816	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	8	0	0
T12	0	13	0	0
T19	5999	16	0	0
T24	702	0	0	0
T29	0	26	0	0
T31	0	8	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T51	0	5	0	0
T65	0	20	0	0
T66	0	17	0	0
T73	0	11	0	0
T109	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T6
1	0	Covered	T1,T13,T19
1	1	Covered	T1,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T69,T85,T87
1	0	Covered	T51,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T7
1	-	Covered	T1,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T7
DetectSt	168	Covered	T1,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T7
DebounceSt->IdleSt	163	Covered	T7,T9,T40
DetectSt->IdleSt	186	Covered	T69,T85,T87
DetectSt->StableSt	191	Covered	T1,T6,T7
IdleSt->DebounceSt	148	Covered	T1,T6,T7
StableSt->IdleSt	206	Covered	T1,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T9,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T69,T85,T87
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	938	0	0
CntIncr_A	7650645	46897	0	0
CntNoWrap_A	7650645	6984043	0	0
DetectStDropOut_A	7650645	93	0	0
DetectedOut_A	7650645	13316	0	0
DetectedPulseOut_A	7650645	338	0	0
DisabledIdleSt_A	7650645	6624662	0	0
DisabledNoDetection_A	7650645	6626370	0	0
EnterDebounceSt_A	7650645	507	0	0
EnterDetectSt_A	7650645	434	0	0
EnterStableSt_A	7650645	338	0	0
PulseIsPulse_A	7650645	338	0	0
StayInStableSt	7650645	12932	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	289	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	938	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	2	0	0
T7	0	5	0	0
T8	0	6	0	0
T9	0	22	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	4	0	0
T32	0	4	0	0
T40	0	1	0	0
T69	0	23	0	0
T82	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	46897	0	0
T1	17251	25	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	25	0	0
T7	0	133	0	0
T8	0	210	0	0
T9	0	954	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	192	0	0
T32	0	216	0	0
T40	0	20	0	0
T69	0	961	0	0
T82	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984043	0	0
T1	17251	11168	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	93	0	0
T31	13726	0	0	0
T33	229451	0	0	0
T41	614	0	0	0
T42	8334	0	0	0
T69	8747	11	0	0
T85	0	1	0	0
T87	0	4	0	0
T92	0	8	0	0
T93	0	8	0	0
T94	0	7	0	0
T96	0	10	0	0
T97	0	5	0	0
T98	0	12	0	0
T99	0	11	0	0
T100	502	0	0	0
T101	645	0	0	0
T102	9965	0	0	0
T103	431	0	0	0
T104	23794	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	13316	0	0
T1	17251	3	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	3	0	0
T7	0	100	0	0
T8	0	206	0	0
T9	0	151	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	107	0	0
T31	0	76	0	0
T32	0	33	0	0
T42	0	18	0	0
T82	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	338	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	10	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T42	0	1	0	0
T82	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6624662	0	0
T1	17251	9189	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6626370	0	0
T1	17251	9204	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	507	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	1	0	0
T7	0	3	0	0
T8	0	3	0	0
T9	0	12	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T40	0	1	0	0
T69	0	12	0	0
T82	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	434	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	10	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T42	0	1	0	0
T69	0	11	0	0
T82	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	338	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	10	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T42	0	1	0	0
T82	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	338	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	10	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T42	0	1	0	0
T82	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	12932	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	2	0	0
T7	0	98	0	0
T8	0	203	0	0
T9	0	141	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	105	0	0
T31	0	75	0	0
T32	0	31	0	0
T42	0	17	0	0
T82	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	289	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T6	0	1	0	0
T7	0	2	0	0
T8	0	3	0	0
T9	0	10	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T42	0	1	0	0
T82	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T8,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T8,T12
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T8,T12
0	1	Covered	T67,T86,T89
1	0	Covered	T19,T12,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T30
0	1	Covered	T8,T29,T30
1	0	Covered	T8,T51,T222

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T29,T30
1	-	Covered	T8,T29,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T8,T12
DetectSt	168	Covered	T19,T8,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T29,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T8,T12
DebounceSt->IdleSt	163	Covered	T51,T218,T219
DetectSt->IdleSt	186	Covered	T19,T12,T67
DetectSt->StableSt	191	Covered	T8,T29,T30
IdleSt->DebounceSt	148	Covered	T19,T8,T12
StableSt->IdleSt	206	Covered	T8,T29,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T8,T12
0	1	Covered	T19,T8,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T8,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T19,T8,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T19,T12,T67
DetectSt	-	-	-	-	0	1	-	Covered	T8,T29,T30
DetectSt	-	-	-	-	0	0	-	Covered	T19,T8,T12
StableSt	-	-	-	-	-	-	1	Covered	T8,T29,T30
StableSt	-	-	-	-	-	-	0	Covered	T8,T29,T30
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	2934	0	0
CntIncr_A	7650645	100683	0	0
CntNoWrap_A	7650645	6982047	0	0
DetectStDropOut_A	7650645	404	0	0
DetectedOut_A	7650645	69079	0	0
DetectedPulseOut_A	7650645	857	0	0
DisabledIdleSt_A	7650645	6544723	0	0
DisabledNoDetection_A	7650645	6546974	0	0
EnterDebounceSt_A	7650645	1475	0	0
EnterDetectSt_A	7650645	1459	0	0
EnterStableSt_A	7650645	857	0	0
PulseIsPulse_A	7650645	857	0	0
StayInStableSt	7650645	68121	0	0
gen_high_event_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	732	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	2934	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	52	0	0
T12	0	24	0	0
T19	5999	12	0	0
T24	702	0	0	0
T29	0	30	0	0
T30	0	10	0	0
T31	0	12	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	10	0	0
T66	0	6	0	0
T67	0	18	0	0
T68	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	100683	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	1976	0	0
T12	0	1502	0	0
T19	5999	275	0	0
T24	702	0	0	0
T29	0	1005	0	0
T30	0	265	0	0
T31	0	324	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	455	0	0
T66	0	231	0	0
T67	0	437	0	0
T68	0	368	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6982047	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	404	0	0
T51	0	1	0	0
T67	5066	9	0	0
T83	641	0	0	0
T84	751	0	0	0
T86	0	21	0	0
T89	0	8	0	0
T91	0	16	0	0
T151	595	0	0	0
T161	0	24	0	0
T220	0	15	0	0
T223	0	12	0	0
T224	0	5	0	0
T225	0	7	0	0
T226	422	0	0	0
T227	3419	0	0	0
T228	426	0	0	0
T229	491	0	0	0
T230	25760	0	0	0
T231	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	69079	0	0
T8	25484	168	0	0
T9	5119	0	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T29	0	192	0	0
T30	0	42	0	0
T31	0	334	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	234	0	0
T66	0	40	0	0
T68	0	914	0	0
T73	0	181	0	0
T88	0	149	0	0
T109	0	68	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	857	0	0
T8	25484	26	0	0
T9	5119	0	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T29	0	15	0	0
T30	0	5	0	0
T31	0	6	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T68	0	8	0	0
T73	0	4	0	0
T88	0	3	0	0
T109	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6544723	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6546974	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1475	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	26	0	0
T12	0	12	0	0
T19	5999	6	0	0
T24	702	0	0	0
T29	0	15	0	0
T30	0	5	0	0
T31	0	6	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T67	0	9	0	0
T68	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1459	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	26	0	0
T12	0	12	0	0
T19	5999	6	0	0
T24	702	0	0	0
T29	0	15	0	0
T30	0	5	0	0
T31	0	6	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T67	0	9	0	0
T68	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	857	0	0
T8	25484	26	0	0
T9	5119	0	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T29	0	15	0	0
T30	0	5	0	0
T31	0	6	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T68	0	8	0	0
T73	0	4	0	0
T88	0	3	0	0
T109	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	857	0	0
T8	25484	26	0	0
T9	5119	0	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T29	0	15	0	0
T30	0	5	0	0
T31	0	6	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T68	0	8	0	0
T73	0	4	0	0
T88	0	3	0	0
T109	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	68121	0	0
T8	25484	142	0	0
T9	5119	0	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T29	0	176	0	0
T30	0	37	0	0
T31	0	327	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	229	0	0
T66	0	37	0	0
T68	0	903	0	0
T73	0	177	0	0
T88	0	145	0	0
T109	0	63	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	732	0	0
T8	25484	10	0	0
T9	5119	0	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T29	0	14	0	0
T30	0	5	0	0
T31	0	5	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	5	0	0
T66	0	3	0	0
T68	0	5	0	0
T73	0	4	0	0
T88	0	2	0	0
T109	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T13,T19
1	1	Covered	T1,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T9,T32,T70
1	0	Covered	T51,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T29
0	1	Covered	T1,T7,T29
1	0	Covered	T51

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T29
1	-	Covered	T1,T7,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T9
DetectSt	168	Covered	T1,T7,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T7,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T9
DebounceSt->IdleSt	163	Covered	T7,T9,T85
DetectSt->IdleSt	186	Covered	T9,T32,T70
DetectSt->StableSt	191	Covered	T1,T7,T29
IdleSt->DebounceSt	148	Covered	T1,T7,T9
StableSt->IdleSt	206	Covered	T1,T7,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T9,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T32,T70
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T29
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T29
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	760	0	0
CntIncr_A	7650645	39536	0	0
CntNoWrap_A	7650645	6984221	0	0
DetectStDropOut_A	7650645	66	0	0
DetectedOut_A	7650645	12642	0	0
DetectedPulseOut_A	7650645	290	0	0
DisabledIdleSt_A	7650645	6628887	0	0
DisabledNoDetection_A	7650645	6630677	0	0
EnterDebounceSt_A	7650645	401	0	0
EnterDetectSt_A	7650645	361	0	0
EnterStableSt_A	7650645	290	0	0
PulseIsPulse_A	7650645	290	0	0
StayInStableSt	7650645	12315	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	250	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	760	0	0
T1	17251	6	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	23	0	0
T9	0	26	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	2	0	0
T31	0	2	0	0
T32	0	6	0	0
T42	0	2	0	0
T69	0	4	0	0
T102	0	4	0	0
T104	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	39536	0	0
T1	17251	423	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	1054	0	0
T9	0	1305	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	61	0	0
T31	0	63	0	0
T32	0	372	0	0
T42	0	98	0	0
T69	0	140	0	0
T102	0	154	0	0
T104	0	765	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984221	0	0
T1	17251	11164	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	66	0	0
T9	5119	12	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T32	0	3	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T70	0	3	0	0
T81	0	5	0	0
T87	0	2	0	0
T95	0	1	0	0
T232	0	3	0	0
T233	0	10	0	0
T234	0	1	0	0
T235	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	12642	0	0
T1	17251	81	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	86	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	89	0	0
T31	0	66	0	0
T42	0	7	0	0
T69	0	24	0	0
T70	0	436	0	0
T85	0	586	0	0
T102	0	100	0	0
T104	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	290	0	0
T1	17251	3	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	11	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T42	0	1	0	0
T69	0	2	0	0
T70	0	6	0	0
T85	0	6	0	0
T102	0	2	0	0
T104	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6628887	0	0
T1	17251	9301	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6630677	0	0
T1	17251	9317	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	401	0	0
T1	17251	3	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	12	0	0
T9	0	14	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T42	0	1	0	0
T69	0	2	0	0
T102	0	2	0	0
T104	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	361	0	0
T1	17251	3	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	11	0	0
T9	0	12	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T42	0	1	0	0
T69	0	2	0	0
T102	0	2	0	0
T104	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	290	0	0
T1	17251	3	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	11	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T42	0	1	0	0
T69	0	2	0	0
T70	0	6	0	0
T85	0	6	0	0
T102	0	2	0	0
T104	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	290	0	0
T1	17251	3	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	11	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T42	0	1	0	0
T69	0	2	0	0
T70	0	6	0	0
T85	0	6	0	0
T102	0	2	0	0
T104	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	12315	0	0
T1	17251	78	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	75	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	88	0	0
T31	0	65	0	0
T42	0	6	0	0
T69	0	22	0	0
T70	0	430	0	0
T85	0	580	0	0
T102	0	98	0	0
T104	0	97	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	250	0	0
T1	17251	3	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	11	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T42	0	1	0	0
T69	0	2	0	0
T70	0	6	0	0
T85	0	6	0	0
T102	0	2	0	0
T104	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T8,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T8,T12
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T8,T12
0	1	Covered	T67,T68,T88
1	0	Covered	T68,T88,T91

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T8,T12
0	1	Covered	T19,T8,T12
1	0	Covered	T76,T236,T237

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T8,T12
1	-	Covered	T19,T8,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T8,T12
DetectSt	168	Covered	T19,T8,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T19,T8,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T8,T12
DebounceSt->IdleSt	163	Covered	T51,T218,T219
DetectSt->IdleSt	186	Covered	T67,T68,T88
DetectSt->StableSt	191	Covered	T19,T8,T12
IdleSt->DebounceSt	148	Covered	T19,T8,T12
StableSt->IdleSt	206	Covered	T19,T8,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T8,T12
0	1	Covered	T19,T8,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T8,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T19,T8,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T67,T68,T88
DetectSt	-	-	-	-	0	1	-	Covered	T19,T8,T12
DetectSt	-	-	-	-	0	0	-	Covered	T19,T8,T12
StableSt	-	-	-	-	-	-	1	Covered	T19,T8,T12
StableSt	-	-	-	-	-	-	0	Covered	T19,T8,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	3076	0	0
CntIncr_A	7650645	99231	0	0
CntNoWrap_A	7650645	6981905	0	0
DetectStDropOut_A	7650645	343	0	0
DetectedOut_A	7650645	90434	0	0
DetectedPulseOut_A	7650645	1003	0	0
DisabledIdleSt_A	7650645	6526408	0	0
DisabledNoDetection_A	7650645	6528607	0	0
EnterDebounceSt_A	7650645	1547	0	0
EnterDetectSt_A	7650645	1530	0	0
EnterStableSt_A	7650645	1003	0	0
PulseIsPulse_A	7650645	1003	0	0
StayInStableSt	7650645	89276	0	0
gen_high_event_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	812	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3076	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	34	0	0
T12	0	50	0	0
T19	5999	66	0	0
T24	702	0	0	0
T29	0	54	0	0
T30	0	58	0	0
T31	0	14	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	20	0	0
T66	0	52	0	0
T67	0	10	0	0
T68	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	99231	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	1105	0	0
T12	0	1750	0	0
T19	5999	792	0	0
T24	702	0	0	0
T29	0	1161	0	0
T30	0	1073	0	0
T31	0	364	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	710	0	0
T66	0	1222	0	0
T67	0	240	0	0
T68	0	473	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6981905	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	343	0	0
T51	0	1	0	0
T67	5066	5	0	0
T68	0	5	0	0
T83	641	0	0	0
T84	751	0	0	0
T88	0	6	0	0
T89	0	26	0	0
T91	0	14	0	0
T151	595	0	0	0
T161	0	25	0	0
T220	0	12	0	0
T223	0	3	0	0
T225	0	13	0	0
T226	422	0	0	0
T227	3419	0	0	0
T228	426	0	0	0
T229	491	0	0	0
T230	25760	0	0	0
T231	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	90434	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	2594	0	0
T12	0	3076	0	0
T19	5999	1772	0	0
T24	702	0	0	0
T29	0	1650	0	0
T30	0	2865	0	0
T31	0	497	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	1586	0	0
T66	0	1659	0	0
T73	0	1610	0	0
T109	0	1821	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1003	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	17	0	0
T12	0	25	0	0
T19	5999	33	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	29	0	0
T31	0	7	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	10	0	0
T66	0	26	0	0
T73	0	17	0	0
T109	0	19	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6526408	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6528607	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1547	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	17	0	0
T12	0	25	0	0
T19	5999	33	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	29	0	0
T31	0	7	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	10	0	0
T66	0	26	0	0
T67	0	5	0	0
T68	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1530	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	17	0	0
T12	0	25	0	0
T19	5999	33	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	29	0	0
T31	0	7	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	10	0	0
T66	0	26	0	0
T67	0	5	0	0
T68	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1003	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	17	0	0
T12	0	25	0	0
T19	5999	33	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	29	0	0
T31	0	7	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	10	0	0
T66	0	26	0	0
T73	0	17	0	0
T109	0	19	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1003	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	17	0	0
T12	0	25	0	0
T19	5999	33	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	29	0	0
T31	0	7	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	10	0	0
T66	0	26	0	0
T73	0	17	0	0
T109	0	19	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	89276	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	2570	0	0
T12	0	3051	0	0
T19	5999	1739	0	0
T24	702	0	0	0
T29	0	1621	0	0
T30	0	2830	0	0
T31	0	488	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	1573	0	0
T66	0	1633	0	0
T73	0	1592	0	0
T109	0	1798	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	812	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	10	0	0
T12	0	25	0	0
T19	5999	33	0	0
T24	702	0	0	0
T29	0	25	0	0
T30	0	23	0	0
T31	0	5	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	7	0	0
T66	0	26	0	0
T73	0	16	0	0
T109	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T19,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T19,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Covered	T1,T13,T19
1	1	Covered	T1,T19,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T9,T69,T102
1	0	Covered	T51,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T12
1	0	Covered	T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T8
1	-	Covered	T1,T7,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T7
DetectSt	168	Covered	T1,T7,T8
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T8
DebounceSt->IdleSt	163	Covered	T19,T32,T30
DetectSt->IdleSt	186	Covered	T9,T69,T102
DetectSt->StableSt	191	Covered	T1,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T19,T7
StableSt->IdleSt	206	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T7
0	1	Covered	T1,T19,T7
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T32,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T7
DetectSt	-	-	-	-	1	-	-	Covered	T9,T69,T102
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	1022	0	0
CntIncr_A	7650645	53371	0	0
CntNoWrap_A	7650645	6983959	0	0
DetectStDropOut_A	7650645	45	0	0
DetectedOut_A	7650645	19754	0	0
DetectedPulseOut_A	7650645	436	0	0
DisabledIdleSt_A	7650645	6607911	0	0
DisabledNoDetection_A	7650645	6609642	0	0
EnterDebounceSt_A	7650645	538	0	0
EnterDetectSt_A	7650645	485	0	0
EnterStableSt_A	7650645	436	0	0
PulseIsPulse_A	7650645	436	0	0
StayInStableSt	7650645	19272	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	386	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1022	0	0
T1	17251	2	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	6	0	0
T8	0	10	0	0
T9	0	2	0	0
T12	0	10	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	1	0	0
T29	0	2	0	0
T30	0	13	0	0
T32	0	21	0	0
T69	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	53371	0	0
T1	17251	162	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	171	0	0
T8	0	395	0	0
T9	0	99	0	0
T12	0	340	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	11	0	0
T29	0	54	0	0
T30	0	429	0	0
T32	0	810	0	0
T69	0	164	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6983959	0	0
T1	17251	11168	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	45	0	0
T9	5119	1	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T23	933	0	0	0
T42	0	1	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T69	0	2	0	0
T70	0	3	0	0
T102	0	1	0	0
T104	0	9	0	0
T238	0	9	0	0
T239	0	1	0	0
T240	0	5	0	0
T241	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	19754	0	0
T1	17251	7	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	129	0	0
T8	0	293	0	0
T12	0	475	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	96	0	0
T30	0	370	0	0
T31	0	80	0	0
T32	0	402	0	0
T65	0	52	0	0
T85	0	178	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	436	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	3	0	0
T8	0	5	0	0
T12	0	5	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	9	0	0
T65	0	1	0	0
T85	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6607911	0	0
T1	17251	9301	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6609642	0	0
T1	17251	9317	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	538	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	3	0	0
T8	0	5	0	0
T9	0	1	0	0
T12	0	5	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	1	0	0
T29	0	1	0	0
T30	0	7	0	0
T32	0	12	0	0
T69	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	485	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	3	0	0
T8	0	5	0	0
T9	0	1	0	0
T12	0	5	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T32	0	9	0	0
T69	0	2	0	0
T102	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	436	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	3	0	0
T8	0	5	0	0
T12	0	5	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	9	0	0
T65	0	1	0	0
T85	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	436	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	3	0	0
T8	0	5	0	0
T12	0	5	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	9	0	0
T65	0	1	0	0
T85	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	19272	0	0
T1	17251	6	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	126	0	0
T8	0	283	0	0
T12	0	470	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	95	0	0
T30	0	364	0	0
T31	0	79	0	0
T32	0	393	0	0
T65	0	50	0	0
T85	0	169	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	386	0	0
T1	17251	1	0	0
T2	1263	0	0	0
T3	681	0	0	0
T7	0	3	0	0
T12	0	5	0	0
T13	8419	0	0	0
T14	439	0	0	0
T15	422	0	0	0
T16	674	0	0	0
T17	502	0	0	0
T18	492	0	0	0
T19	5999	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	9	0	0
T66	0	2	0	0
T85	0	9	0	0
T242	0	6	0	0