Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T19,T8,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T19,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T8,T12
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T8,T12
0	1	Covered	T8,T67,T109
1	0	Covered	T8,T109,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T12,T29
0	1	Covered	T19,T12,T29
1	0	Covered	T243

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T12,T29
1	-	Covered	T19,T12,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T8,T12
DetectSt	168	Covered	T19,T8,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T19,T12,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T8,T12
DebounceSt->IdleSt	163	Covered	T51,T218,T219
DetectSt->IdleSt	186	Covered	T8,T67,T109
DetectSt->StableSt	191	Covered	T19,T12,T29
IdleSt->DebounceSt	148	Covered	T19,T8,T12
StableSt->IdleSt	206	Covered	T19,T12,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T8,T12
0	1	Covered	T19,T8,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T8,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T19,T8,T12
IdleSt	0	-	-	-	-	-	-	Covered	T19,T8,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T8,T12
DetectSt	-	-	-	-	1	-	-	Covered	T8,T67,T109
DetectSt	-	-	-	-	0	1	-	Covered	T19,T12,T29
DetectSt	-	-	-	-	0	0	-	Covered	T19,T8,T12
StableSt	-	-	-	-	-	-	1	Covered	T19,T12,T29
StableSt	-	-	-	-	-	-	0	Covered	T19,T12,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	3184	0	0
CntIncr_A	7650645	113242	0	0
CntNoWrap_A	7650645	6981797	0	0
DetectStDropOut_A	7650645	336	0	0
DetectedOut_A	7650645	81226	0	0
DetectedPulseOut_A	7650645	970	0	0
DisabledIdleSt_A	7650645	6531284	0	0
DisabledNoDetection_A	7650645	6533500	0	0
EnterDebounceSt_A	7650645	1600	0	0
EnterDetectSt_A	7650645	1584	0	0
EnterStableSt_A	7650645	970	0	0
PulseIsPulse_A	7650645	970	0	0
StayInStableSt	7650645	80117	0	0
gen_high_event_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	827	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	3184	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	60	0	0
T12	0	34	0	0
T19	5999	52	0	0
T24	702	0	0	0
T29	0	54	0	0
T30	0	12	0	0
T31	0	56	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	42	0	0
T66	0	24	0	0
T67	0	34	0	0
T68	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	113242	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	2471	0	0
T12	0	1071	0	0
T19	5999	936	0	0
T24	702	0	0	0
T29	0	1134	0	0
T30	0	228	0	0
T31	0	1456	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	1491	0	0
T66	0	588	0	0
T67	0	824	0	0
T68	0	440	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6981797	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	336	0	0
T8	25484	18	0	0
T9	5119	0	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	12802	0	0	0
T51	0	1	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T67	0	17	0	0
T86	0	10	0	0
T109	0	3	0	0
T161	0	12	0	0
T220	0	15	0	0
T223	0	9	0	0
T244	0	10	0	0
T245	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	81226	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	0	0	0
T12	0	1250	0	0
T19	5999	311	0	0
T24	702	0	0	0
T29	0	1677	0	0
T30	0	141	0	0
T31	0	1982	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	2785	0	0
T66	0	908	0	0
T68	0	985	0	0
T73	0	769	0	0
T88	0	2978	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	970	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	0	0	0
T12	0	17	0	0
T19	5999	26	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	6	0	0
T31	0	28	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	21	0	0
T66	0	12	0	0
T68	0	11	0	0
T73	0	10	0	0
T88	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6531284	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6533500	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1600	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	30	0	0
T12	0	17	0	0
T19	5999	26	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	6	0	0
T31	0	28	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	21	0	0
T66	0	12	0	0
T67	0	17	0	0
T68	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	1584	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	30	0	0
T12	0	17	0	0
T19	5999	26	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	6	0	0
T31	0	28	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	21	0	0
T66	0	12	0	0
T67	0	17	0	0
T68	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	970	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	0	0	0
T12	0	17	0	0
T19	5999	26	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	6	0	0
T31	0	28	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	21	0	0
T66	0	12	0	0
T68	0	11	0	0
T73	0	10	0	0
T88	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	970	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	0	0	0
T12	0	17	0	0
T19	5999	26	0	0
T24	702	0	0	0
T29	0	27	0	0
T30	0	6	0	0
T31	0	28	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	21	0	0
T66	0	12	0	0
T68	0	11	0	0
T73	0	10	0	0
T88	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	80117	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	0	0	0
T12	0	1232	0	0
T19	5999	285	0	0
T24	702	0	0	0
T29	0	1648	0	0
T30	0	135	0	0
T31	0	1952	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	2758	0	0
T66	0	894	0	0
T68	0	972	0	0
T73	0	758	0	0
T88	0	2935	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	827	0	0
T6	2309	0	0	0
T7	27736	0	0	0
T8	25484	0	0	0
T12	0	16	0	0
T19	5999	26	0	0
T24	702	0	0	0
T29	0	25	0	0
T30	0	6	0	0
T31	0	26	0	0
T46	502	0	0	0
T47	641	0	0	0
T48	422	0	0	0
T49	406	0	0	0
T50	402	0	0	0
T65	0	15	0	0
T66	0	10	0	0
T68	0	9	0	0
T73	0	9	0	0
T88	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Covered	T1,T13,T19
1	1	Covered	T7,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T12
0	1	Covered	T7,T9,T104
1	0	Covered	T51,T72

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T32,T69
0	1	Covered	T12,T32,T69
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T32,T69
1	-	Covered	T12,T32,T69

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T12
DetectSt	168	Covered	T7,T9,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T12,T32,T69

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T12
DebounceSt->IdleSt	163	Covered	T9,T85,T70
DetectSt->IdleSt	186	Covered	T7,T9,T104
DetectSt->StableSt	191	Covered	T12,T32,T69
IdleSt->DebounceSt	148	Covered	T7,T9,T12
StableSt->IdleSt	206	Covered	T12,T32,T69

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T12
0	1	Covered	T7,T9,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T51,T72
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T85,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T7,T9,T104
DetectSt	-	-	-	-	0	1	-	Covered	T12,T32,T69
DetectSt	-	-	-	-	0	0	-	Covered	T7,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T12,T32,T69
StableSt	-	-	-	-	-	-	0	Covered	T12,T32,T69
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7650645	954	0	0
CntIncr_A	7650645	48652	0	0
CntNoWrap_A	7650645	6984027	0	0
DetectStDropOut_A	7650645	82	0	0
DetectedOut_A	7650645	17860	0	0
DetectedPulseOut_A	7650645	373	0	0
DisabledIdleSt_A	7650645	6617635	0	0
DisabledNoDetection_A	7650645	6619390	0	0
EnterDebounceSt_A	7650645	496	0	0
EnterDetectSt_A	7650645	458	0	0
EnterStableSt_A	7650645	373	0	0
PulseIsPulse_A	7650645	373	0	0
StayInStableSt	7650645	17438	0	0
gen_high_level_sva.HighLevelEvent_A	7650645	6987427	0	0
gen_not_sticky_sva.StableStDropOut_A	7650645	322	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	954	0	0
T7	27736	18	0	0
T8	25484	0	0	0
T9	5119	9	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	0	2	0	0
T31	0	2	0	0
T32	0	12	0	0
T42	0	2	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	12	0	0
T69	0	2	0	0
T85	0	15	0	0
T104	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	48652	0	0
T7	27736	913	0	0
T8	25484	0	0	0
T9	5119	449	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	0	106	0	0
T31	0	60	0	0
T32	0	684	0	0
T42	0	80	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	336	0	0
T69	0	75	0	0
T85	0	1098	0	0
T104	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6984027	0	0
T1	17251	11170	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	82	0	0
T7	27736	9	0	0
T8	25484	0	0	0
T9	5119	4	0	0
T10	673	0	0	0
T11	1698	0	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T94	0	1	0	0
T96	0	9	0	0
T99	0	4	0	0
T104	0	1	0	0
T216	0	10	0	0
T232	0	1	0	0
T235	0	10	0	0
T246	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	17860	0	0
T12	12802	58	0	0
T23	933	0	0	0
T25	733	0	0	0
T29	14170	0	0	0
T31	0	67	0	0
T32	0	72	0	0
T40	466	0	0	0
T42	0	25	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T65	0	560	0	0
T66	0	108	0	0
T69	0	7	0	0
T70	0	361	0	0
T85	0	796	0	0
T115	404	0	0	0
T116	421	0	0	0
T230	0	180	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	373	0	0
T12	12802	1	0	0
T23	933	0	0	0
T25	733	0	0	0
T29	14170	0	0	0
T31	0	1	0	0
T32	0	6	0	0
T40	466	0	0	0
T42	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T65	0	6	0	0
T66	0	2	0	0
T69	0	1	0	0
T70	0	9	0	0
T85	0	6	0	0
T115	404	0	0	0
T116	421	0	0	0
T230	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6617635	0	0
T1	17251	9301	0	0
T2	1263	862	0	0
T3	681	280	0	0
T4	495	94	0	0
T5	498	97	0	0
T13	8419	4	0	0
T14	439	38	0	0
T15	422	21	0	0
T16	674	273	0	0
T17	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6619390	0	0
T1	17251	9317	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	496	0	0
T7	27736	9	0	0
T8	25484	0	0	0
T9	5119	5	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	0	1	0	0
T31	0	1	0	0
T32	0	6	0	0
T42	0	1	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	6	0	0
T69	0	1	0	0
T85	0	9	0	0
T104	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	458	0	0
T7	27736	9	0	0
T8	25484	0	0	0
T9	5119	4	0	0
T10	673	0	0	0
T11	1698	0	0	0
T12	0	1	0	0
T31	0	1	0	0
T32	0	6	0	0
T42	0	1	0	0
T53	481	0	0	0
T58	523	0	0	0
T59	522	0	0	0
T60	514	0	0	0
T61	502	0	0	0
T65	0	6	0	0
T69	0	1	0	0
T85	0	6	0	0
T104	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	373	0	0
T12	12802	1	0	0
T23	933	0	0	0
T25	733	0	0	0
T29	14170	0	0	0
T31	0	1	0	0
T32	0	6	0	0
T40	466	0	0	0
T42	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T65	0	6	0	0
T66	0	2	0	0
T69	0	1	0	0
T70	0	9	0	0
T85	0	6	0	0
T115	404	0	0	0
T116	421	0	0	0
T230	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	373	0	0
T12	12802	1	0	0
T23	933	0	0	0
T25	733	0	0	0
T29	14170	0	0	0
T31	0	1	0	0
T32	0	6	0	0
T40	466	0	0	0
T42	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T65	0	6	0	0
T66	0	2	0	0
T69	0	1	0	0
T70	0	9	0	0
T85	0	6	0	0
T115	404	0	0	0
T116	421	0	0	0
T230	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	17438	0	0
T12	12802	57	0	0
T23	933	0	0	0
T25	733	0	0	0
T29	14170	0	0	0
T31	0	66	0	0
T32	0	66	0	0
T40	466	0	0	0
T42	0	24	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T65	0	548	0	0
T66	0	106	0	0
T69	0	6	0	0
T70	0	352	0	0
T85	0	790	0	0
T115	404	0	0	0
T116	421	0	0	0
T230	0	178	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	6987427	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7650645	322	0	0
T12	12802	1	0	0
T23	933	0	0	0
T25	733	0	0	0
T29	14170	0	0	0
T31	0	1	0	0
T32	0	6	0	0
T40	466	0	0	0
T42	0	1	0	0
T52	1775	0	0	0
T54	993	0	0	0
T62	525	0	0	0
T66	0	2	0	0
T68	0	2	0	0
T69	0	1	0	0
T70	0	9	0	0
T85	0	6	0	0
T115	404	0	0	0
T116	421	0	0	0
T230	0	2	0	0