Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1389473439	10838	0	0
auto_block_debounce_ctl_rd_A	1389473439	2284	0	0
auto_block_out_ctl_rd_A	1389473439	2941	0	0
com_det_ctl_0_rd_A	1389473439	4392	0	0
com_det_ctl_1_rd_A	1389473439	4503	0	0
com_det_ctl_2_rd_A	1389473439	4309	0	0
com_det_ctl_3_rd_A	1389473439	4449	0	0
com_out_ctl_0_rd_A	1389473439	5044	0	0
com_out_ctl_1_rd_A	1389473439	5055	0	0
com_out_ctl_2_rd_A	1389473439	4784	0	0
com_out_ctl_3_rd_A	1389473439	4901	0	0
com_pre_det_ctl_0_rd_A	1389473439	1913	0	0
com_pre_det_ctl_1_rd_A	1389473439	1770	0	0
com_pre_det_ctl_2_rd_A	1389473439	1781	0	0
com_pre_det_ctl_3_rd_A	1389473439	1746	0	0
com_pre_sel_ctl_0_rd_A	1389473439	5160	0	0
com_pre_sel_ctl_1_rd_A	1389473439	5049	0	0
com_pre_sel_ctl_2_rd_A	1389473439	4940	0	0
com_pre_sel_ctl_3_rd_A	1389473439	4894	0	0
com_sel_ctl_0_rd_A	1389473439	4897	0	0
com_sel_ctl_1_rd_A	1389473439	4864	0	0
com_sel_ctl_2_rd_A	1389473439	5112	0	0
com_sel_ctl_3_rd_A	1389473439	5094	0	0
ec_rst_ctl_rd_A	1389473439	2865	0	0
intr_enable_rd_A	1389473439	2568	0	0
key_intr_ctl_rd_A	1389473439	3790	0	0
key_intr_debounce_ctl_rd_A	1389473439	1817	0	0
key_invert_ctl_rd_A	1389473439	4819	0	0
pin_allowed_ctl_rd_A	1389473439	7387	0	0
pin_out_ctl_rd_A	1389473439	5482	0	0
pin_out_value_rd_A	1389473439	5305	0	0
regwen_rd_A	1389473439	2302	0	0
ulp_ac_debounce_ctl_rd_A	1389473439	1993	0	0
ulp_ctl_rd_A	1389473439	1819	0	0
ulp_lid_debounce_ctl_rd_A	1389473439	1937	0	0
ulp_pwrb_debounce_ctl_rd_A	1389473439	2023	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	10838	0	0
T1	642925	8	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	16	0	0
T35	0	13	0	0
T38	0	7	0	0
T39	0	6	0	0
T42	0	2	0	0
T45	0	9	0	0
T70	0	9	0	0
T133	0	10	0	0
T153	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2284	0	0
T6	110829	0	0	0
T16	47214	13	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	0	0	0
T33	0	7	0	0
T38	0	23	0	0
T41	0	17	0	0
T43	0	15	0	0
T45	0	20	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T70	0	12	0	0
T83	0	9	0	0
T264	0	7	0	0
T265	0	10	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2941	0	0
T6	110829	0	0	0
T16	47214	8	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	0	0	0
T33	0	1	0	0
T36	0	5	0	0
T38	0	11	0	0
T41	0	3	0	0
T43	0	17	0	0
T45	0	37	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T70	0	11	0	0
T83	0	8	0	0
T264	0	5	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4392	0	0
T7	540858	58	0	0
T8	637114	0	0	0
T9	250838	45	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	32	0	0
T38	0	12	0	0
T45	0	8	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	33	0	0
T69	0	26	0	0
T85	0	93	0	0
T104	0	42	0	0
T242	0	51	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4503	0	0
T7	540858	41	0	0
T8	637114	0	0	0
T9	250838	42	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	46	0	0
T33	0	1	0	0
T38	0	12	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	32	0	0
T69	0	67	0	0
T85	0	52	0	0
T104	0	55	0	0
T242	0	39	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4309	0	0
T7	540858	53	0	0
T8	637114	0	0	0
T9	250838	16	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	21	0	0
T33	0	6	0	0
T38	0	13	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	31	0	0
T69	0	54	0	0
T85	0	42	0	0
T104	0	30	0	0
T242	0	22	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4449	0	0
T7	540858	39	0	0
T8	637114	0	0	0
T9	250838	32	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	31	0	0
T33	0	5	0	0
T38	0	31	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	59	0	0
T69	0	52	0	0
T85	0	54	0	0
T104	0	43	0	0
T242	0	20	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5044	0	0
T7	540858	29	0	0
T8	637114	0	0	0
T9	250838	22	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	35	0	0
T33	0	18	0	0
T38	0	14	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	47	0	0
T69	0	41	0	0
T85	0	84	0	0
T104	0	44	0	0
T242	0	42	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5055	0	0
T7	540858	57	0	0
T8	637114	0	0	0
T9	250838	56	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	25	0	0
T33	0	8	0	0
T38	0	13	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	33	0	0
T69	0	49	0	0
T85	0	54	0	0
T104	0	41	0	0
T242	0	45	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4784	0	0
T7	540858	62	0	0
T8	637114	0	0	0
T9	250838	45	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	15	0	0
T33	0	10	0	0
T38	0	6	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	66	0	0
T69	0	39	0	0
T85	0	79	0	0
T104	0	59	0	0
T242	0	34	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4901	0	0
T7	540858	39	0	0
T8	637114	0	0	0
T9	250838	21	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	35	0	0
T33	0	5	0	0
T38	0	18	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	46	0	0
T69	0	28	0	0
T85	0	67	0	0
T104	0	42	0	0
T242	0	47	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1913	0	0
T30	956487	0	0	0
T38	295736	20	0	0
T41	294724	0	0	0
T45	0	29	0	0
T63	55319	0	0	0
T69	113720	0	0	0
T70	0	9	0	0
T82	61104	0	0	0
T99	0	43	0	0
T100	125823	0	0	0
T101	319743	0	0	0
T102	119582	0	0	0
T118	0	17	0	0
T131	0	24	0	0
T147	0	10	0	0
T209	50979	0	0	0
T266	0	1	0	0
T267	0	10	0	0
T268	0	31	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1770	0	0
T30	956487	0	0	0
T33	0	9	0	0
T38	295736	10	0	0
T41	294724	0	0	0
T63	55319	0	0	0
T69	113720	0	0	0
T82	61104	0	0	0
T99	0	18	0	0
T100	125823	0	0	0
T101	319743	0	0	0
T102	119582	0	0	0
T118	0	21	0	0
T131	0	10	0	0
T147	0	11	0	0
T209	50979	0	0	0
T266	0	3	0	0
T267	0	10	0	0
T268	0	36	0	0
T269	0	17	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1781	0	0
T30	956487	0	0	0
T33	0	4	0	0
T38	295736	14	0	0
T41	294724	0	0	0
T45	0	10	0	0
T63	55319	0	0	0
T69	113720	0	0	0
T70	0	7	0	0
T82	61104	0	0	0
T99	0	35	0	0
T100	125823	0	0	0
T101	319743	0	0	0
T102	119582	0	0	0
T118	0	10	0	0
T131	0	12	0	0
T147	0	17	0	0
T209	50979	0	0	0
T266	0	2	0	0
T267	0	7	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1746	0	0
T30	956487	0	0	0
T33	0	5	0	0
T38	295736	20	0	0
T41	294724	0	0	0
T63	55319	0	0	0
T69	113720	0	0	0
T70	0	1	0	0
T82	61104	0	0	0
T99	0	35	0	0
T100	125823	0	0	0
T101	319743	0	0	0
T102	119582	0	0	0
T118	0	31	0	0
T131	0	15	0	0
T147	0	15	0	0
T209	50979	0	0	0
T267	0	9	0	0
T268	0	30	0	0
T269	0	30	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5160	0	0
T7	540858	40	0	0
T8	637114	0	0	0
T9	250838	52	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	30	0	0
T33	0	2	0	0
T38	0	9	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	72	0	0
T69	0	60	0	0
T85	0	74	0	0
T104	0	43	0	0
T242	0	27	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5049	0	0
T7	540858	41	0	0
T8	637114	0	0	0
T9	250838	31	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	51	0	0
T38	0	22	0	0
T45	0	13	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	44	0	0
T69	0	31	0	0
T85	0	59	0	0
T104	0	52	0	0
T242	0	40	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4940	0	0
T7	540858	46	0	0
T8	637114	0	0	0
T9	250838	40	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	38	0	0
T33	0	1	0	0
T38	0	11	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	31	0	0
T69	0	45	0	0
T85	0	63	0	0
T104	0	47	0	0
T242	0	54	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4894	0	0
T7	540858	50	0	0
T8	637114	0	0	0
T9	250838	37	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	37	0	0
T33	0	10	0	0
T38	0	17	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	65	0	0
T69	0	32	0	0
T85	0	73	0	0
T104	0	33	0	0
T242	0	18	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4897	0	0
T7	540858	43	0	0
T8	637114	0	0	0
T9	250838	46	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	40	0	0
T33	0	9	0	0
T38	0	9	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	74	0	0
T69	0	53	0	0
T85	0	61	0	0
T104	0	44	0	0
T242	0	13	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4864	0	0
T7	540858	42	0	0
T8	637114	0	0	0
T9	250838	38	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	21	0	0
T33	0	3	0	0
T38	0	16	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	42	0	0
T69	0	29	0	0
T85	0	84	0	0
T104	0	37	0	0
T242	0	47	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5112	0	0
T7	540858	33	0	0
T8	637114	0	0	0
T9	250838	17	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	23	0	0
T38	0	17	0	0
T45	0	11	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	73	0	0
T69	0	58	0	0
T85	0	77	0	0
T104	0	42	0	0
T242	0	60	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5094	0	0
T7	540858	54	0	0
T8	637114	0	0	0
T9	250838	36	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	18	0	0
T33	0	5	0	0
T38	0	17	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	49	0	0
T69	0	46	0	0
T85	0	60	0	0
T104	0	46	0	0
T242	0	33	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2865	0	0
T7	540858	11	0	0
T8	637114	0	0	0
T9	250838	4	0	0
T10	47134	0	0	0
T11	60580	0	0	0
T30	0	16	0	0
T33	0	8	0	0
T38	0	27	0	0
T53	115668	0	0	0
T58	154315	0	0	0
T59	216646	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T65	0	30	0	0
T69	0	10	0	0
T85	0	43	0	0
T104	0	13	0	0
T242	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2568	0	0
T30	956487	0	0	0
T33	0	12	0	0
T38	295736	26	0	0
T41	294724	0	0	0
T43	0	11	0	0
T45	0	26	0	0
T63	55319	0	0	0
T69	113720	0	0	0
T70	0	17	0	0
T82	61104	0	0	0
T100	125823	0	0	0
T101	319743	0	0	0
T102	119582	0	0	0
T118	0	15	0	0
T131	0	11	0	0
T147	0	20	0	0
T209	50979	0	0	0
T266	0	19	0	0
T270	0	11	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	3790	0	0
T10	47134	3	0	0
T11	60580	0	0	0
T12	153627	0	0	0
T23	116678	0	0	0
T29	170043	0	0	0
T33	0	12	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	21	0	0
T45	0	18	0	0
T53	115668	0	0	0
T54	476918	0	0	0
T60	23131	0	0	0
T61	210758	0	0	0
T62	70861	0	0	0
T64	0	1	0	0
T70	0	5	0	0
T79	0	1	0	0
T271	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1817	0	0
T30	956487	0	0	0
T33	0	1	0	0
T38	295736	9	0	0
T41	294724	0	0	0
T45	0	12	0	0
T63	55319	0	0	0
T69	113720	0	0	0
T70	0	2	0	0
T82	61104	0	0	0
T99	0	34	0	0
T100	125823	0	0	0
T101	319743	0	0	0
T102	119582	0	0	0
T118	0	7	0	0
T131	0	8	0	0
T147	0	16	0	0
T209	50979	0	0	0
T266	0	10	0	0
T267	0	15	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	4819	0	0
T1	642925	0	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T4	66936	62	0	0
T5	54898	0	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T33	0	39	0	0
T36	0	59	0	0
T38	0	12	0	0
T45	0	196	0	0
T56	0	37	0	0
T70	0	7	0	0
T272	0	66	0	0
T273	0	54	0	0
T274	0	82	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7387	0	0
T6	110829	0	0	0
T17	238501	55	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	0	0	0
T33	0	82	0	0
T38	0	77	0	0
T45	0	250	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T61	0	59	0	0
T70	0	156	0	0
T100	0	74	0	0
T174	0	93	0	0
T275	0	31	0	0
T276	0	73	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5482	0	0
T6	110829	0	0	0
T17	238501	61	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	0	0	0
T33	0	70	0	0
T38	0	79	0	0
T45	0	242	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T61	0	87	0	0
T70	0	122	0	0
T100	0	62	0	0
T174	0	53	0	0
T275	0	17	0	0
T276	0	59	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5305	0	0
T6	110829	0	0	0
T17	238501	69	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	0	0	0
T33	0	98	0	0
T38	0	65	0	0
T45	0	252	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T61	0	78	0	0
T70	0	144	0	0
T100	0	71	0	0
T174	0	59	0	0
T275	0	55	0	0
T276	0	71	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2302	0	0
T30	956487	0	0	0
T33	0	11	0	0
T38	295736	13	0	0
T41	294724	0	0	0
T45	0	13	0	0
T63	55319	0	0	0
T69	113720	0	0	0
T70	0	3	0	0
T82	61104	0	0	0
T99	0	49	0	0
T100	125823	0	0	0
T101	319743	0	0	0
T102	119582	0	0	0
T118	0	23	0	0
T131	0	9	0	0
T147	0	14	0	0
T209	50979	0	0	0
T266	0	5	0	0
T267	0	15	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1993	0	0
T2	232720	2	0	0
T3	56736	0	0	0
T6	110829	0	0	0
T11	0	6	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	27	0	0
T38	0	29	0	0
T43	0	5	0	0
T45	0	13	0	0
T55	0	4	0	0
T70	0	9	0	0
T71	0	7	0	0
T112	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1819	0	0
T2	232720	9	0	0
T3	56736	0	0	0
T6	110829	0	0	0
T11	0	3	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	18	0	0
T38	0	9	0	0
T45	0	17	0	0
T70	0	6	0	0
T71	0	9	0	0
T112	0	4	0	0
T128	0	12	0	0
T277	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1937	0	0
T11	60580	7	0	0
T12	153627	0	0	0
T23	116678	0	0	0
T29	170043	0	0	0
T33	0	11	0	0
T38	0	16	0	0
T40	58318	0	0	0
T43	0	2	0	0
T45	0	22	0	0
T52	11938	0	0	0
T54	476918	0	0	0
T62	70861	0	0	0
T70	0	10	0	0
T71	0	14	0	0
T112	0	9	0	0
T115	101020	0	0	0
T116	210895	0	0	0
T128	0	2	0	0
T277	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2023	0	0
T2	232720	5	0	0
T3	56736	0	0	0
T6	110829	0	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	15	0	0
T38	0	19	0	0
T43	0	6	0	0
T45	0	19	0	0
T70	0	1	0	0
T71	0	9	0	0
T128	0	5	0	0
T147	0	21	0	0
T277	0	2	0	0