Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	104062827	0	0
DstReqKnown_A	268836096	239771298	0	0
SrcAckBusyChk_A	2147483647	118776	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	104062827	0	0
T1	10286800	860	0	0
T2	3723520	0	0	0
T3	907776	0	0	0
T4	66936	0	0	0
T5	54898	0	0	0
T6	1108290	1432	0	0
T7	4326864	14953	0	0
T8	5096912	14236	0	0
T9	0	2828	0	0
T12	0	1880	0	0
T13	1818576	0	0	0
T14	878400	0	0	0
T15	3343872	0	0	0
T16	849852	1549	0	0
T17	4293018	0	0	0
T18	2009502	0	0	0
T19	17998500	940	0	0
T24	843270	3797	0	0
T25	0	712	0	0
T29	0	3276	0	0
T30	0	11901	0	0
T32	0	10050	0	0
T36	0	3078	0	0
T39	0	1556	0	0
T40	0	444	0	0
T41	0	12875	0	0
T42	0	12647	0	0
T43	0	2781	0	0
T44	0	5587	0	0
T45	0	16950	0	0
T46	2510040	0	0	0
T47	545900	0	0	0
T48	2112270	0	0	0
T49	529030	0	0	0
T50	1544032	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	268836096	239771298	0	0
T1	586534	380426	0	0
T2	42942	29342	0	0
T3	23154	9554	0	0
T4	16830	3230	0	0
T5	16932	3332	0	0
T13	286246	646	0	0
T14	14926	1326	0	0
T15	14348	748	0	0
T16	22916	9316	0	0
T17	17068	3468	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118776	0	0
T1	10286800	7	0	0
T2	3723520	0	0	0
T3	907776	0	0	0
T4	66936	0	0	0
T5	54898	0	0	0
T6	1108290	1	0	0
T7	4326864	24	0	0
T8	5096912	18	0	0
T9	0	2	0	0
T12	0	4	0	0
T13	1818576	0	0	0
T14	878400	0	0	0
T15	3343872	0	0	0
T16	849852	7	0	0
T17	4293018	0	0	0
T18	2009502	0	0	0
T19	17998500	2	0	0
T24	843270	9	0	0
T25	0	6	0	0
T29	0	8	0	0
T30	0	7	0	0
T32	0	26	0	0
T36	0	7	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	8	0	0
T42	0	13	0	0
T43	0	8	0	0
T44	0	7	0	0
T45	0	21	0	0
T46	2510040	0	0	0
T47	545900	0	0	0
T48	2112270	0	0	0
T49	529030	0	0	0
T50	1544032	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	21859450	21810048	0	0
T2	7912480	7910678	0	0
T3	1929024	1926440	0	0
T4	2275824	2273988	0	0
T5	1866532	1864322	0	0
T13	3864474	3859102	0	0
T14	1866600	1864628	0	0
T15	7105728	7103042	0	0
T16	1605276	1602114	0	0
T17	8109034	8106892	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T51,T26,T20
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1113472	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1235	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1113472	0	0
T1	642925	502	0	0
T2	232720	1426	0	0
T3	56736	492	0	0
T7	0	7179	0	0
T8	0	2681	0	0
T9	0	16402	0	0
T11	0	356	0	0
T12	0	477	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T29	0	1191	0	0
T52	0	95	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1235	0	0
T1	642925	4	0	0
T2	232720	1	0	0
T3	56736	1	0	0
T7	0	11	0	0
T8	0	3	0	0
T9	0	10	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T29	0	3	0	0
T52	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1783832	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	2034	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1783832	0	0
T1	642925	437	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1428	0	0
T7	0	6730	0	0
T8	0	6230	0	0
T9	0	1361	0	0
T12	0	882	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	441	0	0
T47	0	234	0	0
T53	0	714	0	0
T54	0	1897	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2034	0	0
T1	642925	4	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	989015	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1058	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	989015	0	0
T1	642925	390	0	0
T2	232720	5364	0	0
T3	56736	495	0	0
T11	0	750	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	2078	0	0
T38	0	1985	0	0
T39	0	779	0	0
T43	0	313	0	0
T52	0	158	0	0
T55	0	710	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1058	0	0
T1	642925	3	0	0
T2	232720	3	0	0
T3	56736	1	0	0
T11	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	938109	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1017	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	938109	0	0
T1	642925	384	0	0
T2	232720	5333	0	0
T3	56736	493	0	0
T11	0	724	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	2030	0	0
T38	0	1976	0	0
T39	0	777	0	0
T43	0	296	0	0
T52	0	164	0	0
T55	0	701	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1017	0	0
T1	642925	3	0	0
T2	232720	3	0	0
T3	56736	1	0	0
T11	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	979468	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1046	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	979468	0	0
T1	642925	378	0	0
T2	232720	5312	0	0
T3	56736	491	0	0
T11	0	701	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	1978	0	0
T38	0	1973	0	0
T39	0	775	0	0
T43	0	290	0	0
T52	0	152	0	0
T55	0	693	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1046	0	0
T1	642925	3	0	0
T2	232720	3	0	0
T3	56736	1	0	0
T11	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T52	0	2	0	0
T55	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	2832060	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	3083	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2832060	0	0
T1	642925	8453	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T4	66936	9352	0	0
T5	54898	7816	0	0
T6	0	32161	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	0	16561	0	0
T33	0	8158	0	0
T36	0	8411	0	0
T45	0	65724	0	0
T56	0	5161	0	0
T57	0	9199	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	3083	0	0
T1	642925	60	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T4	66936	20	0	0
T5	54898	20	0	0
T6	0	20	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	0	20	0	0
T33	0	20	0	0
T36	0	20	0	0
T45	0	80	0	0
T56	0	20	0	0
T57	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	5624196	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	6504	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5624196	0	0
T1	642925	2995	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T4	66936	512	0	0
T5	54898	327	0	0
T6	0	34003	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	33196	0	0
T18	0	714	0	0
T46	0	35931	0	0
T58	0	20872	0	0
T59	0	28564	0	0
T60	0	2658	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6504	0	0
T1	642925	23	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T4	66936	1	0	0
T5	54898	1	0	0
T6	0	21	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	20	0	0
T18	0	1	0	0
T46	0	20	0	0
T58	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T5,T1
0	0	1	Covered	T4,T5,T1
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6723920	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7702	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6723920	0	0
T1	642925	3828	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T4	66936	520	0	0
T5	54898	329	0	0
T6	0	36002	0	0
T7	0	7827	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	33653	0	0
T18	0	716	0	0
T19	0	477	0	0
T46	0	36011	0	0
T47	0	237	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7702	0	0
T1	642925	28	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T4	66936	1	0	0
T5	54898	1	0	0
T6	0	22	0	0
T7	0	12	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	20	0	0
T18	0	1	0	0
T19	0	1	0	0
T46	0	20	0	0
T47	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T17,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T17,T6
1	1	Covered	T1,T17,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T17,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T17,T6
1	1	Covered	T1,T17,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T17,T6
0	0	1	Covered	T1,T17,T6
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T17,T6
0	0	1	Covered	T1,T17,T6
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	5570669	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	6383	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	5570669	0	0
T1	642925	2605	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	32125	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	33444	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T38	0	104063	0	0
T46	0	35971	0	0
T58	0	20912	0	0
T59	0	28604	0	0
T60	0	2787	0	0
T61	0	28681	0	0
T62	0	9830	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6383	0	0
T1	642925	20	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	20	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	20	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T38	0	60	0	0
T46	0	20	0	0
T58	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T10,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T10,T23
1	1	Covered	T1,T10,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T10,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T10,T23
1	1	Covered	T1,T10,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T10,T23
0	0	1	Covered	T1,T10,T23
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T10,T23
0	0	1	Covered	T1,T10,T23
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	993019	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1090	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	993019	0	0
T1	642925	119	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T10	0	280	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T23	0	371	0	0
T33	0	1279	0	0
T36	0	472	0	0
T37	0	377	0	0
T38	0	1998	0	0
T39	0	779	0	0
T63	0	371	0	0
T64	0	1450	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1090	0	0
T1	642925	1	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T10	0	1	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T23	0	1	0	0
T33	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1774348	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	2066	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1774348	0	0
T1	642925	546	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1426	0	0
T7	0	6610	0	0
T8	0	6166	0	0
T9	0	1350	0	0
T10	0	271	0	0
T12	0	878	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	439	0	0
T23	0	369	0	0
T29	0	1514	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	2066	0	0
T1	642925	5	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T23	0	1	0	0
T29	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T16,T24,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T16,T24,T25
1	1	Covered	T16,T24,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T16,T24,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T24,T25
1	1	Covered	T16,T24,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T24,T25
0	0	1	Covered	T16,T24,T25
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T24,T25
0	0	1	Covered	T16,T24,T25
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1233798	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1388	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1233798	0	0
T6	110829	0	0	0
T16	47214	892	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	2491	0	0
T25	0	359	0	0
T36	0	1785	0	0
T39	0	779	0	0
T41	0	8120	0	0
T42	0	7783	0	0
T43	0	1728	0	0
T44	0	3168	0	0
T45	0	9727	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1388	0	0
T6	110829	0	0	0
T16	47214	4	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	6	0	0
T25	0	3	0	0
T36	0	4	0	0
T39	0	1	0	0
T41	0	5	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	4	0	0
T45	0	12	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T16,T24,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T16,T24,T25
1	1	Covered	T16,T24,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T16,T24,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T24,T25
1	1	Covered	T16,T24,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T24,T25
0	0	1	Covered	T16,T24,T25
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T24,T25
0	0	1	Covered	T16,T24,T25
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1066708	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1191	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1066708	0	0
T6	110829	0	0	0
T16	47214	657	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	1306	0	0
T25	0	353	0	0
T36	0	1293	0	0
T39	0	777	0	0
T41	0	4755	0	0
T42	0	4864	0	0
T43	0	1053	0	0
T44	0	2419	0	0
T45	0	7223	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1191	0	0
T6	110829	0	0	0
T16	47214	3	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T24	84327	3	0	0
T25	0	3	0	0
T36	0	3	0	0
T39	0	1	0	0
T41	0	3	0	0
T42	0	5	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	9	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6502658	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7390	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6502658	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	58821	0	0
T12	0	32347	0	0
T19	719940	31376	0	0
T24	84327	0	0	0
T29	0	28884	0	0
T30	0	145198	0	0
T31	0	7081	0	0
T40	0	484	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	29261	0	0
T66	0	31262	0	0
T67	0	92432	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7390	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	70	0	0
T12	0	76	0	0
T19	719940	76	0	0
T24	84327	0	0	0
T29	0	66	0	0
T30	0	86	0	0
T31	0	77	0	0
T40	0	1	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	71	0	0
T66	0	77	0	0
T67	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6510488	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7508	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6510488	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	66276	0	0
T12	0	37921	0	0
T19	719940	37657	0	0
T24	84327	0	0	0
T29	0	34260	0	0
T30	0	135481	0	0
T31	0	7367	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	36336	0	0
T66	0	36599	0	0
T67	0	92222	0	0
T68	0	20675	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7508	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	81	0	0
T12	0	89	0	0
T19	719940	92	0	0
T24	84327	0	0	0
T29	0	79	0	0
T30	0	81	0	0
T31	0	81	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	91	0	0
T66	0	93	0	0
T67	0	51	0	0
T68	0	62	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6345577	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7359	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6345577	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	51033	0	0
T12	0	26853	0	0
T19	719940	24103	0	0
T24	84327	0	0	0
T29	0	28982	0	0
T30	0	94142	0	0
T31	0	7423	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	32796	0	0
T66	0	26838	0	0
T67	0	92012	0	0
T68	0	22373	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7359	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	64	0	0
T12	0	64	0	0
T19	719940	59	0	0
T24	84327	0	0	0
T29	0	67	0	0
T30	0	57	0	0
T31	0	80	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	86	0	0
T66	0	70	0	0
T67	0	51	0	0
T68	0	70	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6325259	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7353	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6325259	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	63905	0	0
T12	0	29804	0	0
T19	719940	26743	0	0
T24	84327	0	0	0
T29	0	28690	0	0
T30	0	130858	0	0
T31	0	5467	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	28915	0	0
T66	0	31847	0	0
T67	0	91802	0	0
T68	0	18054	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7353	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	81	0	0
T12	0	72	0	0
T19	719940	66	0	0
T24	84327	0	0	0
T29	0	67	0	0
T30	0	80	0	0
T31	0	59	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	75	0	0
T66	0	84	0	0
T67	0	51	0	0
T68	0	59	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1206954	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1323	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1206954	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	7390	0	0
T12	0	958	0	0
T19	719940	479	0	0
T24	84327	0	0	0
T29	0	1674	0	0
T30	0	12374	0	0
T31	0	374	0	0
T40	0	473	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	4106	0	0
T66	0	2210	0	0
T67	0	1498	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1323	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	9	0	0
T12	0	2	0	0
T19	719940	1	0	0
T24	84327	0	0	0
T29	0	4	0	0
T30	0	7	0	0
T31	0	4	0	0
T40	0	1	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	10	0	0
T66	0	5	0	0
T67	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1244677	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1337	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1244677	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	7088	0	0
T12	0	938	0	0
T19	719940	469	0	0
T24	84327	0	0	0
T29	0	1634	0	0
T30	0	12042	0	0
T31	0	378	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	3665	0	0
T66	0	2063	0	0
T67	0	1488	0	0
T68	0	1238	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1337	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	9	0	0
T12	0	2	0	0
T19	719940	1	0	0
T24	84327	0	0	0
T29	0	4	0	0
T30	0	7	0	0
T31	0	4	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	10	0	0
T66	0	5	0	0
T67	0	1	0	0
T68	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1164962	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1294	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1164962	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	6808	0	0
T12	0	918	0	0
T19	719940	459	0	0
T24	84327	0	0	0
T29	0	1594	0	0
T30	0	11734	0	0
T31	0	369	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	3320	0	0
T66	0	1880	0	0
T67	0	1478	0	0
T68	0	1172	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1294	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	9	0	0
T12	0	2	0	0
T19	719940	1	0	0
T24	84327	0	0	0
T29	0	4	0	0
T30	0	7	0	0
T31	0	4	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	10	0	0
T66	0	5	0	0
T67	0	1	0	0
T68	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T8,T12
1	1	Covered	T19,T8,T12

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T19,T8,T12
0	0	1	Covered	T19,T8,T12
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1148074	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1289	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1148074	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	6478	0	0
T12	0	898	0	0
T19	719940	449	0	0
T24	84327	0	0	0
T29	0	1554	0	0
T30	0	11461	0	0
T31	0	356	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	3956	0	0
T66	0	1841	0	0
T67	0	1468	0	0
T68	0	1302	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1289	0	0
T6	110829	0	0	0
T7	540858	0	0	0
T8	637114	9	0	0
T12	0	2	0	0
T19	719940	1	0	0
T24	84327	0	0	0
T29	0	4	0	0
T30	0	7	0	0
T31	0	4	0	0
T46	251004	0	0	0
T47	54590	0	0	0
T48	211227	0	0	0
T49	52903	0	0	0
T50	193004	0	0	0
T65	0	10	0	0
T66	0	5	0	0
T67	0	1	0	0
T68	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	7042477	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7997	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7042477	0	0
T1	642925	515	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1434	0	0
T7	0	7952	0	0
T8	0	59157	0	0
T9	0	1460	0	0
T12	0	32487	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	31522	0	0
T29	0	28992	0	0
T32	0	5444	0	0
T40	0	455	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7997	0	0
T1	642925	4	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1	0	0
T7	0	12	0	0
T8	0	70	0	0
T9	0	1	0	0
T12	0	76	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	76	0	0
T29	0	66	0	0
T32	0	13	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6998005	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	8038	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6998005	0	0
T1	642925	395	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	7844	0	0
T8	0	66714	0	0
T9	0	1453	0	0
T12	0	38087	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	37835	0	0
T29	0	34394	0	0
T30	0	135988	0	0
T32	0	5339	0	0
T69	0	1265	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	8038	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	81	0	0
T9	0	1	0	0
T12	0	89	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	92	0	0
T29	0	79	0	0
T30	0	81	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6879146	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7925	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6879146	0	0
T1	642925	389	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	7733	0	0
T8	0	51321	0	0
T9	0	1448	0	0
T12	0	26969	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	24215	0	0
T29	0	29092	0	0
T30	0	94508	0	0
T32	0	5246	0	0
T69	0	1242	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7925	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	64	0	0
T9	0	1	0	0
T12	0	64	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	59	0	0
T29	0	67	0	0
T30	0	57	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	6777588	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	7882	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	6777588	0	0
T1	642925	383	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	7619	0	0
T8	0	64231	0	0
T9	0	1439	0	0
T12	0	29936	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	26869	0	0
T29	0	28800	0	0
T30	0	131423	0	0
T32	0	5159	0	0
T69	0	1222	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	7882	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	81	0	0
T9	0	1	0	0
T12	0	72	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	66	0	0
T29	0	67	0	0
T30	0	80	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1731100	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1970	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1731100	0	0
T1	642925	489	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1432	0	0
T7	0	7528	0	0
T8	0	7258	0	0
T9	0	1418	0	0
T12	0	950	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	475	0	0
T29	0	1658	0	0
T32	0	5080	0	0
T40	0	444	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1970	0	0
T1	642925	4	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T32	0	13	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1618442	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1871	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1618442	0	0
T1	642925	371	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	7425	0	0
T8	0	6978	0	0
T9	0	1410	0	0
T12	0	930	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	465	0	0
T29	0	1618	0	0
T30	0	11901	0	0
T32	0	4970	0	0
T69	0	1165	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1871	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T30	0	7	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1660502	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1880	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1660502	0	0
T1	642925	365	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	7304	0	0
T8	0	6682	0	0
T9	0	1403	0	0
T12	0	910	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	455	0	0
T29	0	1578	0	0
T30	0	11637	0	0
T32	0	4872	0	0
T69	0	1146	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1880	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T30	0	7	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1679459	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1925	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1679459	0	0
T1	642925	359	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	7219	0	0
T8	0	6356	0	0
T9	0	1399	0	0
T12	0	890	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	445	0	0
T29	0	1538	0	0
T30	0	11375	0	0
T32	0	4784	0	0
T69	0	1118	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1925	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T30	0	7	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T6
1	1	Covered	T1,T19,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T6
0	0	1	Covered	T1,T19,T6
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1663234	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1920	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1663234	0	0
T1	642925	463	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1430	0	0
T7	0	7093	0	0
T8	0	7222	0	0
T9	0	1390	0	0
T12	0	946	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	473	0	0
T29	0	1650	0	0
T32	0	4692	0	0
T40	0	437	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1920	0	0
T1	642925	4	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T6	0	1	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T32	0	13	0	0
T40	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1665513	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1908	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1665513	0	0
T1	642925	347	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	7013	0	0
T8	0	6916	0	0
T9	0	1381	0	0
T12	0	926	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	463	0	0
T29	0	1610	0	0
T30	0	11852	0	0
T32	0	4598	0	0
T69	0	1077	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1908	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T30	0	7	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1643792	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1884	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1643792	0	0
T1	642925	341	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	6916	0	0
T8	0	6620	0	0
T9	0	1374	0	0
T12	0	906	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	453	0	0
T29	0	1570	0	0
T30	0	11582	0	0
T32	0	4512	0	0
T69	0	1043	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1884	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T30	0	7	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T19,T7
1	1	Covered	T1,T19,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T19,T7
0	0	1	Covered	T1,T19,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	1632349	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1882	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1632349	0	0
T1	642925	335	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	6824	0	0
T8	0	6297	0	0
T9	0	1363	0	0
T12	0	886	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	443	0	0
T29	0	1530	0	0
T30	0	11309	0	0
T32	0	4417	0	0
T69	0	1005	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1882	0	0
T1	642925	3	0	0
T2	232720	0	0	0
T3	56736	0	0	0
T7	0	12	0	0
T8	0	9	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	1	0	0
T29	0	4	0	0
T30	0	7	0	0
T32	0	13	0	0
T69	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1389473439	999957	0	0
DstReqKnown_A	7906944	7052097	0	0
SrcAckBusyChk_A	1389473439	1044	0	0
SrcBusyKnown_A	1389473439	1389037377	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	999957	0	0
T1	642925	233	0	0
T2	232720	3388	0	0
T3	56736	866	0	0
T11	0	735	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	2390	0	0
T43	0	606	0	0
T45	0	1425	0	0
T52	0	166	0	0
T70	0	226	0	0
T71	0	618	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906944	7052097	0	0
T1	17251	11189	0	0
T2	1263	863	0	0
T3	681	281	0	0
T4	495	95	0	0
T5	498	98	0	0
T13	8419	19	0	0
T14	439	39	0	0
T15	422	22	0	0
T16	674	274	0	0
T17	502	102	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1044	0	0
T1	642925	2	0	0
T2	232720	2	0	0
T3	56736	2	0	0
T11	0	2	0	0
T13	113661	0	0	0
T14	54900	0	0	0
T15	208992	0	0	0
T16	47214	0	0	0
T17	238501	0	0	0
T18	118206	0	0	0
T19	719940	0	0	0
T33	0	6	0	0
T43	0	2	0	0
T45	0	2	0	0
T52	0	2	0	0
T70	0	2	0	0
T71	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1389473439	1389037377	0	0
T1	642925	641472	0	0
T2	232720	232667	0	0
T3	56736	56660	0	0
T4	66936	66882	0	0
T5	54898	54833	0	0
T13	113661	113503	0	0
T14	54900	54842	0	0
T15	208992	208913	0	0
T16	47214	47121	0	0
T17	238501	238438	0	0