Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T18 |
10 |
|
T19 |
8 |
|
T20 |
10 |
| auto[1] |
828 |
1 |
|
|
T18 |
10 |
|
T19 |
12 |
|
T20 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T18 |
9 |
|
T19 |
10 |
|
T20 |
13 |
| auto[1] |
817 |
1 |
|
|
T18 |
11 |
|
T19 |
10 |
|
T20 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T18 |
8 |
|
T19 |
12 |
|
T20 |
12 |
| auto[1] |
828 |
1 |
|
|
T18 |
12 |
|
T19 |
8 |
|
T20 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T18 |
10 |
|
T19 |
12 |
|
T20 |
10 |
| auto[1] |
807 |
1 |
|
|
T18 |
10 |
|
T19 |
8 |
|
T20 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T18 |
11 |
|
T19 |
12 |
|
T20 |
10 |
| auto[1] |
847 |
1 |
|
|
T18 |
9 |
|
T19 |
8 |
|
T20 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
835 |
1 |
|
|
T18 |
11 |
|
T19 |
8 |
|
T20 |
10 |
| auto[1] |
825 |
1 |
|
|
T18 |
9 |
|
T19 |
12 |
|
T20 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
837 |
1 |
|
|
T18 |
7 |
|
T19 |
13 |
|
T20 |
13 |
| auto[1] |
823 |
1 |
|
|
T18 |
13 |
|
T19 |
7 |
|
T20 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
817 |
1 |
|
|
T18 |
7 |
|
T19 |
11 |
|
T20 |
13 |
| auto[1] |
843 |
1 |
|
|
T18 |
13 |
|
T19 |
9 |
|
T20 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T18 |
10 |
|
T19 |
14 |
|
T20 |
12 |
| auto[1] |
820 |
1 |
|
|
T18 |
10 |
|
T19 |
6 |
|
T20 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T18 |
14 |
|
T19 |
9 |
|
T20 |
10 |
| auto[1] |
829 |
1 |
|
|
T18 |
6 |
|
T19 |
11 |
|
T20 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T18 |
8 |
|
T19 |
11 |
|
T20 |
8 |
| auto[1] |
847 |
1 |
|
|
T18 |
12 |
|
T19 |
9 |
|
T20 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T18 |
10 |
|
T19 |
11 |
|
T20 |
6 |
| auto[1] |
848 |
1 |
|
|
T18 |
10 |
|
T19 |
9 |
|
T20 |
14 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T18 |
8 |
|
T19 |
9 |
|
T20 |
5 |
| auto[1] |
837 |
1 |
|
|
T18 |
12 |
|
T19 |
11 |
|
T20 |
15 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T18 |
9 |
|
T19 |
10 |
|
T20 |
13 |
| auto[1] |
817 |
1 |
|
|
T18 |
11 |
|
T19 |
10 |
|
T20 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T18 |
10 |
|
T19 |
10 |
|
T20 |
7 |
| auto[1] |
808 |
1 |
|
|
T18 |
10 |
|
T19 |
10 |
|
T20 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T18 |
12 |
|
T19 |
8 |
|
T20 |
7 |
| auto[1] |
831 |
1 |
|
|
T18 |
8 |
|
T19 |
12 |
|
T20 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T18 |
12 |
|
T19 |
9 |
|
T20 |
17 |
| auto[1] |
826 |
1 |
|
|
T18 |
8 |
|
T19 |
11 |
|
T20 |
3 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
786 |
1 |
|
|
T18 |
4 |
|
T19 |
13 |
|
T20 |
11 |
| auto[1] |
874 |
1 |
|
|
T18 |
16 |
|
T19 |
7 |
|
T20 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
843 |
1 |
|
|
T18 |
7 |
|
T19 |
10 |
|
T20 |
11 |
| auto[1] |
817 |
1 |
|
|
T18 |
13 |
|
T19 |
10 |
|
T20 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
837 |
1 |
|
|
T18 |
7 |
|
T19 |
8 |
|
T20 |
7 |
| auto[1] |
823 |
1 |
|
|
T18 |
13 |
|
T19 |
12 |
|
T20 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T18 |
14 |
|
T19 |
12 |
|
T20 |
11 |
| auto[1] |
792 |
1 |
|
|
T18 |
6 |
|
T19 |
8 |
|
T20 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
842 |
1 |
|
|
T18 |
8 |
|
T19 |
7 |
|
T20 |
6 |
| auto[1] |
818 |
1 |
|
|
T18 |
12 |
|
T19 |
13 |
|
T20 |
14 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T18 |
10 |
|
T19 |
13 |
|
T20 |
12 |
| auto[1] |
788 |
1 |
|
|
T18 |
10 |
|
T19 |
7 |
|
T20 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T18 |
10 |
|
T19 |
11 |
|
T20 |
6 |
| auto[1] |
848 |
1 |
|
|
T18 |
10 |
|
T19 |
9 |
|
T20 |
14 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T18 |
4 |
|
T19 |
4 |
|
T20 |
4 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T18 |
6 |
|
T19 |
6 |
|
T20 |
3 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T18 |
4 |
|
T19 |
8 |
|
T20 |
8 |
| auto[1] |
auto[1] |
403 |
1 |
|
|
T18 |
6 |
|
T19 |
2 |
|
T20 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T18 |
6 |
|
T19 |
3 |
|
T20 |
3 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T18 |
6 |
|
T19 |
5 |
|
T20 |
4 |
| auto[1] |
auto[0] |
427 |
1 |
|
|
T18 |
4 |
|
T19 |
9 |
|
T20 |
7 |
| auto[1] |
auto[1] |
404 |
1 |
|
|
T18 |
4 |
|
T19 |
3 |
|
T20 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T18 |
7 |
|
T19 |
6 |
|
T20 |
9 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T18 |
5 |
|
T19 |
3 |
|
T20 |
8 |
| auto[1] |
auto[0] |
397 |
1 |
|
|
T18 |
4 |
|
T19 |
6 |
|
T20 |
1 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T18 |
4 |
|
T19 |
5 |
|
T20 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
403 |
1 |
|
|
T18 |
3 |
|
T19 |
6 |
|
T20 |
6 |
| auto[0] |
auto[1] |
383 |
1 |
|
|
T18 |
1 |
|
T19 |
7 |
|
T20 |
5 |
| auto[1] |
auto[0] |
432 |
1 |
|
|
T18 |
8 |
|
T19 |
2 |
|
T20 |
4 |
| auto[1] |
auto[1] |
442 |
1 |
|
|
T18 |
8 |
|
T19 |
5 |
|
T20 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
428 |
1 |
|
|
T18 |
1 |
|
T19 |
6 |
|
T20 |
6 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T18 |
6 |
|
T19 |
4 |
|
T20 |
5 |
| auto[1] |
auto[0] |
409 |
1 |
|
|
T18 |
6 |
|
T19 |
7 |
|
T20 |
7 |
| auto[1] |
auto[1] |
408 |
1 |
|
|
T18 |
7 |
|
T19 |
3 |
|
T20 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
415 |
1 |
|
|
T18 |
1 |
|
T19 |
4 |
|
T20 |
4 |
| auto[0] |
auto[1] |
422 |
1 |
|
|
T18 |
6 |
|
T19 |
4 |
|
T20 |
3 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T18 |
6 |
|
T19 |
7 |
|
T20 |
9 |
| auto[1] |
auto[1] |
421 |
1 |
|
|
T18 |
7 |
|
T19 |
5 |
|
T20 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
423 |
1 |
|
|
T18 |
5 |
|
T19 |
5 |
|
T20 |
4 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T18 |
3 |
|
T19 |
2 |
|
T20 |
2 |
| auto[1] |
auto[0] |
408 |
1 |
|
|
T18 |
9 |
|
T19 |
4 |
|
T20 |
6 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T18 |
3 |
|
T19 |
9 |
|
T20 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
429 |
1 |
|
|
T18 |
3 |
|
T19 |
9 |
|
T20 |
6 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T18 |
7 |
|
T19 |
4 |
|
T20 |
6 |
| auto[1] |
auto[0] |
384 |
1 |
|
|
T18 |
5 |
|
T19 |
2 |
|
T20 |
2 |
| auto[1] |
auto[1] |
404 |
1 |
|
|
T18 |
5 |
|
T19 |
5 |
|
T20 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
386 |
1 |
|
|
T18 |
5 |
|
T19 |
1 |
|
T20 |
1 |
| auto[0] |
auto[1] |
437 |
1 |
|
|
T18 |
3 |
|
T19 |
8 |
|
T20 |
4 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T18 |
5 |
|
T19 |
7 |
|
T20 |
9 |
| auto[1] |
auto[1] |
391 |
1 |
|
|
T18 |
7 |
|
T19 |
4 |
|
T20 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
843 |
1 |
|
|
T18 |
9 |
|
T19 |
10 |
|
T20 |
13 |
| auto[1] |
auto[1] |
817 |
1 |
|
|
T18 |
11 |
|
T19 |
10 |
|
T20 |
7 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
473 |
1 |
|
|
T18 |
8 |
|
T19 |
9 |
|
T20 |
6 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T18 |
6 |
|
T19 |
3 |
|
T20 |
5 |
| auto[1] |
auto[0] |
367 |
1 |
|
|
T18 |
2 |
|
T19 |
5 |
|
T20 |
6 |
| auto[1] |
auto[1] |
425 |
1 |
|
|
T18 |
4 |
|
T19 |
3 |
|
T20 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
812 |
1 |
|
|
T18 |
10 |
|
T19 |
11 |
|
T20 |
6 |
| auto[1] |
auto[1] |
848 |
1 |
|
|
T18 |
10 |
|
T19 |
9 |
|
T20 |
14 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
86 |
1 |
|
|
T233 |
9 |
|
T181 |
11 |
|
T184 |
10 |
| auto[1] |
74 |
1 |
|
|
T233 |
11 |
|
T181 |
9 |
|
T184 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T233 |
8 |
|
T181 |
9 |
|
T184 |
14 |
| auto[1] |
83 |
1 |
|
|
T233 |
12 |
|
T181 |
11 |
|
T184 |
6 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T233 |
10 |
|
T181 |
11 |
|
T184 |
14 |
| auto[1] |
75 |
1 |
|
|
T233 |
10 |
|
T181 |
9 |
|
T184 |
6 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T233 |
8 |
|
T181 |
10 |
|
T184 |
8 |
| auto[1] |
85 |
1 |
|
|
T233 |
12 |
|
T181 |
10 |
|
T184 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T233 |
8 |
|
T181 |
9 |
|
T184 |
9 |
| auto[1] |
83 |
1 |
|
|
T233 |
12 |
|
T181 |
11 |
|
T184 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T233 |
12 |
|
T181 |
11 |
|
T184 |
10 |
| auto[1] |
79 |
1 |
|
|
T233 |
8 |
|
T181 |
9 |
|
T184 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T233 |
12 |
|
T181 |
8 |
|
T184 |
10 |
| auto[1] |
76 |
1 |
|
|
T233 |
8 |
|
T181 |
12 |
|
T184 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T233 |
8 |
|
T181 |
13 |
|
T184 |
12 |
| auto[1] |
71 |
1 |
|
|
T233 |
12 |
|
T181 |
7 |
|
T184 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T233 |
13 |
|
T181 |
12 |
|
T184 |
10 |
| auto[1] |
81 |
1 |
|
|
T233 |
7 |
|
T181 |
8 |
|
T184 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T233 |
9 |
|
T181 |
14 |
|
T184 |
10 |
| auto[1] |
68 |
1 |
|
|
T233 |
11 |
|
T181 |
6 |
|
T184 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T233 |
12 |
|
T181 |
11 |
|
T184 |
11 |
| auto[1] |
76 |
1 |
|
|
T233 |
8 |
|
T181 |
9 |
|
T184 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69 |
1 |
|
|
T233 |
10 |
|
T181 |
8 |
|
T184 |
7 |
| auto[1] |
91 |
1 |
|
|
T233 |
10 |
|
T181 |
12 |
|
T184 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T233 |
12 |
|
T181 |
10 |
|
T184 |
14 |
| auto[1] |
80 |
1 |
|
|
T233 |
8 |
|
T181 |
10 |
|
T184 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T233 |
8 |
|
T181 |
9 |
|
T184 |
14 |
| auto[1] |
83 |
1 |
|
|
T233 |
12 |
|
T181 |
11 |
|
T184 |
6 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T233 |
9 |
|
T181 |
8 |
|
T184 |
8 |
| auto[1] |
78 |
1 |
|
|
T233 |
11 |
|
T181 |
12 |
|
T184 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T233 |
9 |
|
T181 |
11 |
|
T184 |
10 |
| auto[1] |
86 |
1 |
|
|
T233 |
11 |
|
T181 |
9 |
|
T184 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T233 |
9 |
|
T181 |
13 |
|
T184 |
11 |
| auto[1] |
82 |
1 |
|
|
T233 |
11 |
|
T181 |
7 |
|
T184 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T233 |
9 |
|
T181 |
11 |
|
T184 |
10 |
| auto[1] |
78 |
1 |
|
|
T233 |
11 |
|
T181 |
9 |
|
T184 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T233 |
9 |
|
T181 |
7 |
|
T184 |
9 |
| auto[1] |
85 |
1 |
|
|
T233 |
11 |
|
T181 |
13 |
|
T184 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T233 |
5 |
|
T181 |
10 |
|
T184 |
9 |
| auto[1] |
94 |
1 |
|
|
T233 |
15 |
|
T181 |
10 |
|
T184 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T233 |
13 |
|
T181 |
10 |
|
T184 |
11 |
| auto[1] |
79 |
1 |
|
|
T233 |
7 |
|
T181 |
10 |
|
T184 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T233 |
9 |
|
T181 |
11 |
|
T184 |
12 |
| auto[1] |
80 |
1 |
|
|
T233 |
11 |
|
T181 |
9 |
|
T184 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T233 |
14 |
|
T181 |
8 |
|
T184 |
9 |
| auto[1] |
82 |
1 |
|
|
T233 |
6 |
|
T181 |
12 |
|
T184 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
69 |
1 |
|
|
T233 |
10 |
|
T181 |
8 |
|
T184 |
7 |
| auto[1] |
91 |
1 |
|
|
T233 |
10 |
|
T181 |
12 |
|
T184 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
44 |
1 |
|
|
T233 |
4 |
|
T181 |
4 |
|
T184 |
5 |
| auto[0] |
auto[1] |
38 |
1 |
|
|
T233 |
5 |
|
T181 |
4 |
|
T184 |
3 |
| auto[1] |
auto[0] |
41 |
1 |
|
|
T233 |
6 |
|
T181 |
7 |
|
T184 |
9 |
| auto[1] |
auto[1] |
37 |
1 |
|
|
T233 |
5 |
|
T181 |
5 |
|
T184 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
35 |
1 |
|
|
T233 |
3 |
|
T181 |
5 |
|
T184 |
3 |
| auto[0] |
auto[1] |
39 |
1 |
|
|
T233 |
6 |
|
T181 |
6 |
|
T184 |
7 |
| auto[1] |
auto[0] |
40 |
1 |
|
|
T233 |
5 |
|
T181 |
5 |
|
T184 |
5 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T233 |
6 |
|
T181 |
4 |
|
T184 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T233 |
5 |
|
T181 |
6 |
|
T184 |
5 |
| auto[0] |
auto[1] |
39 |
1 |
|
|
T233 |
4 |
|
T181 |
7 |
|
T184 |
6 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T233 |
3 |
|
T181 |
3 |
|
T184 |
4 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T233 |
8 |
|
T181 |
4 |
|
T184 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
43 |
1 |
|
|
T233 |
7 |
|
T181 |
6 |
|
T184 |
5 |
| auto[0] |
auto[1] |
39 |
1 |
|
|
T233 |
2 |
|
T181 |
5 |
|
T184 |
5 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T233 |
5 |
|
T181 |
5 |
|
T184 |
5 |
| auto[1] |
auto[1] |
40 |
1 |
|
|
T233 |
6 |
|
T181 |
4 |
|
T184 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
40 |
1 |
|
|
T233 |
6 |
|
T181 |
1 |
|
T184 |
6 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T233 |
3 |
|
T181 |
6 |
|
T184 |
3 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T233 |
6 |
|
T181 |
7 |
|
T184 |
4 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T233 |
5 |
|
T181 |
6 |
|
T184 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
38 |
1 |
|
|
T233 |
2 |
|
T181 |
5 |
|
T184 |
7 |
| auto[0] |
auto[1] |
28 |
1 |
|
|
T233 |
3 |
|
T181 |
5 |
|
T184 |
2 |
| auto[1] |
auto[0] |
51 |
1 |
|
|
T233 |
6 |
|
T181 |
8 |
|
T184 |
5 |
| auto[1] |
auto[1] |
43 |
1 |
|
|
T233 |
9 |
|
T181 |
2 |
|
T184 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
48 |
1 |
|
|
T233 |
4 |
|
T181 |
7 |
|
T184 |
4 |
| auto[0] |
auto[1] |
32 |
1 |
|
|
T233 |
5 |
|
T181 |
4 |
|
T184 |
8 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T233 |
5 |
|
T181 |
7 |
|
T184 |
6 |
| auto[1] |
auto[1] |
36 |
1 |
|
|
T233 |
6 |
|
T181 |
2 |
|
T184 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
43 |
1 |
|
|
T233 |
8 |
|
T181 |
4 |
|
T184 |
3 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T233 |
6 |
|
T181 |
4 |
|
T184 |
6 |
| auto[1] |
auto[0] |
41 |
1 |
|
|
T233 |
4 |
|
T181 |
7 |
|
T184 |
8 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T233 |
2 |
|
T181 |
5 |
|
T184 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T233 |
5 |
|
T181 |
4 |
|
T184 |
7 |
| auto[0] |
auto[1] |
35 |
1 |
|
|
T233 |
7 |
|
T181 |
6 |
|
T184 |
7 |
| auto[1] |
auto[0] |
41 |
1 |
|
|
T233 |
4 |
|
T181 |
7 |
|
T184 |
3 |
| auto[1] |
auto[1] |
39 |
1 |
|
|
T233 |
4 |
|
T181 |
3 |
|
T184 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T233 |
8 |
|
T181 |
9 |
|
T184 |
14 |
| auto[1] |
auto[1] |
83 |
1 |
|
|
T233 |
12 |
|
T181 |
11 |
|
T184 |
6 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T233 |
10 |
|
T181 |
7 |
|
T184 |
7 |
| auto[0] |
auto[1] |
39 |
1 |
|
|
T233 |
3 |
|
T181 |
3 |
|
T184 |
4 |
| auto[1] |
auto[0] |
37 |
1 |
|
|
T233 |
3 |
|
T181 |
5 |
|
T184 |
3 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T233 |
4 |
|
T181 |
5 |
|
T184 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T233 |
10 |
|
T181 |
8 |
|
T184 |
7 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T233 |
10 |
|
T181 |
12 |
|
T184 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T18 |
14 |
|
T185 |
8 |
|
T317 |
9 |
| auto[1] |
29 |
1 |
|
|
T18 |
6 |
|
T185 |
12 |
|
T317 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T18 |
14 |
|
T185 |
7 |
|
T317 |
13 |
| auto[1] |
26 |
1 |
|
|
T18 |
6 |
|
T185 |
13 |
|
T317 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T18 |
8 |
|
T185 |
7 |
|
T317 |
12 |
| auto[1] |
33 |
1 |
|
|
T18 |
12 |
|
T185 |
13 |
|
T317 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
35 |
1 |
|
|
T18 |
8 |
|
T185 |
14 |
|
T317 |
13 |
| auto[1] |
25 |
1 |
|
|
T18 |
12 |
|
T185 |
6 |
|
T317 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
35 |
1 |
|
|
T18 |
12 |
|
T185 |
12 |
|
T317 |
11 |
| auto[1] |
25 |
1 |
|
|
T18 |
8 |
|
T185 |
8 |
|
T317 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
25 |
1 |
|
|
T18 |
9 |
|
T185 |
7 |
|
T317 |
9 |
| auto[1] |
35 |
1 |
|
|
T18 |
11 |
|
T185 |
13 |
|
T317 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T18 |
15 |
|
T185 |
8 |
|
T317 |
9 |
| auto[1] |
28 |
1 |
|
|
T18 |
5 |
|
T185 |
12 |
|
T317 |
11 |