Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
796 |
1 |
|
|
T25 |
7 |
|
T20 |
10 |
|
T3 |
13 |
| auto[1] |
744 |
1 |
|
|
T25 |
13 |
|
T20 |
10 |
|
T3 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T25 |
9 |
|
T20 |
9 |
|
T3 |
11 |
| auto[1] |
785 |
1 |
|
|
T25 |
11 |
|
T20 |
11 |
|
T3 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
762 |
1 |
|
|
T25 |
7 |
|
T20 |
9 |
|
T3 |
10 |
| auto[1] |
778 |
1 |
|
|
T25 |
13 |
|
T20 |
11 |
|
T3 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
757 |
1 |
|
|
T25 |
8 |
|
T20 |
9 |
|
T3 |
8 |
| auto[1] |
783 |
1 |
|
|
T25 |
12 |
|
T20 |
11 |
|
T3 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
750 |
1 |
|
|
T25 |
7 |
|
T20 |
9 |
|
T3 |
14 |
| auto[1] |
790 |
1 |
|
|
T25 |
13 |
|
T20 |
11 |
|
T3 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
770 |
1 |
|
|
T25 |
13 |
|
T20 |
13 |
|
T3 |
11 |
| auto[1] |
770 |
1 |
|
|
T25 |
7 |
|
T20 |
7 |
|
T3 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
742 |
1 |
|
|
T25 |
12 |
|
T20 |
9 |
|
T3 |
8 |
| auto[1] |
798 |
1 |
|
|
T25 |
8 |
|
T20 |
11 |
|
T3 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
761 |
1 |
|
|
T25 |
11 |
|
T20 |
6 |
|
T3 |
9 |
| auto[1] |
779 |
1 |
|
|
T25 |
9 |
|
T20 |
14 |
|
T3 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
790 |
1 |
|
|
T25 |
9 |
|
T20 |
9 |
|
T3 |
10 |
| auto[1] |
750 |
1 |
|
|
T25 |
11 |
|
T20 |
11 |
|
T3 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
760 |
1 |
|
|
T25 |
9 |
|
T20 |
10 |
|
T3 |
9 |
| auto[1] |
780 |
1 |
|
|
T25 |
11 |
|
T20 |
10 |
|
T3 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
751 |
1 |
|
|
T25 |
14 |
|
T20 |
6 |
|
T3 |
11 |
| auto[1] |
789 |
1 |
|
|
T25 |
6 |
|
T20 |
14 |
|
T3 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
776 |
1 |
|
|
T25 |
8 |
|
T20 |
11 |
|
T3 |
8 |
| auto[1] |
764 |
1 |
|
|
T25 |
12 |
|
T20 |
9 |
|
T3 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
767 |
1 |
|
|
T25 |
12 |
|
T20 |
8 |
|
T3 |
11 |
| auto[1] |
773 |
1 |
|
|
T25 |
8 |
|
T20 |
12 |
|
T3 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T25 |
9 |
|
T20 |
9 |
|
T3 |
11 |
| auto[1] |
785 |
1 |
|
|
T25 |
11 |
|
T20 |
11 |
|
T3 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
781 |
1 |
|
|
T25 |
7 |
|
T20 |
7 |
|
T3 |
8 |
| auto[1] |
759 |
1 |
|
|
T25 |
13 |
|
T20 |
13 |
|
T3 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
788 |
1 |
|
|
T25 |
12 |
|
T20 |
9 |
|
T3 |
12 |
| auto[1] |
752 |
1 |
|
|
T25 |
8 |
|
T20 |
11 |
|
T3 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
764 |
1 |
|
|
T25 |
11 |
|
T20 |
11 |
|
T3 |
11 |
| auto[1] |
776 |
1 |
|
|
T25 |
9 |
|
T20 |
9 |
|
T3 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
764 |
1 |
|
|
T25 |
11 |
|
T20 |
11 |
|
T3 |
8 |
| auto[1] |
776 |
1 |
|
|
T25 |
9 |
|
T20 |
9 |
|
T3 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
783 |
1 |
|
|
T25 |
8 |
|
T20 |
13 |
|
T3 |
10 |
| auto[1] |
757 |
1 |
|
|
T25 |
12 |
|
T20 |
7 |
|
T3 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
780 |
1 |
|
|
T25 |
13 |
|
T20 |
12 |
|
T3 |
13 |
| auto[1] |
760 |
1 |
|
|
T25 |
7 |
|
T20 |
8 |
|
T3 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
774 |
1 |
|
|
T25 |
10 |
|
T20 |
9 |
|
T3 |
9 |
| auto[1] |
766 |
1 |
|
|
T25 |
10 |
|
T20 |
11 |
|
T3 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
753 |
1 |
|
|
T25 |
13 |
|
T20 |
7 |
|
T3 |
9 |
| auto[1] |
787 |
1 |
|
|
T25 |
7 |
|
T20 |
13 |
|
T3 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T25 |
10 |
|
T20 |
9 |
|
T3 |
9 |
| auto[1] |
762 |
1 |
|
|
T25 |
10 |
|
T20 |
11 |
|
T3 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
776 |
1 |
|
|
T25 |
8 |
|
T20 |
11 |
|
T3 |
8 |
| auto[1] |
764 |
1 |
|
|
T25 |
12 |
|
T20 |
9 |
|
T3 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
386 |
1 |
|
|
T25 |
2 |
|
T20 |
3 |
|
T3 |
4 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T25 |
5 |
|
T20 |
4 |
|
T3 |
4 |
| auto[1] |
auto[0] |
376 |
1 |
|
|
T25 |
5 |
|
T20 |
6 |
|
T3 |
6 |
| auto[1] |
auto[1] |
383 |
1 |
|
|
T25 |
8 |
|
T20 |
7 |
|
T3 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
387 |
1 |
|
|
T25 |
5 |
|
T20 |
4 |
|
T3 |
5 |
| auto[0] |
auto[1] |
401 |
1 |
|
|
T25 |
7 |
|
T20 |
5 |
|
T3 |
7 |
| auto[1] |
auto[0] |
370 |
1 |
|
|
T25 |
3 |
|
T20 |
5 |
|
T3 |
3 |
| auto[1] |
auto[1] |
382 |
1 |
|
|
T25 |
5 |
|
T20 |
6 |
|
T3 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
359 |
1 |
|
|
T25 |
4 |
|
T20 |
4 |
|
T3 |
9 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T25 |
7 |
|
T20 |
7 |
|
T3 |
2 |
| auto[1] |
auto[0] |
391 |
1 |
|
|
T25 |
3 |
|
T20 |
5 |
|
T3 |
5 |
| auto[1] |
auto[1] |
385 |
1 |
|
|
T25 |
6 |
|
T20 |
4 |
|
T3 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
369 |
1 |
|
|
T25 |
7 |
|
T20 |
6 |
|
T3 |
6 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T25 |
4 |
|
T20 |
5 |
|
T3 |
2 |
| auto[1] |
auto[0] |
401 |
1 |
|
|
T25 |
6 |
|
T20 |
7 |
|
T3 |
5 |
| auto[1] |
auto[1] |
375 |
1 |
|
|
T25 |
3 |
|
T20 |
2 |
|
T3 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
368 |
1 |
|
|
T25 |
6 |
|
T20 |
3 |
|
T3 |
5 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T25 |
2 |
|
T20 |
10 |
|
T3 |
5 |
| auto[1] |
auto[0] |
374 |
1 |
|
|
T25 |
6 |
|
T20 |
6 |
|
T3 |
3 |
| auto[1] |
auto[1] |
383 |
1 |
|
|
T25 |
6 |
|
T20 |
1 |
|
T3 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
376 |
1 |
|
|
T25 |
8 |
|
T20 |
1 |
|
T3 |
7 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T25 |
5 |
|
T20 |
11 |
|
T3 |
6 |
| auto[1] |
auto[0] |
385 |
1 |
|
|
T25 |
3 |
|
T20 |
5 |
|
T3 |
2 |
| auto[1] |
auto[1] |
375 |
1 |
|
|
T25 |
4 |
|
T20 |
3 |
|
T3 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
383 |
1 |
|
|
T25 |
5 |
|
T20 |
3 |
|
T3 |
4 |
| auto[0] |
auto[1] |
370 |
1 |
|
|
T25 |
8 |
|
T20 |
4 |
|
T3 |
5 |
| auto[1] |
auto[0] |
377 |
1 |
|
|
T25 |
4 |
|
T20 |
7 |
|
T3 |
5 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T25 |
3 |
|
T20 |
6 |
|
T3 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
391 |
1 |
|
|
T25 |
6 |
|
T20 |
2 |
|
T3 |
5 |
| auto[0] |
auto[1] |
387 |
1 |
|
|
T25 |
4 |
|
T20 |
7 |
|
T3 |
4 |
| auto[1] |
auto[0] |
360 |
1 |
|
|
T25 |
8 |
|
T20 |
4 |
|
T3 |
6 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T25 |
2 |
|
T20 |
7 |
|
T3 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
390 |
1 |
|
|
T25 |
3 |
|
T20 |
4 |
|
T3 |
9 |
| auto[0] |
auto[1] |
377 |
1 |
|
|
T25 |
9 |
|
T20 |
4 |
|
T3 |
2 |
| auto[1] |
auto[0] |
406 |
1 |
|
|
T25 |
4 |
|
T20 |
6 |
|
T3 |
4 |
| auto[1] |
auto[1] |
367 |
1 |
|
|
T25 |
4 |
|
T20 |
6 |
|
T3 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
755 |
1 |
|
|
T25 |
9 |
|
T20 |
9 |
|
T3 |
11 |
| auto[1] |
auto[1] |
785 |
1 |
|
|
T25 |
11 |
|
T20 |
11 |
|
T3 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
379 |
1 |
|
|
T25 |
4 |
|
T20 |
5 |
|
T3 |
4 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T25 |
6 |
|
T20 |
4 |
|
T3 |
5 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T25 |
5 |
|
T20 |
4 |
|
T3 |
6 |
| auto[1] |
auto[1] |
355 |
1 |
|
|
T25 |
5 |
|
T20 |
7 |
|
T3 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
776 |
1 |
|
|
T25 |
8 |
|
T20 |
11 |
|
T3 |
8 |
| auto[1] |
auto[1] |
764 |
1 |
|
|
T25 |
12 |
|
T20 |
9 |
|
T3 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T74 |
9 |
|
T78 |
11 |
|
T80 |
10 |
| auto[1] |
110 |
1 |
|
|
T74 |
11 |
|
T78 |
9 |
|
T80 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T74 |
11 |
|
T78 |
12 |
|
T80 |
6 |
| auto[1] |
112 |
1 |
|
|
T74 |
9 |
|
T78 |
8 |
|
T80 |
14 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T74 |
13 |
|
T78 |
11 |
|
T80 |
9 |
| auto[1] |
103 |
1 |
|
|
T74 |
7 |
|
T78 |
9 |
|
T80 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T74 |
8 |
|
T78 |
9 |
|
T80 |
10 |
| auto[1] |
108 |
1 |
|
|
T74 |
12 |
|
T78 |
11 |
|
T80 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T74 |
12 |
|
T78 |
8 |
|
T80 |
15 |
| auto[1] |
107 |
1 |
|
|
T74 |
8 |
|
T78 |
12 |
|
T80 |
5 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T74 |
9 |
|
T78 |
12 |
|
T80 |
8 |
| auto[1] |
105 |
1 |
|
|
T74 |
11 |
|
T78 |
8 |
|
T80 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T74 |
14 |
|
T78 |
10 |
|
T80 |
15 |
| auto[1] |
104 |
1 |
|
|
T74 |
6 |
|
T78 |
10 |
|
T80 |
5 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
102 |
1 |
|
|
T74 |
8 |
|
T78 |
10 |
|
T80 |
10 |
| auto[1] |
118 |
1 |
|
|
T74 |
12 |
|
T78 |
10 |
|
T80 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T74 |
6 |
|
T78 |
9 |
|
T80 |
7 |
| auto[1] |
119 |
1 |
|
|
T74 |
14 |
|
T78 |
11 |
|
T80 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T74 |
8 |
|
T78 |
13 |
|
T80 |
8 |
| auto[1] |
116 |
1 |
|
|
T74 |
12 |
|
T78 |
7 |
|
T80 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T74 |
8 |
|
T78 |
11 |
|
T80 |
8 |
| auto[1] |
126 |
1 |
|
|
T74 |
12 |
|
T78 |
9 |
|
T80 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T74 |
12 |
|
T78 |
6 |
|
T80 |
7 |
| auto[1] |
110 |
1 |
|
|
T74 |
8 |
|
T78 |
14 |
|
T80 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T74 |
10 |
|
T78 |
12 |
|
T80 |
16 |
| auto[1] |
103 |
1 |
|
|
T74 |
10 |
|
T78 |
8 |
|
T80 |
4 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T74 |
11 |
|
T78 |
12 |
|
T80 |
6 |
| auto[1] |
112 |
1 |
|
|
T74 |
9 |
|
T78 |
8 |
|
T80 |
14 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
106 |
1 |
|
|
T74 |
7 |
|
T78 |
15 |
|
T80 |
10 |
| auto[1] |
114 |
1 |
|
|
T74 |
13 |
|
T78 |
5 |
|
T80 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
107 |
1 |
|
|
T74 |
12 |
|
T78 |
7 |
|
T80 |
9 |
| auto[1] |
113 |
1 |
|
|
T74 |
8 |
|
T78 |
13 |
|
T80 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T74 |
6 |
|
T78 |
10 |
|
T80 |
14 |
| auto[1] |
106 |
1 |
|
|
T74 |
14 |
|
T78 |
10 |
|
T80 |
6 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T74 |
11 |
|
T78 |
10 |
|
T80 |
9 |
| auto[1] |
116 |
1 |
|
|
T74 |
9 |
|
T78 |
10 |
|
T80 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T74 |
12 |
|
T78 |
5 |
|
T80 |
6 |
| auto[1] |
103 |
1 |
|
|
T74 |
8 |
|
T78 |
15 |
|
T80 |
14 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T74 |
12 |
|
T78 |
11 |
|
T80 |
13 |
| auto[1] |
111 |
1 |
|
|
T74 |
8 |
|
T78 |
9 |
|
T80 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T74 |
11 |
|
T78 |
7 |
|
T80 |
11 |
| auto[1] |
112 |
1 |
|
|
T74 |
9 |
|
T78 |
13 |
|
T80 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T74 |
11 |
|
T78 |
10 |
|
T80 |
5 |
| auto[1] |
110 |
1 |
|
|
T74 |
9 |
|
T78 |
10 |
|
T80 |
15 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T74 |
11 |
|
T78 |
10 |
|
T80 |
13 |
| auto[1] |
92 |
1 |
|
|
T74 |
9 |
|
T78 |
10 |
|
T80 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T74 |
12 |
|
T78 |
6 |
|
T80 |
7 |
| auto[1] |
110 |
1 |
|
|
T74 |
8 |
|
T78 |
14 |
|
T80 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T74 |
6 |
|
T78 |
8 |
|
T80 |
3 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T74 |
1 |
|
T78 |
7 |
|
T80 |
7 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T74 |
7 |
|
T78 |
3 |
|
T80 |
6 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T74 |
6 |
|
T78 |
2 |
|
T80 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T74 |
6 |
|
T78 |
3 |
|
T80 |
3 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T74 |
6 |
|
T78 |
4 |
|
T80 |
6 |
| auto[1] |
auto[0] |
55 |
1 |
|
|
T74 |
2 |
|
T78 |
6 |
|
T80 |
7 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T74 |
6 |
|
T78 |
7 |
|
T80 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T74 |
4 |
|
T78 |
2 |
|
T80 |
11 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T74 |
2 |
|
T78 |
8 |
|
T80 |
3 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T74 |
8 |
|
T78 |
6 |
|
T80 |
4 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T74 |
6 |
|
T78 |
4 |
|
T80 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T74 |
5 |
|
T78 |
4 |
|
T80 |
5 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T74 |
6 |
|
T78 |
6 |
|
T80 |
4 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T74 |
4 |
|
T78 |
8 |
|
T80 |
3 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T74 |
5 |
|
T78 |
2 |
|
T80 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T74 |
9 |
|
T78 |
1 |
|
T80 |
5 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T74 |
3 |
|
T78 |
4 |
|
T80 |
1 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T74 |
5 |
|
T78 |
9 |
|
T80 |
10 |
| auto[1] |
auto[1] |
46 |
1 |
|
|
T74 |
3 |
|
T78 |
6 |
|
T80 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
48 |
1 |
|
|
T74 |
6 |
|
T78 |
4 |
|
T80 |
6 |
| auto[0] |
auto[1] |
61 |
1 |
|
|
T74 |
6 |
|
T78 |
7 |
|
T80 |
7 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T74 |
2 |
|
T78 |
6 |
|
T80 |
4 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T74 |
6 |
|
T78 |
3 |
|
T80 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
52 |
1 |
|
|
T74 |
4 |
|
T78 |
6 |
|
T80 |
3 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T74 |
7 |
|
T78 |
4 |
|
T80 |
2 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T74 |
4 |
|
T78 |
7 |
|
T80 |
5 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T74 |
5 |
|
T78 |
3 |
|
T80 |
10 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T74 |
4 |
|
T78 |
5 |
|
T80 |
7 |
| auto[0] |
auto[1] |
72 |
1 |
|
|
T74 |
7 |
|
T78 |
5 |
|
T80 |
6 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T74 |
4 |
|
T78 |
6 |
|
T80 |
1 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T74 |
5 |
|
T78 |
4 |
|
T80 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T74 |
5 |
|
T78 |
6 |
|
T80 |
8 |
| auto[0] |
auto[1] |
59 |
1 |
|
|
T74 |
5 |
|
T78 |
6 |
|
T80 |
8 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T74 |
4 |
|
T78 |
5 |
|
T80 |
2 |
| auto[1] |
auto[1] |
51 |
1 |
|
|
T74 |
6 |
|
T78 |
3 |
|
T80 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
108 |
1 |
|
|
T74 |
11 |
|
T78 |
12 |
|
T80 |
6 |
| auto[1] |
auto[1] |
112 |
1 |
|
|
T74 |
9 |
|
T78 |
8 |
|
T80 |
14 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T74 |
4 |
|
T78 |
5 |
|
T80 |
6 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T74 |
7 |
|
T78 |
2 |
|
T80 |
5 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T74 |
2 |
|
T78 |
4 |
|
T80 |
1 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T74 |
7 |
|
T78 |
9 |
|
T80 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
110 |
1 |
|
|
T74 |
12 |
|
T78 |
6 |
|
T80 |
7 |
| auto[1] |
auto[1] |
110 |
1 |
|
|
T74 |
8 |
|
T78 |
14 |
|
T80 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
36 |
1 |
|
|
T80 |
6 |
|
T113 |
12 |
|
T98 |
11 |
| auto[1] |
44 |
1 |
|
|
T80 |
14 |
|
T113 |
8 |
|
T98 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T80 |
10 |
|
T113 |
11 |
|
T98 |
9 |
| auto[1] |
38 |
1 |
|
|
T80 |
10 |
|
T113 |
9 |
|
T98 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T80 |
9 |
|
T113 |
11 |
|
T98 |
7 |
| auto[1] |
46 |
1 |
|
|
T80 |
11 |
|
T113 |
9 |
|
T98 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T80 |
7 |
|
T113 |
7 |
|
T98 |
8 |
| auto[1] |
50 |
1 |
|
|
T80 |
13 |
|
T113 |
13 |
|
T98 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T80 |
8 |
|
T113 |
10 |
|
T98 |
13 |
| auto[1] |
38 |
1 |
|
|
T80 |
12 |
|
T113 |
10 |
|
T98 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T80 |
10 |
|
T113 |
8 |
|
T98 |
5 |
| auto[1] |
46 |
1 |
|
|
T80 |
10 |
|
T113 |
12 |
|
T98 |
15 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T80 |
9 |
|
T113 |
14 |
|
T98 |
17 |
| auto[1] |
32 |
1 |
|
|
T80 |
11 |
|
T113 |
6 |
|
T98 |
3 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T80 |
12 |
|
T113 |
10 |
|
T98 |
11 |
| auto[1] |
37 |
1 |
|
|
T80 |
8 |
|
T113 |
10 |
|
T98 |
9 |