Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.68	98.90	96.76	100.00	97.44	98.37	99.71	92.55

Total tests in report: 908

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
51.17	51.17	72.53	72.53	56.70	56.70	63.93	63.93	12.18	12.18	74.34	74.34	62.52	62.52	16.00	16.00	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.1651731244
71.95	20.78	87.05	14.52	78.74	22.04	86.99	23.06	43.59	31.41	88.39	14.05	79.19	16.67	39.72	23.71	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2446966899
79.49	7.54	91.12	4.07	83.52	4.78	86.99	0.00	75.00	31.41	92.05	3.66	87.67	8.48	40.08	0.37	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1146747042
84.83	5.34	97.05	5.93	91.66	8.14	92.01	5.02	78.85	3.85	96.86	4.81	93.55	5.88	43.86	3.78	/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1467611189
88.11	3.28	97.24	0.19	92.04	0.38	92.47	0.46	81.41	2.56	97.12	0.26	94.22	0.67	62.28	18.42	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2166881190
89.33	1.22	97.46	0.22	92.34	0.30	92.47	0.00	83.33	1.92	97.26	0.15	95.09	0.87	67.37	5.09	/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2188405542
90.54	1.21	97.48	0.02	92.69	0.35	93.15	0.68	83.33	0.00	97.30	0.04	95.28	0.19	74.55	7.19	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.504916961
91.49	0.95	97.59	0.11	93.15	0.46	97.49	4.34	84.62	1.28	97.41	0.11	95.47	0.19	74.71	0.16	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2320903119
92.09	0.60	97.72	0.13	93.30	0.15	97.49	0.00	87.82	3.21	97.60	0.18	95.86	0.39	74.87	0.16	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2482678730
92.61	0.52	97.84	0.11	93.60	0.30	97.49	0.00	87.82	0.00	97.60	0.00	95.86	0.00	78.07	3.20	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.2545121534
93.05	0.44	97.91	0.07	93.68	0.08	97.49	0.00	87.82	0.00	97.60	0.00	95.86	0.00	81.01	2.94	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3560297006
93.47	0.42	97.97	0.06	93.86	0.18	97.49	0.00	87.82	0.00	97.60	0.00	97.69	1.83	81.90	0.89	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4135674518
93.83	0.36	98.06	0.09	93.96	0.10	97.49	0.00	89.74	1.92	97.71	0.11	97.98	0.29	81.90	0.00	/workspace/coverage/default/41.sysrst_ctrl_edge_detect.579444336
94.16	0.32	98.12	0.06	94.03	0.08	97.49	0.00	91.67	1.92	97.82	0.11	98.07	0.10	81.90	0.00	/workspace/coverage/default/0.sysrst_ctrl_stress_all.863915079
94.44	0.28	98.12	0.00	94.06	0.03	99.09	1.60	91.67	0.00	97.82	0.00	98.17	0.10	82.16	0.26	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.1755723832
94.69	0.25	98.36	0.24	94.21	0.15	99.77	0.68	91.67	0.00	97.89	0.07	98.36	0.19	82.58	0.42	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3971557127
94.94	0.25	98.36	0.00	94.21	0.00	99.77	0.00	91.67	0.00	97.89	0.00	98.36	0.00	84.31	1.73	/workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1083458660
95.18	0.24	98.41	0.06	95.15	0.94	99.77	0.00	91.67	0.00	97.97	0.07	98.94	0.58	84.37	0.05	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3422670032
95.42	0.24	98.49	0.07	95.20	0.05	99.77	0.00	92.95	1.28	98.04	0.07	99.13	0.19	84.37	0.00	/workspace/coverage/default/34.sysrst_ctrl_edge_detect.20484684
95.62	0.20	98.51	0.02	95.20	0.00	99.77	0.00	92.95	0.00	98.04	0.00	99.13	0.00	85.73	1.36	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.1925419059
95.79	0.17	98.51	0.00	96.06	0.86	99.77	0.00	92.95	0.00	98.04	0.00	99.13	0.00	86.04	0.31	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1040884433
95.94	0.15	98.54	0.04	96.11	0.05	99.77	0.00	93.59	0.64	98.08	0.04	99.23	0.10	86.25	0.21	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.97819772
96.07	0.13	98.58	0.04	96.18	0.08	99.77	0.00	94.23	0.64	98.11	0.04	99.33	0.10	86.31	0.05	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3458585948
96.20	0.13	98.58	0.00	96.18	0.00	99.77	0.00	94.23	0.00	98.11	0.00	99.33	0.00	87.20	0.89	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2982557538
96.32	0.12	98.62	0.04	96.21	0.03	99.77	0.00	94.87	0.64	98.15	0.04	99.42	0.10	87.20	0.00	/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2057525318
96.44	0.12	98.66	0.04	96.23	0.03	99.77	0.00	95.51	0.64	98.19	0.04	99.52	0.10	87.20	0.00	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3443447994
96.54	0.10	98.68	0.02	96.23	0.00	99.77	0.00	95.51	0.00	98.19	0.00	99.52	0.00	87.88	0.68	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1317223779
96.64	0.10	98.69	0.02	96.23	0.00	99.77	0.00	96.15	0.64	98.23	0.04	99.52	0.00	87.88	0.00	/workspace/coverage/default/12.sysrst_ctrl_edge_detect.3495783621
96.74	0.10	98.71	0.02	96.23	0.00	99.77	0.00	96.79	0.64	98.26	0.04	99.52	0.00	87.88	0.00	/workspace/coverage/default/24.sysrst_ctrl_edge_detect.2055477803
96.84	0.10	98.73	0.02	96.23	0.00	99.77	0.00	97.44	0.64	98.30	0.04	99.52	0.00	87.88	0.00	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.1846279560
96.93	0.09	98.73	0.00	96.23	0.00	99.77	0.00	97.44	0.00	98.30	0.00	99.52	0.00	88.51	0.63	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3327069324
97.00	0.07	98.75	0.02	96.23	0.00	99.77	0.00	97.44	0.00	98.30	0.00	99.52	0.00	88.98	0.47	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2395884235
97.07	0.07	98.75	0.00	96.23	0.00	99.77	0.00	97.44	0.00	98.30	0.00	99.52	0.00	89.45	0.47	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3401091271
97.13	0.06	98.81	0.06	96.31	0.08	100.00	0.23	97.44	0.00	98.30	0.00	99.52	0.00	89.51	0.05	/workspace/coverage/default/35.sysrst_ctrl_alert_test.267355434
97.18	0.06	98.84	0.04	96.31	0.00	100.00	0.00	97.44	0.00	98.30	0.00	99.52	0.00	89.87	0.37	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2821333670
97.22	0.04	98.88	0.04	96.46	0.15	100.00	0.00	97.44	0.00	98.37	0.07	99.52	0.00	89.87	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.207046791
97.26	0.04	98.88	0.00	96.46	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.52	0.00	90.14	0.26	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.2653734051
97.30	0.04	98.88	0.00	96.46	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.52	0.00	90.40	0.26	/workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.4169848441
97.33	0.03	98.88	0.00	96.49	0.03	100.00	0.00	97.44	0.00	98.37	0.00	99.52	0.00	90.61	0.21	/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2168838365
97.36	0.03	98.88	0.00	96.49	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.52	0.00	90.82	0.21	/workspace/coverage/default/2.sysrst_ctrl_combo_detect.3333843709
97.39	0.03	98.88	0.00	96.49	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.52	0.00	91.03	0.21	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2546609730
97.42	0.03	98.88	0.00	96.49	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.52	0.00	91.24	0.21	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3758123463
97.45	0.03	98.88	0.00	96.49	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.19	91.24	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3922077167
97.47	0.03	98.88	0.00	96.66	0.18	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	91.24	0.00	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3334780914
97.49	0.02	98.88	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	91.40	0.16	/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2019344524
97.52	0.02	98.88	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	91.55	0.16	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2291946985
97.53	0.01	98.88	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	91.66	0.10	/workspace/coverage/default/10.sysrst_ctrl_combo_detect.2800827169
97.55	0.01	98.88	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	91.76	0.10	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3476070769
97.56	0.01	98.88	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	91.87	0.10	/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1092437884
97.58	0.01	98.88	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	91.97	0.10	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.133327535
97.59	0.01	98.88	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.08	0.10	/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.876370879
97.60	0.01	98.90	0.02	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.13	0.05	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3883989041
97.61	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.18	0.05	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3781025582
97.62	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.24	0.05	/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.4241570461
97.62	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.29	0.05	/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.23612837
97.63	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.34	0.05	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1867520344
97.64	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.39	0.05	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2073084745
97.65	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.44	0.05	/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4146445980
97.65	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.50	0.05	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2992609879
97.66	0.01	98.90	0.00	96.66	0.00	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.55	0.05	/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1516914354
97.67	0.01	98.90	0.00	96.71	0.05	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.55	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2003065077
97.67	0.01	98.90	0.00	96.74	0.03	100.00	0.00	97.44	0.00	98.37	0.00	99.71	0.00	92.55	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.836746845

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1849600242
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3235733168
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.853348209
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2163167963
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1873191074
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3084454217
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.799717870
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2422198748
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.992469690
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3449544706
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3953931782
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.258134604
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1867224135
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.249417221
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3172405095
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.583265492
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1771318941
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3355764536
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4271591708
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1752533794
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.759042143
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4238746571
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.244047711
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1077191065
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1845821799
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1680413327
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3208510464
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3388468420
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1120228723
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3686168221
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3743282557
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.389298971
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3109154093
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1173553224
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2146406638
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1204166152
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3557687051
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3780799048
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.690441336
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1648498378
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3632536220
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4028279372
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2863396216
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1882267015
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3746243772
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1432392784
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2790891025
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1196534834
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.354725158
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2307982489
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2506895791
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1199254810
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.605262481
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.942139353
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2968985649
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2475606667
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2981140218
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1751256957
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.668448554
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2366851532
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.13065261
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1274881320
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.870165484
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2351902997
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/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1906753263
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4067832119
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.860914616
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.4016355211
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.741333777
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2199591966
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3401464863
/workspace/coverage/default/40.sysrst_ctrl_smoke.2313663769
/workspace/coverage/default/40.sysrst_ctrl_stress_all.2663356242
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3107524455
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.16710474
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3255456305
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3120804961
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.542274077
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2631834671
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.877873158
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2600415490
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3973826245
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3987880313
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2315196374
/workspace/coverage/default/41.sysrst_ctrl_smoke.4213188218
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2288707055
/workspace/coverage/default/42.sysrst_ctrl_alert_test.30905677
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.649082046
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3994082497
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3865033836
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.958019905
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3883282338
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1938204942
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1955904747
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.890802822
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2630292003
/workspace/coverage/default/42.sysrst_ctrl_smoke.1032231863
/workspace/coverage/default/42.sysrst_ctrl_stress_all.707879269
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2944518636
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.73058348
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1057810686
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.682891966
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1722863541
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1718195060
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3384346546
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1977270716
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3615361553
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1362710865
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3336714617
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.343350645
/workspace/coverage/default/43.sysrst_ctrl_smoke.1430892677
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3086874719
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1938805988
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1462047736
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2821542357
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1558562203
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.401367980
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1929766162
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2713141996
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3640480181
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.937706415
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.287668914
/workspace/coverage/default/44.sysrst_ctrl_smoke.1114866013
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1349723637
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2095676994
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2424346329
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4264738488
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2735903827
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2051814804
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2215790608
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2463592703
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.735323981
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.941209382
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1279892794
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.851183116
/workspace/coverage/default/45.sysrst_ctrl_smoke.1021781370
/workspace/coverage/default/45.sysrst_ctrl_stress_all.3745411115
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3076334325
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3203948420
/workspace/coverage/default/46.sysrst_ctrl_alert_test.763534602
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3885129128
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.932796613
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3136009160
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.245354812
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2623971336
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3772745782
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1380559401
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.895208189
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1193871341
/workspace/coverage/default/46.sysrst_ctrl_smoke.3563257005
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1325737219
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.690679549
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1316703306
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3158434770
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2879700583
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3723442007
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1307748787
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.310510769
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3136725657
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1623897853
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.609293908
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.410300761
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2102848640
/workspace/coverage/default/47.sysrst_ctrl_smoke.1035005240
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2047778582
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.544333506
/workspace/coverage/default/48.sysrst_ctrl_alert_test.629433003
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2316201888
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3092628894
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4101811780
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2791985585
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3236285751
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1460300561
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.852064705
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2151759243
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4290627445
/workspace/coverage/default/48.sysrst_ctrl_smoke.3806378339
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1886305055
/workspace/coverage/default/49.sysrst_ctrl_alert_test.218981587
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1001738402
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3178932478
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.56823623
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.808541567
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.637198196
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2978489241
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.125740405
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2792727400
/workspace/coverage/default/49.sysrst_ctrl_smoke.2060166927
/workspace/coverage/default/49.sysrst_ctrl_stress_all.4143224713
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2252581259
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1828734939
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1703828012
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.309575323
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2292861685
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.760247621
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1375072603
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3533808828
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1874574823
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1031640788
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1313373335
/workspace/coverage/default/5.sysrst_ctrl_smoke.2006399171
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1197793576
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3985295986
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2605955123
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.251530999
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1519704949
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2915783644
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.238646544
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1302541578
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4016417955
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2034283577
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1546730505
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1063216868
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.298776523
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3837222333
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2433806110
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.386491312
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.838875148
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.298896612
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1959789322
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2191536112
/workspace/coverage/default/6.sysrst_ctrl_smoke.3448559612
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1868517973
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2442303331
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.992198817
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3343739870
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1347176125
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1682858063
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.512354390
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2135950723
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2386037770
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1975531584
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2824467432
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.738504322
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.68268535
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3498138358
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2310156149
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2609350541
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1361328434
/workspace/coverage/default/7.sysrst_ctrl_smoke.3379235077
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3654186006
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2961757269
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1621488865
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2326304716
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3409716792
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2699155263
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.94260057
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1745924410
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1360959079
/workspace/coverage/default/8.sysrst_ctrl_alert_test.4053218172
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2282783325
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3318723711
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3298949415
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3716607765
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1313609531
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3122360689
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.995388970
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.522134283
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.188958150
/workspace/coverage/default/8.sysrst_ctrl_smoke.2487693910
/workspace/coverage/default/8.sysrst_ctrl_stress_all.56718687
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4105498701
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.158574030
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.681264458
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.973565624
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2076579536
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2925269267
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3741835465
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.923597685
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1564338738
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3627346258
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2694597131
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.939952852
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1291032161
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.419457014
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1426261407
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3002900817
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2453164234
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1478625463
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3876588936
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.197680907
/workspace/coverage/default/9.sysrst_ctrl_smoke.2642494690
/workspace/coverage/default/9.sysrst_ctrl_stress_all.4071409888
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2528155360
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1835496692
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1192609583
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.776687283
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2578896185
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2028270502
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3258684166
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2669272223
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2520210843

Total test records in report: 908

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4188841492	Aug 06 06:39:49 PM PDT 24	Aug 06 06:39:54 PM PDT 24	3197456490 ps
T5	/workspace/coverage/default/33.sysrst_ctrl_smoke.2320248996	Aug 06 06:41:27 PM PDT 24	Aug 06 06:41:31 PM PDT 24	2115419917 ps
T6	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1975531584	Aug 06 06:38:58 PM PDT 24	Aug 06 06:43:04 PM PDT 24	97519557491 ps
T22	/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.410300761	Aug 06 06:42:34 PM PDT 24	Aug 06 06:42:40 PM PDT 24	2018289504 ps
T23	/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1602665187	Aug 06 06:40:21 PM PDT 24	Aug 06 06:40:24 PM PDT 24	2140979170 ps
T24	/workspace/coverage/default/47.sysrst_ctrl_smoke.1035005240	Aug 06 06:42:35 PM PDT 24	Aug 06 06:42:41 PM PDT 24	2111291674 ps
T25	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.2027235180	Aug 06 06:39:49 PM PDT 24	Aug 06 06:39:53 PM PDT 24	2461826161 ps
T1	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.1651731244	Aug 06 06:38:16 PM PDT 24	Aug 06 06:40:09 PM PDT 24	42077118731 ps
T14	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.626806476	Aug 06 06:39:48 PM PDT 24	Aug 06 06:39:55 PM PDT 24	2610256673 ps
T15	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3971557127	Aug 06 06:41:23 PM PDT 24	Aug 06 06:41:30 PM PDT 24	2513840644 ps
T16	/workspace/coverage/default/43.sysrst_ctrl_smoke.1430892677	Aug 06 06:42:09 PM PDT 24	Aug 06 06:42:15 PM PDT 24	2109658459 ps
T17	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2879700583	Aug 06 06:42:35 PM PDT 24	Aug 06 06:43:29 PM PDT 24	62501198685 ps
T18	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.487429068	Aug 06 06:41:01 PM PDT 24	Aug 06 06:41:07 PM PDT 24	2612187428 ps
T19	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1946045131	Aug 06 06:38:40 PM PDT 24	Aug 06 06:38:43 PM PDT 24	3286924188 ps
T20	/workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2534793065	Aug 06 06:39:52 PM PDT 24	Aug 06 06:39:54 PM PDT 24	2478011784 ps
T21	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1046835639	Aug 06 06:41:26 PM PDT 24	Aug 06 06:41:29 PM PDT 24	2106443914 ps
T2	/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1291032161	Aug 06 06:39:00 PM PDT 24	Aug 06 06:45:03 PM PDT 24	139884434312 ps
T66	/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.4241570461	Aug 06 06:38:18 PM PDT 24	Aug 06 06:38:23 PM PDT 24	2518048821 ps
T47	/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2259267192	Aug 06 06:41:38 PM PDT 24	Aug 06 06:41:48 PM PDT 24	3827981335 ps
T3	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.414014926	Aug 06 06:38:16 PM PDT 24	Aug 06 06:39:12 PM PDT 24	49528066437 ps
T48	/workspace/coverage/default/25.sysrst_ctrl_combo_detect.2481593027	Aug 06 06:40:25 PM PDT 24	Aug 06 06:43:34 PM PDT 24	77874963261 ps
T7	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2605955123	Aug 06 06:42:39 PM PDT 24	Aug 06 06:43:24 PM PDT 24	64496955331 ps
T8	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2446966899	Aug 06 06:39:28 PM PDT 24	Aug 06 06:43:12 PM PDT 24	1518298238947 ps
T55	/workspace/coverage/default/35.sysrst_ctrl_alert_test.267355434	Aug 06 06:41:25 PM PDT 24	Aug 06 06:41:27 PM PDT 24	2027991545 ps
T9	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.4224900164	Aug 06 06:39:51 PM PDT 24	Aug 06 06:39:53 PM PDT 24	3566911068 ps
T49	/workspace/coverage/default/4.sysrst_ctrl_combo_detect.2219624640	Aug 06 06:38:39 PM PDT 24	Aug 06 06:40:17 PM PDT 24	36738172126 ps
T56	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.337774240	Aug 06 06:40:44 PM PDT 24	Aug 06 06:40:49 PM PDT 24	2616895113 ps
T10	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1625462291	Aug 06 06:38:16 PM PDT 24	Aug 06 06:38:18 PM PDT 24	2565343056 ps
T50	/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1686173083	Aug 06 06:39:47 PM PDT 24	Aug 06 06:40:04 PM PDT 24	32660210962 ps
T57	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.3310949683	Aug 06 06:39:48 PM PDT 24	Aug 06 06:39:50 PM PDT 24	2492671218 ps
T70	/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.958019905	Aug 06 06:42:06 PM PDT 24	Aug 06 06:42:15 PM PDT 24	2854566607 ps
T76	/workspace/coverage/default/12.sysrst_ctrl_alert_test.1972545919	Aug 06 06:39:46 PM PDT 24	Aug 06 06:39:48 PM PDT 24	2032214611 ps
T11	/workspace/coverage/default/0.sysrst_ctrl_stress_all.863915079	Aug 06 06:38:19 PM PDT 24	Aug 06 06:38:31 PM PDT 24	23832525610 ps
T12	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.3743133680	Aug 06 06:39:53 PM PDT 24	Aug 06 06:40:03 PM PDT 24	3347718487 ps
T13	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2320903119	Aug 06 06:39:27 PM PDT 24	Aug 06 06:45:00 PM PDT 24	1471234393562 ps
T111	/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.2270267065	Aug 06 06:40:44 PM PDT 24	Aug 06 06:40:49 PM PDT 24	2107631226 ps
T35	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2546609730	Aug 06 06:42:34 PM PDT 24	Aug 06 06:43:32 PM PDT 24	146444818314 ps
T41	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.1947291417	Aug 06 06:38:19 PM PDT 24	Aug 06 06:38:26 PM PDT 24	2725829195 ps
T64	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1874574823	Aug 06 06:38:43 PM PDT 24	Aug 06 06:38:46 PM PDT 24	2492914795 ps
T65	/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2164935761	Aug 06 06:40:45 PM PDT 24	Aug 06 06:40:47 PM PDT 24	2476204164 ps
T44	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.3546592541	Aug 06 06:40:27 PM PDT 24	Aug 06 06:40:32 PM PDT 24	4266196466 ps
T51	/workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.4271960687	Aug 06 06:41:22 PM PDT 24	Aug 06 06:41:31 PM PDT 24	3133338747 ps
T285	/workspace/coverage/default/8.sysrst_ctrl_alert_test.4053218172	Aug 06 06:39:04 PM PDT 24	Aug 06 06:39:06 PM PDT 24	2093817227 ps
T31	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1564338738	Aug 06 06:42:51 PM PDT 24	Aug 06 06:43:09 PM PDT 24	26099009924 ps
T61	/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.73058348	Aug 06 06:42:07 PM PDT 24	Aug 06 06:42:11 PM PDT 24	3241625754 ps
T250	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.4092506342	Aug 06 06:41:39 PM PDT 24	Aug 06 06:41:41 PM PDT 24	2184508033 ps
T251	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2398926509	Aug 06 06:41:25 PM PDT 24	Aug 06 06:41:28 PM PDT 24	2060909546 ps
T32	/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2925269267	Aug 06 06:42:56 PM PDT 24	Aug 06 06:43:30 PM PDT 24	26838667832 ps
T52	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2298311260	Aug 06 06:40:21 PM PDT 24	Aug 06 06:40:24 PM PDT 24	2992535943 ps
T36	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4135674518	Aug 06 06:42:37 PM PDT 24	Aug 06 06:43:16 PM PDT 24	71268949267 ps
T237	/workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2232571800	Aug 06 06:40:17 PM PDT 24	Aug 06 06:40:24 PM PDT 24	2609442848 ps
T39	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.2815223704	Aug 06 06:40:47 PM PDT 24	Aug 06 06:40:55 PM PDT 24	4421576440 ps
T60	/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3783934921	Aug 06 06:41:24 PM PDT 24	Aug 06 06:41:26 PM PDT 24	5850317455 ps
T45	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3883989041	Aug 06 06:40:27 PM PDT 24	Aug 06 06:41:04 PM PDT 24	55420308056 ps
T137	/workspace/coverage/default/0.sysrst_ctrl_smoke.566591617	Aug 06 06:38:07 PM PDT 24	Aug 06 06:38:12 PM PDT 24	2114491723 ps
T138	/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.634694860	Aug 06 06:38:42 PM PDT 24	Aug 06 06:38:49 PM PDT 24	2514156563 ps
T37	/workspace/coverage/default/34.sysrst_ctrl_combo_detect.588523531	Aug 06 06:41:23 PM PDT 24	Aug 06 06:42:49 PM PDT 24	164796676041 ps
T139	/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1145570498	Aug 06 06:41:37 PM PDT 24	Aug 06 06:41:39 PM PDT 24	2099660585 ps
T140	/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.588172066	Aug 06 06:40:45 PM PDT 24	Aug 06 06:40:47 PM PDT 24	2156034195 ps
T141	/workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1941145344	Aug 06 06:38:40 PM PDT 24	Aug 06 06:38:48 PM PDT 24	2611982626 ps
T142	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.838875148	Aug 06 06:38:44 PM PDT 24	Aug 06 06:38:45 PM PDT 24	2677098111 ps
T143	/workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3973019623	Aug 06 06:39:47 PM PDT 24	Aug 06 06:39:48 PM PDT 24	3241385078 ps
T53	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.4009292031	Aug 06 06:39:26 PM PDT 24	Aug 06 06:39:31 PM PDT 24	3028342669 ps
T390	/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.2628309789	Aug 06 06:39:29 PM PDT 24	Aug 06 06:39:36 PM PDT 24	2441045707 ps
T38	/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1467611189	Aug 06 06:42:48 PM PDT 24	Aug 06 06:47:00 PM PDT 24	97543016106 ps
T260	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.2545121534	Aug 06 06:39:29 PM PDT 24	Aug 06 06:40:50 PM PDT 24	134669549686 ps
T88	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.2653734051	Aug 06 06:38:16 PM PDT 24	Aug 06 06:38:53 PM PDT 24	26245938389 ps
T40	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2442303331	Aug 06 06:38:45 PM PDT 24	Aug 06 06:40:40 PM PDT 24	47694682089 ps
T297	/workspace/coverage/default/30.sysrst_ctrl_stress_all.2223018182	Aug 06 06:41:03 PM PDT 24	Aug 06 06:41:07 PM PDT 24	8936897585 ps
T54	/workspace/coverage/default/34.sysrst_ctrl_stress_all.3996315628	Aug 06 06:41:25 PM PDT 24	Aug 06 06:41:41 PM PDT 24	12780436820 ps
T389	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3797343225	Aug 06 06:41:25 PM PDT 24	Aug 06 06:41:29 PM PDT 24	2520912554 ps
T261	/workspace/coverage/default/24.sysrst_ctrl_combo_detect.434753063	Aug 06 06:40:24 PM PDT 24	Aug 06 06:42:17 PM PDT 24	94010840705 ps
T391	/workspace/coverage/default/34.sysrst_ctrl_smoke.2822474395	Aug 06 06:41:27 PM PDT 24	Aug 06 06:41:33 PM PDT 24	2107997099 ps
T265	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.1925419059	Aug 06 06:41:28 PM PDT 24	Aug 06 06:49:27 PM PDT 24	177702072337 ps
T326	/workspace/coverage/default/33.sysrst_ctrl_stress_all.3214943951	Aug 06 06:41:23 PM PDT 24	Aug 06 06:49:18 PM PDT 24	908522463029 ps
T392	/workspace/coverage/default/6.sysrst_ctrl_alert_test.1546730505	Aug 06 06:38:45 PM PDT 24	Aug 06 06:38:49 PM PDT 24	2018777417 ps
T43	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3883282338	Aug 06 06:42:06 PM PDT 24	Aug 06 06:42:13 PM PDT 24	3444768257 ps
T46	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2821333670	Aug 06 06:40:24 PM PDT 24	Aug 06 06:40:36 PM PDT 24	73620310732 ps
T62	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.97819772	Aug 06 06:42:07 PM PDT 24	Aug 06 06:43:18 PM PDT 24	59900815606 ps
T114	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3566222908	Aug 06 06:39:01 PM PDT 24	Aug 06 06:39:04 PM PDT 24	2464589444 ps
T115	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3401464863	Aug 06 06:41:38 PM PDT 24	Aug 06 06:41:41 PM PDT 24	2525695057 ps
T116	/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.4239559395	Aug 06 06:41:03 PM PDT 24	Aug 06 06:41:10 PM PDT 24	2462481586 ps
T117	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1959789322	Aug 06 06:38:42 PM PDT 24	Aug 06 06:38:44 PM PDT 24	2122881475 ps
T118	/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1944025673	Aug 06 06:40:21 PM PDT 24	Aug 06 06:40:24 PM PDT 24	2482162952 ps
T119	/workspace/coverage/default/3.sysrst_ctrl_smoke.1345543014	Aug 06 06:38:41 PM PDT 24	Aug 06 06:38:44 PM PDT 24	2127285228 ps
T120	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.741333777	Aug 06 06:41:41 PM PDT 24	Aug 06 06:41:44 PM PDT 24	2483188890 ps
T63	/workspace/coverage/default/43.sysrst_ctrl_stress_all.3086874719	Aug 06 06:42:05 PM PDT 24	Aug 06 06:42:14 PM PDT 24	13047461260 ps
T121	/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2180614556	Aug 06 06:41:22 PM PDT 24	Aug 06 06:41:37 PM PDT 24	5615119280 ps
T67	/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.923597685	Aug 06 06:42:50 PM PDT 24	Aug 06 06:43:36 PM PDT 24	71109522497 ps
T42	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3236285751	Aug 06 06:42:38 PM PDT 24	Aug 06 06:42:48 PM PDT 24	3997741454 ps
T393	/workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1844172501	Aug 06 06:40:33 PM PDT 24	Aug 06 06:40:44 PM PDT 24	3690898190 ps
T394	/workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2475276169	Aug 06 06:41:25 PM PDT 24	Aug 06 06:41:29 PM PDT 24	2616077374 ps
T72	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2036113334	Aug 06 06:39:26 PM PDT 24	Aug 06 06:41:16 PM PDT 24	44816721199 ps
T159	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2463592703	Aug 06 06:42:34 PM PDT 24	Aug 06 06:42:38 PM PDT 24	4011687206 ps
T302	/workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3570709020	Aug 06 06:38:18 PM PDT 24	Aug 06 06:38:25 PM PDT 24	2510481025 ps
T68	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3402012665	Aug 06 06:41:22 PM PDT 24	Aug 06 06:41:49 PM PDT 24	20336293245 ps
T395	/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3632285153	Aug 06 06:41:02 PM PDT 24	Aug 06 06:41:08 PM PDT 24	2071519700 ps
T69	/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3741835465	Aug 06 06:42:50 PM PDT 24	Aug 06 06:43:08 PM PDT 24	26358118346 ps
T73	/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1818987766	Aug 06 06:40:36 PM PDT 24	Aug 06 06:40:39 PM PDT 24	7122501394 ps
T396	/workspace/coverage/default/0.sysrst_ctrl_alert_test.782554540	Aug 06 06:38:18 PM PDT 24	Aug 06 06:38:19 PM PDT 24	2040325418 ps
T397	/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3659913779	Aug 06 06:40:16 PM PDT 24	Aug 06 06:40:24 PM PDT 24	3671623666 ps
T71	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2578896185	Aug 06 06:42:51 PM PDT 24	Aug 06 06:43:04 PM PDT 24	51067324779 ps
T398	/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2215790608	Aug 06 06:42:38 PM PDT 24	Aug 06 06:42:40 PM PDT 24	2726191656 ps
T74	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2648870512	Aug 06 06:39:50 PM PDT 24	Aug 06 06:42:49 PM PDT 24	422623351913 ps
T399	/workspace/coverage/default/49.sysrst_ctrl_smoke.2060166927	Aug 06 06:42:34 PM PDT 24	Aug 06 06:42:40 PM PDT 24	2113256458 ps
T252	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1588468561	Aug 06 06:38:41 PM PDT 24	Aug 06 06:38:42 PM PDT 24	2585219037 ps
T400	/workspace/coverage/default/26.sysrst_ctrl_smoke.3674120928	Aug 06 06:40:26 PM PDT 24	Aug 06 06:40:29 PM PDT 24	2114225772 ps
T259	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.3135242482	Aug 06 06:40:18 PM PDT 24	Aug 06 06:42:01 PM PDT 24	39565376467 ps
T401	/workspace/coverage/default/8.sysrst_ctrl_smoke.2487693910	Aug 06 06:38:57 PM PDT 24	Aug 06 06:38:58 PM PDT 24	2159951802 ps
T300	/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3898709155	Aug 06 06:39:51 PM PDT 24	Aug 06 06:39:55 PM PDT 24	2468770130 ps
T402	/workspace/coverage/default/22.sysrst_ctrl_alert_test.2056644296	Aug 06 06:40:25 PM PDT 24	Aug 06 06:40:27 PM PDT 24	2046265784 ps
T75	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3654186006	Aug 06 06:39:45 PM PDT 24	Aug 06 06:41:40 PM PDT 24	48487565119 ps
T58	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1146747042	Aug 06 06:38:16 PM PDT 24	Aug 06 06:38:38 PM PDT 24	33859376089 ps
T107	/workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3559246575	Aug 06 06:40:46 PM PDT 24	Aug 06 06:40:48 PM PDT 24	7887712860 ps
T403	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2254610047	Aug 06 06:40:26 PM PDT 24	Aug 06 06:40:28 PM PDT 24	7551306855 ps
T59	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.836746845	Aug 06 06:38:19 PM PDT 24	Aug 06 06:39:56 PM PDT 24	38057479057 ps
T404	/workspace/coverage/default/27.sysrst_ctrl_stress_all.2216700442	Aug 06 06:40:48 PM PDT 24	Aug 06 06:41:09 PM PDT 24	15634053420 ps
T405	/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.781460537	Aug 06 06:40:16 PM PDT 24	Aug 06 06:40:19 PM PDT 24	3431027883 ps
T406	/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3834150022	Aug 06 06:40:51 PM PDT 24	Aug 06 06:40:54 PM PDT 24	2525722670 ps
T407	/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.760247621	Aug 06 06:38:39 PM PDT 24	Aug 06 06:38:42 PM PDT 24	4186745270 ps
T408	/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.4136357207	Aug 06 06:39:04 PM PDT 24	Aug 06 06:39:06 PM PDT 24	2103236510 ps
T409	/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2792727400	Aug 06 06:42:38 PM PDT 24	Aug 06 06:42:45 PM PDT 24	2512744923 ps
T410	/workspace/coverage/default/29.sysrst_ctrl_alert_test.822566590	Aug 06 06:41:00 PM PDT 24	Aug 06 06:41:05 PM PDT 24	2019177693 ps
T411	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.3519093591	Aug 06 06:39:27 PM PDT 24	Aug 06 06:39:35 PM PDT 24	2469429313 ps
T253	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1317223779	Aug 06 06:38:17 PM PDT 24	Aug 06 06:39:30 PM PDT 24	95571610524 ps
T89	/workspace/coverage/default/19.sysrst_ctrl_stress_all.4153332100	Aug 06 06:40:17 PM PDT 24	Aug 06 06:41:44 PM PDT 24	128768327471 ps
T412	/workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.77042640	Aug 06 06:38:38 PM PDT 24	Aug 06 06:38:44 PM PDT 24	2458332014 ps
T87	/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.992198817	Aug 06 06:39:05 PM PDT 24	Aug 06 06:39:08 PM PDT 24	46589705945 ps
T146	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.691148328	Aug 06 06:40:16 PM PDT 24	Aug 06 06:40:23 PM PDT 24	2739680963 ps
T413	/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1362710865	Aug 06 06:42:08 PM PDT 24	Aug 06 06:42:15 PM PDT 24	2461430604 ps
T414	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.123107052	Aug 06 06:39:53 PM PDT 24	Aug 06 06:40:01 PM PDT 24	2610824880 ps
T171	/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1929766162	Aug 06 06:42:07 PM PDT 24	Aug 06 06:42:17 PM PDT 24	3984264827 ps
T415	/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.98120287	Aug 06 06:39:29 PM PDT 24	Aug 06 06:39:33 PM PDT 24	3215473803 ps
T90	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1745924410	Aug 06 06:42:55 PM PDT 24	Aug 06 06:43:02 PM PDT 24	21113472531 ps
T254	/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1043942646	Aug 06 06:39:51 PM PDT 24	Aug 06 06:47:03 PM PDT 24	176343724932 ps
T255	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3560297006	Aug 06 06:42:51 PM PDT 24	Aug 06 06:44:40 PM PDT 24	161747144780 ps
T416	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.900458354	Aug 06 06:38:41 PM PDT 24	Aug 06 06:38:48 PM PDT 24	2332940994 ps
T417	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3542888615	Aug 06 06:39:00 PM PDT 24	Aug 06 06:39:06 PM PDT 24	2146594169 ps
T418	/workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2147720972	Aug 06 06:40:17 PM PDT 24	Aug 06 06:40:19 PM PDT 24	2215291410 ps
T419	/workspace/coverage/default/2.sysrst_ctrl_pin_access_test.755392095	Aug 06 06:38:45 PM PDT 24	Aug 06 06:38:47 PM PDT 24	2094570208 ps
T108	/workspace/coverage/default/2.sysrst_ctrl_stress_all.1345099913	Aug 06 06:38:44 PM PDT 24	Aug 06 06:39:04 PM PDT 24	18774359339 ps
T167	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.1727582236	Aug 06 06:40:16 PM PDT 24	Aug 06 06:40:19 PM PDT 24	4113849366 ps
T258	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1558578930	Aug 06 06:38:15 PM PDT 24	Aug 06 06:42:34 PM PDT 24	95908214336 ps
T91	/workspace/coverage/default/32.sysrst_ctrl_stress_all.3409314376	Aug 06 06:41:21 PM PDT 24	Aug 06 06:43:45 PM PDT 24	55284883604 ps
T420	/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2791985585	Aug 06 06:42:34 PM PDT 24	Aug 06 06:43:30 PM PDT 24	219729754094 ps
T78	/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2188405542	Aug 06 06:42:36 PM PDT 24	Aug 06 06:44:20 PM PDT 24	172462077353 ps
T99	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.1885071648	Aug 06 06:41:28 PM PDT 24	Aug 06 06:46:25 PM PDT 24	117325915091 ps
T79	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3568946317	Aug 06 06:39:52 PM PDT 24	Aug 06 06:40:02 PM PDT 24	3667950687 ps
T100	/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3286311734	Aug 06 06:38:41 PM PDT 24	Aug 06 06:38:43 PM PDT 24	3247592758 ps
T101	/workspace/coverage/default/24.sysrst_ctrl_alert_test.2469872524	Aug 06 06:40:27 PM PDT 24	Aug 06 06:40:32 PM PDT 24	2011014821 ps
T102	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.1755723832	Aug 06 06:38:17 PM PDT 24	Aug 06 06:38:31 PM PDT 24	22122655928 ps
T103	/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2282783325	Aug 06 06:39:00 PM PDT 24	Aug 06 06:39:10 PM PDT 24	3323613798 ps
T104	/workspace/coverage/default/17.sysrst_ctrl_stress_all.3067796432	Aug 06 06:39:54 PM PDT 24	Aug 06 06:40:00 PM PDT 24	8580643815 ps
T105	/workspace/coverage/default/19.sysrst_ctrl_smoke.1776895975	Aug 06 06:39:53 PM PDT 24	Aug 06 06:39:55 PM PDT 24	2124108985 ps
T106	/workspace/coverage/default/35.sysrst_ctrl_stress_all.924273722	Aug 06 06:41:21 PM PDT 24	Aug 06 06:41:50 PM PDT 24	11982048802 ps
T292	/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1063216868	Aug 06 06:38:44 PM PDT 24	Aug 06 06:38:52 PM PDT 24	3099423311 ps
T293	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1543726513	Aug 06 06:39:54 PM PDT 24	Aug 06 06:39:57 PM PDT 24	3283340443 ps
T267	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3841409218	Aug 06 06:40:21 PM PDT 24	Aug 06 06:40:34 PM PDT 24	96999745123 ps
T294	/workspace/coverage/default/46.sysrst_ctrl_combo_detect.932796613	Aug 06 06:42:32 PM PDT 24	Aug 06 06:44:01 PM PDT 24	138569804446 ps
T109	/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2961757269	Aug 06 06:38:48 PM PDT 24	Aug 06 06:38:55 PM PDT 24	4069207592 ps
T421	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.851183116	Aug 06 06:42:31 PM PDT 24	Aug 06 06:42:33 PM PDT 24	2535606980 ps
T422	/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3615361553	Aug 06 06:42:08 PM PDT 24	Aug 06 06:42:10 PM PDT 24	2633130835 ps
T80	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2166881190	Aug 06 06:41:27 PM PDT 24	Aug 06 06:42:42 PM PDT 24	115420907438 ps
T92	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.1659031246	Aug 06 06:40:26 PM PDT 24	Aug 06 06:42:47 PM PDT 24	57408000908 ps
T127	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.3618721278	Aug 06 06:41:01 PM PDT 24	Aug 06 06:41:33 PM PDT 24	62232299619 ps
T128	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1255952140	Aug 06 06:40:36 PM PDT 24	Aug 06 06:40:44 PM PDT 24	2512756437 ps
T129	/workspace/coverage/default/35.sysrst_ctrl_edge_detect.3663754946	Aug 06 06:41:25 PM PDT 24	Aug 06 06:41:34 PM PDT 24	4997620995 ps
T130	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.251530999	Aug 06 06:42:35 PM PDT 24	Aug 06 06:43:30 PM PDT 24	22583741770 ps
T131	/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3795284702	Aug 06 06:40:16 PM PDT 24	Aug 06 06:40:19 PM PDT 24	2157548398 ps
T132	/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2076579536	Aug 06 06:42:49 PM PDT 24	Aug 06 06:43:06 PM PDT 24	23602928478 ps
T133	/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.834585998	Aug 06 06:39:45 PM PDT 24	Aug 06 06:39:47 PM PDT 24	2532375903 ps
T134	/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3644068378	Aug 06 06:41:30 PM PDT 24	Aug 06 06:41:37 PM PDT 24	2470942017 ps
T423	/workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.702231478	Aug 06 06:38:18 PM PDT 24	Aug 06 06:38:28 PM PDT 24	3421106470 ps
T424	/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1478625463	Aug 06 06:39:01 PM PDT 24	Aug 06 06:39:08 PM PDT 24	2460420630 ps
T147	/workspace/coverage/default/37.sysrst_ctrl_stress_all.3911747145	Aug 06 06:41:39 PM PDT 24	Aug 06 06:41:46 PM PDT 24	9911502932 ps
T425	/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.2872968115	Aug 06 06:41:00 PM PDT 24	Aug 06 06:41:06 PM PDT 24	2204304950 ps
T426	/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2386037770	Aug 06 06:38:46 PM PDT 24	Aug 06 06:38:49 PM PDT 24	2998688230 ps
T83	/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2663794593	Aug 06 06:41:03 PM PDT 24	Aug 06 06:42:16 PM PDT 24	131999172233 ps
T427	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2448087055	Aug 06 06:40:59 PM PDT 24	Aug 06 06:41:05 PM PDT 24	2026139090 ps
T428	/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3375188940	Aug 06 06:38:21 PM PDT 24	Aug 06 06:38:27 PM PDT 24	2140129089 ps
T184	/workspace/coverage/default/32.sysrst_ctrl_edge_detect.3383542893	Aug 06 06:41:21 PM PDT 24	Aug 06 06:41:25 PM PDT 24	2389527696 ps
T186	/workspace/coverage/default/5.sysrst_ctrl_alert_test.1703828012	Aug 06 06:38:41 PM PDT 24	Aug 06 06:38:46 PM PDT 24	2016358750 ps
T187	/workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2373069568	Aug 06 06:38:40 PM PDT 24	Aug 06 06:38:44 PM PDT 24	2522298270 ps
T110	/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2095676994	Aug 06 06:42:08 PM PDT 24	Aug 06 06:42:11 PM PDT 24	11475043190 ps
T188	/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.26755958	Aug 06 06:41:43 PM PDT 24	Aug 06 06:41:56 PM PDT 24	19379024832 ps
T189	/workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.105255077	Aug 06 06:40:30 PM PDT 24	Aug 06 06:40:33 PM PDT 24	3052902628 ps
T190	/workspace/coverage/default/3.sysrst_ctrl_combo_detect.1378459301	Aug 06 06:39:00 PM PDT 24	Aug 06 06:39:53 PM PDT 24	84295209445 ps
T191	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2520210843	Aug 06 06:42:55 PM PDT 24	Aug 06 06:43:14 PM PDT 24	27352012969 ps
T192	/workspace/coverage/default/7.sysrst_ctrl_smoke.3379235077	Aug 06 06:39:20 PM PDT 24	Aug 06 06:39:27 PM PDT 24	2113145745 ps
T193	/workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3962410165	Aug 06 06:41:20 PM PDT 24	Aug 06 06:41:22 PM PDT 24	2629050290 ps
T429	/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1952507861	Aug 06 06:40:17 PM PDT 24	Aug 06 06:40:25 PM PDT 24	2764908652 ps
T430	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.401367980	Aug 06 06:42:07 PM PDT 24	Aug 06 06:42:18 PM PDT 24	3831847931 ps
T431	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.244839235	Aug 06 06:39:28 PM PDT 24	Aug 06 06:39:35 PM PDT 24	2611437138 ps
T432	/workspace/coverage/default/6.sysrst_ctrl_smoke.3448559612	Aug 06 06:38:38 PM PDT 24	Aug 06 06:38:42 PM PDT 24	2116922695 ps
T433	/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1279892794	Aug 06 06:42:37 PM PDT 24	Aug 06 06:42:39 PM PDT 24	2192267312 ps
T434	/workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1185550653	Aug 06 06:38:19 PM PDT 24	Aug 06 06:38:21 PM PDT 24	2522189747 ps
T435	/workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1610439381	Aug 06 06:38:42 PM PDT 24	Aug 06 06:38:45 PM PDT 24	4040089886 ps
T181	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3327069324	Aug 06 06:42:05 PM PDT 24	Aug 06 06:47:03 PM PDT 24	123800371095 ps
T312	/workspace/coverage/default/46.sysrst_ctrl_smoke.3563257005	Aug 06 06:42:34 PM PDT 24	Aug 06 06:42:37 PM PDT 24	2115861511 ps
T313	/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1965321085	Aug 06 06:38:59 PM PDT 24	Aug 06 06:39:01 PM PDT 24	2636009297 ps
T314	/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1005412703	Aug 06 06:40:26 PM PDT 24	Aug 06 06:40:35 PM PDT 24	3419351307 ps
T301	/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1380559401	Aug 06 06:42:32 PM PDT 24	Aug 06 06:42:39 PM PDT 24	2466479419 ps
T315	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2667381525	Aug 06 06:40:46 PM PDT 24	Aug 06 06:41:13 PM PDT 24	58043041008 ps
T256	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3016001467	Aug 06 06:39:53 PM PDT 24	Aug 06 06:40:06 PM PDT 24	25922285395 ps
T316	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1938805988	Aug 06 06:42:06 PM PDT 24	Aug 06 06:42:10 PM PDT 24	7071076882 ps
T317	/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.890802822	Aug 06 06:42:06 PM PDT 24	Aug 06 06:42:08 PM PDT 24	2081204446 ps
T318	/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3610215450	Aug 06 06:38:02 PM PDT 24	Aug 06 06:38:09 PM PDT 24	2093976532 ps
T436	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.147808173	Aug 06 06:39:53 PM PDT 24	Aug 06 06:40:04 PM PDT 24	4278575809 ps
T257	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.776687283	Aug 06 06:42:55 PM PDT 24	Aug 06 06:44:04 PM PDT 24	25580839663 ps
T437	/workspace/coverage/default/5.sysrst_ctrl_smoke.2006399171	Aug 06 06:38:38 PM PDT 24	Aug 06 06:38:41 PM PDT 24	2116133317 ps
T438	/workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3368001157	Aug 06 06:41:23 PM PDT 24	Aug 06 06:41:27 PM PDT 24	2203125388 ps
T156	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3471546455	Aug 06 06:40:16 PM PDT 24	Aug 06 06:41:19 PM PDT 24	94847500183 ps
T439	/workspace/coverage/default/49.sysrst_ctrl_stress_all.4143224713	Aug 06 06:42:37 PM PDT 24	Aug 06 06:43:10 PM PDT 24	13295212885 ps
T373	/workspace/coverage/default/39.sysrst_ctrl_combo_detect.1002505449	Aug 06 06:41:39 PM PDT 24	Aug 06 06:47:35 PM PDT 24	138883092893 ps
T440	/workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.240706716	Aug 06 06:40:46 PM PDT 24	Aug 06 06:40:48 PM PDT 24	3057256311 ps
T347	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.2941278172	Aug 06 06:41:20 PM PDT 24	Aug 06 06:47:55 PM PDT 24	154509804458 ps
T368	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.915603408	Aug 06 06:41:24 PM PDT 24	Aug 06 06:42:28 PM PDT 24	42016749969 ps
T441	/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2307229832	Aug 06 06:38:17 PM PDT 24	Aug 06 06:38:28 PM PDT 24	3903833378 ps
T442	/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1972203111	Aug 06 06:41:04 PM PDT 24	Aug 06 06:41:12 PM PDT 24	6618187021 ps
T77	/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.419457014	Aug 06 06:39:03 PM PDT 24	Aug 06 06:39:53 PM PDT 24	38748285383 ps
T443	/workspace/coverage/default/44.sysrst_ctrl_smoke.1114866013	Aug 06 06:42:07 PM PDT 24	Aug 06 06:42:10 PM PDT 24	2119718941 ps
T444	/workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2520223345	Aug 06 06:39:53 PM PDT 24	Aug 06 06:39:59 PM PDT 24	2191442632 ps
T445	/workspace/coverage/default/6.sysrst_ctrl_edge_detect.386491312	Aug 06 06:38:44 PM PDT 24	Aug 06 06:38:49 PM PDT 24	2391905317 ps
T446	/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3377300121	Aug 06 06:41:29 PM PDT 24	Aug 06 06:41:40 PM PDT 24	3831630283 ps
T148	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.1846279560	Aug 06 06:38:40 PM PDT 24	Aug 06 06:38:48 PM PDT 24	3780503623 ps
T447	/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.961713488	Aug 06 06:38:16 PM PDT 24	Aug 06 06:38:25 PM PDT 24	3032339054 ps
T269	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2051814804	Aug 06 06:42:35 PM PDT 24	Aug 06 06:43:38 PM PDT 24	52605136954 ps
T448	/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.4130022660	Aug 06 06:40:15 PM PDT 24	Aug 06 06:40:19 PM PDT 24	2516129886 ps
T449	/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.310510769	Aug 06 06:42:35 PM PDT 24	Aug 06 06:42:37 PM PDT 24	4373316628 ps
T85	/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.799819622	Aug 06 06:41:06 PM PDT 24	Aug 06 06:41:14 PM PDT 24	4970888788 ps
T450	/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.343350645	Aug 06 06:42:06 PM PDT 24	Aug 06 06:42:08 PM PDT 24	2536719349 ps
T451	/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2933177048	Aug 06 06:41:43 PM PDT 24	Aug 06 06:41:49 PM PDT 24	5837218439 ps
T168	/workspace/coverage/default/48.sysrst_ctrl_stress_all.1886305055	Aug 06 06:42:35 PM PDT 24	Aug 06 06:42:42 PM PDT 24	10621174886 ps
T452	/workspace/coverage/default/14.sysrst_ctrl_smoke.1212876381	Aug 06 06:39:27 PM PDT 24	Aug 06 06:39:29 PM PDT 24	2137869836 ps
T453	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1290266021	Aug 06 06:41:26 PM PDT 24	Aug 06 06:41:30 PM PDT 24	2619467028 ps
T303	/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2718834709	Aug 06 06:41:39 PM PDT 24	Aug 06 06:41:42 PM PDT 24	2531257942 ps
T262	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.2701767159	Aug 06 06:39:24 PM PDT 24	Aug 06 06:42:06 PM PDT 24	62902919271 ps
T454	/workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3403474019	Aug 06 06:38:20 PM PDT 24	Aug 06 06:38:28 PM PDT 24	2612972476 ps
T455	/workspace/coverage/default/2.sysrst_ctrl_smoke.1855958498	Aug 06 06:38:16 PM PDT 24	Aug 06 06:38:18 PM PDT 24	2123251414 ps
T456	/workspace/coverage/default/30.sysrst_ctrl_smoke.3452626199	Aug 06 06:41:05 PM PDT 24	Aug 06 06:41:11 PM PDT 24	2110099252 ps
T363	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2395884235	Aug 06 06:42:50 PM PDT 24	Aug 06 06:47:54 PM PDT 24	228914951888 ps
T457	/workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1925759143	Aug 06 06:41:40 PM PDT 24	Aug 06 06:41:42 PM PDT 24	2890997687 ps
T458	/workspace/coverage/default/11.sysrst_ctrl_alert_test.779478916	Aug 06 06:39:04 PM PDT 24	Aug 06 06:39:08 PM PDT 24	2017321692 ps
T459	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3002900817	Aug 06 06:38:59 PM PDT 24	Aug 06 06:39:06 PM PDT 24	2478187902 ps
T460	/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1329916126	Aug 06 06:41:39 PM PDT 24	Aug 06 06:41:46 PM PDT 24	6041666586 ps
T461	/workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.272586216	Aug 06 06:40:27 PM PDT 24	Aug 06 06:40:31 PM PDT 24	2477063881 ps
T462	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.287668914	Aug 06 06:42:07 PM PDT 24	Aug 06 06:42:08 PM PDT 24	2545981659 ps
T463	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.56823623	Aug 06 06:42:32 PM PDT 24	Aug 06 06:42:50 PM PDT 24	47138115780 ps
T464	/workspace/coverage/default/23.sysrst_ctrl_smoke.2323717282	Aug 06 06:40:21 PM PDT 24	Aug 06 06:40:27 PM PDT 24	2112039790 ps
T465	/workspace/coverage/default/26.sysrst_ctrl_alert_test.3188568653	Aug 06 06:40:44 PM PDT 24	Aug 06 06:40:46 PM PDT 24	2037065204 ps