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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.68 98.90 96.76 100.00 97.44 98.37 99.71 92.55


Total test records in report: 908
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T466 /workspace/coverage/default/10.sysrst_ctrl_alert_test.1053036646 Aug 06 06:39:01 PM PDT 24 Aug 06 06:39:03 PM PDT 24 2030121117 ps
T274 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.4255936959 Aug 06 06:38:43 PM PDT 24 Aug 06 06:38:54 PM PDT 24 22114674674 ps
T467 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1938204942 Aug 06 06:42:05 PM PDT 24 Aug 06 06:42:06 PM PDT 24 2710396253 ps
T375 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1471540167 Aug 06 06:40:45 PM PDT 24 Aug 06 06:41:16 PM PDT 24 50618754282 ps
T468 /workspace/coverage/default/16.sysrst_ctrl_smoke.2261127185 Aug 06 06:39:46 PM PDT 24 Aug 06 06:39:47 PM PDT 24 2145756960 ps
T469 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3987880313 Aug 06 06:41:41 PM PDT 24 Aug 06 06:41:44 PM PDT 24 2264735872 ps
T366 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3297830802 Aug 06 06:39:05 PM PDT 24 Aug 06 06:41:33 PM PDT 24 61579102830 ps
T470 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1460300561 Aug 06 06:42:37 PM PDT 24 Aug 06 06:42:39 PM PDT 24 2637281231 ps
T471 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3865685501 Aug 06 06:40:25 PM PDT 24 Aug 06 06:40:28 PM PDT 24 2244749739 ps
T472 /workspace/coverage/default/12.sysrst_ctrl_smoke.2486407780 Aug 06 06:39:05 PM PDT 24 Aug 06 06:39:09 PM PDT 24 2120235301 ps
T473 /workspace/coverage/default/9.sysrst_ctrl_smoke.2642494690 Aug 06 06:39:46 PM PDT 24 Aug 06 06:39:48 PM PDT 24 2137116900 ps
T474 /workspace/coverage/default/38.sysrst_ctrl_smoke.1794841387 Aug 06 06:41:37 PM PDT 24 Aug 06 06:41:42 PM PDT 24 2110901582 ps
T475 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.716110956 Aug 06 06:40:43 PM PDT 24 Aug 06 06:40:46 PM PDT 24 3100510067 ps
T263 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3723442007 Aug 06 06:42:33 PM PDT 24 Aug 06 06:43:15 PM PDT 24 60124512395 ps
T476 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1212700997 Aug 06 06:40:27 PM PDT 24 Aug 06 06:40:29 PM PDT 24 2628684884 ps
T477 /workspace/coverage/default/25.sysrst_ctrl_smoke.1746902711 Aug 06 06:40:36 PM PDT 24 Aug 06 06:40:38 PM PDT 24 2148715303 ps
T478 /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.649082046 Aug 06 06:42:06 PM PDT 24 Aug 06 06:54:14 PM PDT 24 309265682148 ps
T374 /workspace/coverage/default/10.sysrst_ctrl_stress_all.3282848040 Aug 06 06:39:02 PM PDT 24 Aug 06 06:45:14 PM PDT 24 155929057078 ps
T479 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2451241943 Aug 06 06:41:01 PM PDT 24 Aug 06 06:41:07 PM PDT 24 2510604785 ps
T480 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2191536112 Aug 06 06:39:22 PM PDT 24 Aug 06 06:39:26 PM PDT 24 2519208101 ps
T481 /workspace/coverage/default/49.sysrst_ctrl_alert_test.218981587 Aug 06 06:42:39 PM PDT 24 Aug 06 06:42:40 PM PDT 24 2052202050 ps
T349 /workspace/coverage/default/36.sysrst_ctrl_combo_detect.2231420818 Aug 06 06:41:25 PM PDT 24 Aug 06 06:42:21 PM PDT 24 135064803502 ps
T84 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.3136725657 Aug 06 06:42:38 PM PDT 24 Aug 06 06:42:41 PM PDT 24 5034057862 ps
T199 /workspace/coverage/default/15.sysrst_ctrl_smoke.3251495757 Aug 06 06:39:48 PM PDT 24 Aug 06 06:39:50 PM PDT 24 2133815657 ps
T200 /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2600415490 Aug 06 06:42:06 PM PDT 24 Aug 06 06:42:13 PM PDT 24 2614172669 ps
T201 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4101811780 Aug 06 06:42:37 PM PDT 24 Aug 06 06:43:13 PM PDT 24 26838048797 ps
T202 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2373875673 Aug 06 06:41:29 PM PDT 24 Aug 06 06:41:38 PM PDT 24 3362260699 ps
T203 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1010138068 Aug 06 06:39:03 PM PDT 24 Aug 06 06:39:06 PM PDT 24 8984354699 ps
T204 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2676973771 Aug 06 06:39:49 PM PDT 24 Aug 06 06:39:52 PM PDT 24 2543559384 ps
T205 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.4016355211 Aug 06 06:41:41 PM PDT 24 Aug 06 06:41:44 PM PDT 24 2635182865 ps
T206 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3177649980 Aug 06 06:39:48 PM PDT 24 Aug 06 06:39:54 PM PDT 24 2103270228 ps
T207 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2992609879 Aug 06 06:42:52 PM PDT 24 Aug 06 06:45:41 PM PDT 24 67076231633 ps
T482 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1316703306 Aug 06 06:42:38 PM PDT 24 Aug 06 06:42:40 PM PDT 24 4827227791 ps
T483 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1941822284 Aug 06 06:41:25 PM PDT 24 Aug 06 06:41:29 PM PDT 24 2475125347 ps
T484 /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3837222333 Aug 06 06:39:21 PM PDT 24 Aug 06 06:39:42 PM PDT 24 31132086611 ps
T387 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3396381144 Aug 06 06:41:38 PM PDT 24 Aug 06 06:43:02 PM PDT 24 34254317619 ps
T112 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1835496692 Aug 06 06:39:00 PM PDT 24 Aug 06 06:39:03 PM PDT 24 3488406637 ps
T485 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3136009160 Aug 06 06:42:32 PM PDT 24 Aug 06 06:45:13 PM PDT 24 63047634074 ps
T486 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.4207762680 Aug 06 06:41:37 PM PDT 24 Aug 06 06:41:45 PM PDT 24 3070350090 ps
T487 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3993796982 Aug 06 06:38:41 PM PDT 24 Aug 06 06:38:43 PM PDT 24 2551102821 ps
T488 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1621226251 Aug 06 06:39:51 PM PDT 24 Aug 06 06:39:59 PM PDT 24 2612177860 ps
T489 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2495524851 Aug 06 06:41:25 PM PDT 24 Aug 06 06:41:29 PM PDT 24 11553180650 ps
T490 /workspace/coverage/default/42.sysrst_ctrl_alert_test.30905677 Aug 06 06:42:07 PM PDT 24 Aug 06 06:42:09 PM PDT 24 2040738721 ps
T208 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.429320856 Aug 06 06:41:24 PM PDT 24 Aug 06 06:42:41 PM PDT 24 31812493074 ps
T194 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.3738599989 Aug 06 06:39:27 PM PDT 24 Aug 06 06:39:30 PM PDT 24 3269254893 ps
T491 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.245354812 Aug 06 06:42:32 PM PDT 24 Aug 06 06:42:39 PM PDT 24 2799232664 ps
T304 /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.188958150 Aug 06 06:38:57 PM PDT 24 Aug 06 06:39:03 PM PDT 24 2513304906 ps
T268 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.54126655 Aug 06 06:39:27 PM PDT 24 Aug 06 06:40:12 PM PDT 24 66988341532 ps
T492 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1038180368 Aug 06 06:41:00 PM PDT 24 Aug 06 06:41:07 PM PDT 24 2511819434 ps
T493 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3141718426 Aug 06 06:41:29 PM PDT 24 Aug 06 06:41:35 PM PDT 24 2610601862 ps
T364 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1006739003 Aug 06 06:40:14 PM PDT 24 Aug 06 06:41:44 PM PDT 24 40267780416 ps
T494 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.4206121153 Aug 06 06:40:43 PM PDT 24 Aug 06 06:40:45 PM PDT 24 2521799601 ps
T305 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2315196374 Aug 06 06:41:43 PM PDT 24 Aug 06 06:41:51 PM PDT 24 2513483471 ps
T495 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1651264139 Aug 06 06:40:45 PM PDT 24 Aug 06 06:40:48 PM PDT 24 2257328116 ps
T496 /workspace/coverage/default/20.sysrst_ctrl_alert_test.244601260 Aug 06 06:40:16 PM PDT 24 Aug 06 06:40:18 PM PDT 24 2122671094 ps
T497 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.843852283 Aug 06 06:41:25 PM PDT 24 Aug 06 06:41:28 PM PDT 24 2475848974 ps
T196 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.487728926 Aug 06 06:40:27 PM PDT 24 Aug 06 06:41:45 PM PDT 24 138644451773 ps
T498 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2114955295 Aug 06 06:41:21 PM PDT 24 Aug 06 06:41:23 PM PDT 24 3816371286 ps
T295 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2528155360 Aug 06 06:38:58 PM PDT 24 Aug 06 06:39:29 PM PDT 24 28481864050 ps
T499 /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1288908202 Aug 06 06:40:14 PM PDT 24 Aug 06 06:40:16 PM PDT 24 2628865162 ps
T500 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1477715623 Aug 06 06:38:39 PM PDT 24 Aug 06 06:38:47 PM PDT 24 2507649287 ps
T501 /workspace/coverage/default/30.sysrst_ctrl_alert_test.2031054684 Aug 06 06:41:05 PM PDT 24 Aug 06 06:41:10 PM PDT 24 2010021833 ps
T502 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.738504322 Aug 06 06:39:23 PM PDT 24 Aug 06 06:39:38 PM PDT 24 5468664803 ps
T503 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.309575323 Aug 06 06:38:42 PM PDT 24 Aug 06 06:38:44 PM PDT 24 3219843767 ps
T504 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2316201888 Aug 06 06:42:36 PM PDT 24 Aug 06 06:42:41 PM PDT 24 3529126709 ps
T505 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2760255798 Aug 06 06:41:06 PM PDT 24 Aug 06 06:41:15 PM PDT 24 3478678741 ps
T506 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.937706415 Aug 06 06:42:06 PM PDT 24 Aug 06 06:42:08 PM PDT 24 2134245206 ps
T507 /workspace/coverage/default/24.sysrst_ctrl_stress_all.3223332330 Aug 06 06:40:25 PM PDT 24 Aug 06 06:40:29 PM PDT 24 15025929666 ps
T508 /workspace/coverage/default/24.sysrst_ctrl_smoke.2059095988 Aug 06 06:40:33 PM PDT 24 Aug 06 06:40:39 PM PDT 24 2108960704 ps
T509 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2473992458 Aug 06 06:41:25 PM PDT 24 Aug 06 06:41:31 PM PDT 24 3263889727 ps
T510 /workspace/coverage/default/16.sysrst_ctrl_stress_all.3925801901 Aug 06 06:40:20 PM PDT 24 Aug 06 06:40:24 PM PDT 24 9901337680 ps
T371 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3758123463 Aug 06 06:42:52 PM PDT 24 Aug 06 06:45:58 PM PDT 24 70739918306 ps
T383 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4146445980 Aug 06 06:42:51 PM PDT 24 Aug 06 06:43:03 PM PDT 24 39544506807 ps
T511 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.255212958 Aug 06 06:39:25 PM PDT 24 Aug 06 06:39:31 PM PDT 24 2914481724 ps
T512 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1197793576 Aug 06 06:38:41 PM PDT 24 Aug 06 06:38:57 PM PDT 24 21127689717 ps
T513 /workspace/coverage/default/13.sysrst_ctrl_stress_all.1062312499 Aug 06 06:39:45 PM PDT 24 Aug 06 06:39:52 PM PDT 24 9298925278 ps
T514 /workspace/coverage/default/23.sysrst_ctrl_stress_all.3904899443 Aug 06 06:40:16 PM PDT 24 Aug 06 06:40:27 PM PDT 24 17360502047 ps
T360 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2669272223 Aug 06 06:42:49 PM PDT 24 Aug 06 06:45:38 PM PDT 24 66949893138 ps
T515 /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3640480181 Aug 06 06:42:08 PM PDT 24 Aug 06 06:42:13 PM PDT 24 2467852665 ps
T516 /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.335386251 Aug 06 06:38:44 PM PDT 24 Aug 06 06:38:47 PM PDT 24 2131123074 ps
T517 /workspace/coverage/default/37.sysrst_ctrl_smoke.1818584481 Aug 06 06:41:24 PM PDT 24 Aug 06 06:41:26 PM PDT 24 2122270902 ps
T354 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.973565624 Aug 06 06:42:51 PM PDT 24 Aug 06 06:43:31 PM PDT 24 58821719913 ps
T518 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1828551376 Aug 06 06:38:17 PM PDT 24 Aug 06 06:38:19 PM PDT 24 3147921726 ps
T348 /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1722863541 Aug 06 06:42:08 PM PDT 24 Aug 06 06:43:34 PM PDT 24 71823811075 ps
T519 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.735323981 Aug 06 06:42:34 PM PDT 24 Aug 06 06:42:36 PM PDT 24 2637792573 ps
T520 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.658189628 Aug 06 06:40:48 PM PDT 24 Aug 06 06:40:51 PM PDT 24 3685581454 ps
T521 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2631917289 Aug 06 06:38:40 PM PDT 24 Aug 06 06:38:44 PM PDT 24 2234652320 ps
T309 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.36835433 Aug 06 06:40:48 PM PDT 24 Aug 06 06:41:51 PM PDT 24 50279154462 ps
T169 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3951674995 Aug 06 06:38:40 PM PDT 24 Aug 06 06:38:45 PM PDT 24 5720274890 ps
T522 /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3134678801 Aug 06 06:39:49 PM PDT 24 Aug 06 06:39:55 PM PDT 24 2215704590 ps
T523 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.712558558 Aug 06 06:38:40 PM PDT 24 Aug 06 06:38:50 PM PDT 24 5062141940 ps
T524 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1874117077 Aug 06 06:41:00 PM PDT 24 Aug 06 06:41:02 PM PDT 24 2461410233 ps
T525 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2603632152 Aug 06 06:39:02 PM PDT 24 Aug 06 06:39:07 PM PDT 24 2472035250 ps
T93 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.2206022752 Aug 06 06:40:44 PM PDT 24 Aug 06 06:41:49 PM PDT 24 100910080328 ps
T94 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.1368348786 Aug 06 06:40:46 PM PDT 24 Aug 06 06:41:00 PM PDT 24 44042841414 ps
T526 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3716607765 Aug 06 06:39:00 PM PDT 24 Aug 06 06:39:02 PM PDT 24 3918388369 ps
T527 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1703718061 Aug 06 06:40:17 PM PDT 24 Aug 06 06:40:19 PM PDT 24 3169373266 ps
T528 /workspace/coverage/default/1.sysrst_ctrl_alert_test.4114899606 Aug 06 06:38:17 PM PDT 24 Aug 06 06:38:19 PM PDT 24 2028818276 ps
T170 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2986206853 Aug 06 06:39:06 PM PDT 24 Aug 06 06:39:40 PM PDT 24 71398103210 ps
T386 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.982968194 Aug 06 06:41:03 PM PDT 24 Aug 06 06:44:02 PM PDT 24 72748939411 ps
T529 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2310156149 Aug 06 06:38:42 PM PDT 24 Aug 06 06:38:45 PM PDT 24 2486823665 ps
T185 /workspace/coverage/default/25.sysrst_ctrl_stress_all.4010522740 Aug 06 06:40:33 PM PDT 24 Aug 06 06:40:51 PM PDT 24 13339385423 ps
T530 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1955904747 Aug 06 06:42:04 PM PDT 24 Aug 06 06:42:11 PM PDT 24 2469819780 ps
T531 /workspace/coverage/default/45.sysrst_ctrl_alert_test.2424346329 Aug 06 06:42:32 PM PDT 24 Aug 06 06:42:38 PM PDT 24 2013674122 ps
T361 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1682858063 Aug 06 06:42:50 PM PDT 24 Aug 06 06:44:26 PM PDT 24 147069955997 ps
T532 /workspace/coverage/default/41.sysrst_ctrl_alert_test.3255456305 Aug 06 06:42:07 PM PDT 24 Aug 06 06:42:09 PM PDT 24 2063489868 ps
T275 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.836401192 Aug 06 06:38:16 PM PDT 24 Aug 06 06:39:12 PM PDT 24 22012106462 ps
T533 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1001738402 Aug 06 06:42:39 PM PDT 24 Aug 06 06:42:41 PM PDT 24 2885042490 ps
T306 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1759308763 Aug 06 06:38:39 PM PDT 24 Aug 06 06:38:41 PM PDT 24 4502401677 ps
T534 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.94260057 Aug 06 06:42:48 PM PDT 24 Aug 06 06:43:24 PM PDT 24 26836218688 ps
T311 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3471318954 Aug 06 06:40:17 PM PDT 24 Aug 06 06:41:15 PM PDT 24 40627785992 ps
T535 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3122360689 Aug 06 06:39:00 PM PDT 24 Aug 06 06:39:02 PM PDT 24 2626715304 ps
T197 /workspace/coverage/default/38.sysrst_ctrl_stress_all.630879961 Aug 06 06:41:40 PM PDT 24 Aug 06 06:47:31 PM PDT 24 1359831924116 ps
T536 /workspace/coverage/default/37.sysrst_ctrl_alert_test.688822287 Aug 06 06:41:39 PM PDT 24 Aug 06 06:41:45 PM PDT 24 2015743042 ps
T95 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2482678730 Aug 06 06:41:25 PM PDT 24 Aug 06 06:41:57 PM PDT 24 162614817398 ps
T218 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.135425712 Aug 06 06:41:37 PM PDT 24 Aug 06 06:45:57 PM PDT 24 95503200817 ps
T219 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.133327535 Aug 06 06:42:51 PM PDT 24 Aug 06 06:45:42 PM PDT 24 77054242179 ps
T220 /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.834993190 Aug 06 06:40:54 PM PDT 24 Aug 06 06:40:56 PM PDT 24 2535015702 ps
T221 /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1313373335 Aug 06 06:38:42 PM PDT 24 Aug 06 06:38:44 PM PDT 24 2526749454 ps
T222 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1643465563 Aug 06 06:41:02 PM PDT 24 Aug 06 06:41:09 PM PDT 24 2608499263 ps
T223 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1632951435 Aug 06 06:39:29 PM PDT 24 Aug 06 06:39:31 PM PDT 24 3163340265 ps
T224 /workspace/coverage/default/47.sysrst_ctrl_stress_all.2047778582 Aug 06 06:42:36 PM PDT 24 Aug 06 06:43:03 PM PDT 24 9885408181 ps
T225 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.852064705 Aug 06 06:42:36 PM PDT 24 Aug 06 06:42:39 PM PDT 24 2478434340 ps
T226 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.454917202 Aug 06 06:41:29 PM PDT 24 Aug 06 06:41:44 PM PDT 24 591174578676 ps
T369 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1519704949 Aug 06 06:42:39 PM PDT 24 Aug 06 06:46:16 PM PDT 24 167234483967 ps
T537 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.847042838 Aug 06 06:41:04 PM PDT 24 Aug 06 06:41:07 PM PDT 24 2622180257 ps
T362 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2631834671 Aug 06 06:42:09 PM PDT 24 Aug 06 06:45:21 PM PDT 24 75040687243 ps
T538 /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.932292499 Aug 06 06:41:30 PM PDT 24 Aug 06 06:41:32 PM PDT 24 2638500518 ps
T135 /workspace/coverage/default/39.sysrst_ctrl_stress_all.1130462747 Aug 06 06:41:45 PM PDT 24 Aug 06 06:41:50 PM PDT 24 9054619518 ps
T539 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3343739870 Aug 06 06:42:52 PM PDT 24 Aug 06 06:45:24 PM PDT 24 62232430784 ps
T540 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.2755561024 Aug 06 06:39:01 PM PDT 24 Aug 06 06:39:04 PM PDT 24 2455288812 ps
T541 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.807173051 Aug 06 06:38:02 PM PDT 24 Aug 06 06:38:03 PM PDT 24 2652072476 ps
T542 /workspace/coverage/default/41.sysrst_ctrl_stress_all.2288707055 Aug 06 06:42:07 PM PDT 24 Aug 06 06:42:12 PM PDT 24 6214508308 ps
T543 /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3055134522 Aug 06 06:38:42 PM PDT 24 Aug 06 06:38:43 PM PDT 24 2648541373 ps
T544 /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3203948420 Aug 06 06:42:32 PM PDT 24 Aug 06 06:42:34 PM PDT 24 4550091828 ps
T545 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.575519649 Aug 06 06:41:23 PM PDT 24 Aug 06 06:41:25 PM PDT 24 2872307231 ps
T546 /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3138145858 Aug 06 06:38:40 PM PDT 24 Aug 06 06:38:42 PM PDT 24 2132366212 ps
T547 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4067832119 Aug 06 06:41:41 PM PDT 24 Aug 06 06:41:49 PM PDT 24 3035788564 ps
T548 /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.154371000 Aug 06 06:41:00 PM PDT 24 Aug 06 06:41:02 PM PDT 24 2474897948 ps
T549 /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3741729692 Aug 06 06:39:00 PM PDT 24 Aug 06 06:39:04 PM PDT 24 2688793185 ps
T550 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2657229476 Aug 06 06:39:51 PM PDT 24 Aug 06 06:39:58 PM PDT 24 2120647152 ps
T270 /workspace/coverage/default/6.sysrst_ctrl_combo_detect.298776523 Aug 06 06:39:13 PM PDT 24 Aug 06 06:43:55 PM PDT 24 114690211618 ps
T551 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1523509168 Aug 06 06:39:54 PM PDT 24 Aug 06 06:40:04 PM PDT 24 3923374370 ps
T552 /workspace/coverage/default/20.sysrst_ctrl_smoke.1358494034 Aug 06 06:40:22 PM PDT 24 Aug 06 06:40:25 PM PDT 24 2115701575 ps
T553 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.32806405 Aug 06 06:40:45 PM PDT 24 Aug 06 06:40:52 PM PDT 24 2607923378 ps
T554 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4073607532 Aug 06 06:38:42 PM PDT 24 Aug 06 06:38:47 PM PDT 24 4238004538 ps
T555 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3349241368 Aug 06 06:40:25 PM PDT 24 Aug 06 06:40:29 PM PDT 24 2517918785 ps
T388 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3325389767 Aug 06 06:40:20 PM PDT 24 Aug 06 06:40:33 PM PDT 24 100886978320 ps
T353 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1092437884 Aug 06 06:42:56 PM PDT 24 Aug 06 06:43:40 PM PDT 24 62062538447 ps
T556 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3846444992 Aug 06 06:38:16 PM PDT 24 Aug 06 06:38:24 PM PDT 24 2462957006 ps
T557 /workspace/coverage/default/22.sysrst_ctrl_stress_all.3045416289 Aug 06 06:40:21 PM PDT 24 Aug 06 06:40:28 PM PDT 24 9165194400 ps
T558 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3183674764 Aug 06 06:39:03 PM PDT 24 Aug 06 06:39:08 PM PDT 24 3300482058 ps
T559 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1193871341 Aug 06 06:42:32 PM PDT 24 Aug 06 06:42:33 PM PDT 24 2600760310 ps
T560 /workspace/coverage/default/16.sysrst_ctrl_alert_test.2687998161 Aug 06 06:39:51 PM PDT 24 Aug 06 06:39:57 PM PDT 24 2013094472 ps
T561 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1507850418 Aug 06 06:41:23 PM PDT 24 Aug 06 06:41:30 PM PDT 24 2512464160 ps
T562 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.1296178524 Aug 06 06:40:29 PM PDT 24 Aug 06 06:40:33 PM PDT 24 2232440019 ps
T154 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.20484684 Aug 06 06:41:27 PM PDT 24 Aug 06 06:41:30 PM PDT 24 4163461044 ps
T160 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.975289971 Aug 06 06:40:21 PM PDT 24 Aug 06 06:40:26 PM PDT 24 2993053252 ps
T161 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.235310897 Aug 06 06:38:15 PM PDT 24 Aug 06 06:39:53 PM PDT 24 82729486437 ps
T162 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2028270502 Aug 06 06:42:49 PM PDT 24 Aug 06 06:43:05 PM PDT 24 55063827026 ps
T81 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2291946985 Aug 06 06:42:50 PM PDT 24 Aug 06 06:46:27 PM PDT 24 90273742432 ps
T149 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.3341108821 Aug 06 06:38:17 PM PDT 24 Aug 06 06:38:25 PM PDT 24 3809751802 ps
T163 /workspace/coverage/default/13.sysrst_ctrl_alert_test.2615884000 Aug 06 06:39:29 PM PDT 24 Aug 06 06:39:31 PM PDT 24 2097667488 ps
T164 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3856587 Aug 06 06:38:41 PM PDT 24 Aug 06 06:42:15 PM PDT 24 86527198895 ps
T165 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3307245291 Aug 06 06:39:04 PM PDT 24 Aug 06 06:39:07 PM PDT 24 4443584084 ps
T166 /workspace/coverage/default/11.sysrst_ctrl_stress_all.3024223826 Aug 06 06:39:05 PM PDT 24 Aug 06 06:39:14 PM PDT 24 12136322647 ps
T307 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1246968811 Aug 06 06:40:13 PM PDT 24 Aug 06 06:40:21 PM PDT 24 5717282170 ps
T563 /workspace/coverage/default/3.sysrst_ctrl_alert_test.4251696770 Aug 06 06:38:43 PM PDT 24 Aug 06 06:38:49 PM PDT 24 2014277229 ps
T564 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2306713323 Aug 06 06:40:51 PM PDT 24 Aug 06 06:40:55 PM PDT 24 3147080710 ps
T565 /workspace/coverage/default/32.sysrst_ctrl_alert_test.3669189184 Aug 06 06:41:23 PM PDT 24 Aug 06 06:41:24 PM PDT 24 2032548006 ps
T150 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.860914616 Aug 06 06:41:41 PM PDT 24 Aug 06 06:41:44 PM PDT 24 4549959218 ps
T566 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.4154321122 Aug 06 06:40:16 PM PDT 24 Aug 06 06:40:17 PM PDT 24 2591259996 ps
T567 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3741943151 Aug 06 06:38:41 PM PDT 24 Aug 06 06:38:43 PM PDT 24 4796468229 ps
T568 /workspace/coverage/default/25.sysrst_ctrl_alert_test.918203183 Aug 06 06:40:35 PM PDT 24 Aug 06 06:40:41 PM PDT 24 2014667849 ps
T151 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2623971336 Aug 06 06:42:37 PM PDT 24 Aug 06 06:42:43 PM PDT 24 4836391329 ps
T569 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.637198196 Aug 06 06:42:33 PM PDT 24 Aug 06 06:42:36 PM PDT 24 2633383145 ps
T367 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2982557538 Aug 06 06:42:10 PM PDT 24 Aug 06 06:45:08 PM PDT 24 146754305479 ps
T570 /workspace/coverage/default/46.sysrst_ctrl_alert_test.763534602 Aug 06 06:42:34 PM PDT 24 Aug 06 06:42:40 PM PDT 24 2010297390 ps
T571 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3298949415 Aug 06 06:39:43 PM PDT 24 Aug 06 06:40:23 PM PDT 24 60312230449 ps
T82 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2168838365 Aug 06 06:38:42 PM PDT 24 Aug 06 06:39:27 PM PDT 24 93584366410 ps
T152 /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1977270716 Aug 06 06:42:07 PM PDT 24 Aug 06 06:42:09 PM PDT 24 3727576709 ps
T572 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3110825414 Aug 06 06:40:27 PM PDT 24 Aug 06 06:40:36 PM PDT 24 2458279324 ps
T573 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1426261407 Aug 06 06:39:42 PM PDT 24 Aug 06 06:39:46 PM PDT 24 3287950733 ps
T574 /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3141641344 Aug 06 06:40:31 PM PDT 24 Aug 06 06:40:38 PM PDT 24 2610006085 ps
T86 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.16710474 Aug 06 06:41:45 PM PDT 24 Aug 06 06:43:10 PM PDT 24 1486167764625 ps
T575 /workspace/coverage/default/14.sysrst_ctrl_alert_test.333994168 Aug 06 06:39:51 PM PDT 24 Aug 06 06:39:52 PM PDT 24 2072115242 ps
T576 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.808541567 Aug 06 06:42:37 PM PDT 24 Aug 06 06:42:41 PM PDT 24 4837919702 ps
T577 /workspace/coverage/default/40.sysrst_ctrl_stress_all.2663356242 Aug 06 06:41:42 PM PDT 24 Aug 06 06:42:17 PM PDT 24 16852459976 ps
T370 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2034283577 Aug 06 06:42:53 PM PDT 24 Aug 06 06:43:23 PM PDT 24 45717520175 ps
T578 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1011466333 Aug 06 06:39:51 PM PDT 24 Aug 06 06:39:53 PM PDT 24 2563140658 ps
T579 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2808194385 Aug 06 06:41:40 PM PDT 24 Aug 06 06:41:42 PM PDT 24 2627516199 ps
T355 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1516914354 Aug 06 06:42:52 PM PDT 24 Aug 06 06:43:35 PM PDT 24 34250933926 ps
T580 /workspace/coverage/default/21.sysrst_ctrl_alert_test.1278285633 Aug 06 06:40:18 PM PDT 24 Aug 06 06:40:19 PM PDT 24 2173014300 ps
T581 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1440348033 Aug 06 06:41:23 PM PDT 24 Aug 06 06:41:26 PM PDT 24 3588630633 ps
T376 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3318723711 Aug 06 06:39:03 PM PDT 24 Aug 06 06:40:28 PM PDT 24 130328750537 ps
T582 /workspace/coverage/default/15.sysrst_ctrl_alert_test.395249465 Aug 06 06:39:49 PM PDT 24 Aug 06 06:39:50 PM PDT 24 2054538157 ps
T113 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.67910421 Aug 06 06:41:29 PM PDT 24 Aug 06 06:43:57 PM PDT 24 76060119774 ps
T122 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3458585948 Aug 06 06:39:02 PM PDT 24 Aug 06 06:42:02 PM PDT 24 79356577725 ps
T209 /workspace/coverage/default/42.sysrst_ctrl_smoke.1032231863 Aug 06 06:42:06 PM PDT 24 Aug 06 06:42:10 PM PDT 24 2119127379 ps
T210 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3409716792 Aug 06 06:42:53 PM PDT 24 Aug 06 06:44:02 PM PDT 24 28580990104 ps
T211 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4045985657 Aug 06 06:40:46 PM PDT 24 Aug 06 06:40:50 PM PDT 24 4495405412 ps
T212 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3876588936 Aug 06 06:39:01 PM PDT 24 Aug 06 06:39:07 PM PDT 24 2103409160 ps
T182 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2055477803 Aug 06 06:40:34 PM PDT 24 Aug 06 06:40:36 PM PDT 24 4705403774 ps
T213 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3560951346 Aug 06 06:39:00 PM PDT 24 Aug 06 06:40:01 PM PDT 24 95163524227 ps
T214 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.88146391 Aug 06 06:39:00 PM PDT 24 Aug 06 06:39:11 PM PDT 24 5059403131 ps
T215 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3395967617 Aug 06 06:40:48 PM PDT 24 Aug 06 06:41:07 PM PDT 24 61459929096 ps
T216 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1096512748 Aug 06 06:39:46 PM PDT 24 Aug 06 06:41:19 PM PDT 24 35587097499 ps
T583 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1031640788 Aug 06 06:38:43 PM PDT 24 Aug 06 06:38:44 PM PDT 24 2086047157 ps
T584 /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3985295986 Aug 06 06:39:12 PM PDT 24 Aug 06 06:39:16 PM PDT 24 7689353815 ps
T585 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2978489241 Aug 06 06:42:34 PM PDT 24 Aug 06 06:42:36 PM PDT 24 2477564927 ps
T195 /workspace/coverage/default/42.sysrst_ctrl_stress_all.707879269 Aug 06 06:42:08 PM PDT 24 Aug 06 06:42:41 PM PDT 24 11889250272 ps
T586 /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2453164234 Aug 06 06:39:43 PM PDT 24 Aug 06 06:39:45 PM PDT 24 2678459532 ps
T183 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.4222769568 Aug 06 06:40:22 PM PDT 24 Aug 06 06:40:31 PM PDT 24 4668961555 ps
T587 /workspace/coverage/default/26.sysrst_ctrl_stress_all.2713370300 Aug 06 06:40:43 PM PDT 24 Aug 06 06:40:48 PM PDT 24 12076919531 ps
T588 /workspace/coverage/default/29.sysrst_ctrl_smoke.3219562642 Aug 06 06:40:46 PM PDT 24 Aug 06 06:40:48 PM PDT 24 2130782915 ps
T589 /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2890757785 Aug 06 06:40:17 PM PDT 24 Aug 06 06:40:20 PM PDT 24 2466098188 ps
T381 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1867520344 Aug 06 06:38:43 PM PDT 24 Aug 06 06:39:14 PM PDT 24 45557283547 ps
T352 /workspace/coverage/default/21.sysrst_ctrl_stress_all.2683968017 Aug 06 06:40:21 PM PDT 24 Aug 06 06:44:28 PM PDT 24 103395560030 ps
T96 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3401091271 Aug 06 06:39:51 PM PDT 24 Aug 06 06:40:23 PM PDT 24 82826978248 ps
T590 /workspace/coverage/default/27.sysrst_ctrl_smoke.1213263750 Aug 06 06:40:44 PM PDT 24 Aug 06 06:40:50 PM PDT 24 2111526519 ps
T591 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1199380488 Aug 06 06:39:05 PM PDT 24 Aug 06 06:41:14 PM PDT 24 119048600802 ps
T592 /workspace/coverage/default/44.sysrst_ctrl_stress_all.1349723637 Aug 06 06:42:32 PM PDT 24 Aug 06 06:42:34 PM PDT 24 6470705012 ps
T593 /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2609350541 Aug 06 06:38:46 PM PDT 24 Aug 06 06:38:52 PM PDT 24 2179028340 ps
T594 /workspace/coverage/default/45.sysrst_ctrl_smoke.1021781370 Aug 06 06:42:30 PM PDT 24 Aug 06 06:42:31 PM PDT 24 2196956379 ps
T595 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2271901302 Aug 06 06:41:38 PM PDT 24 Aug 06 06:41:42 PM PDT 24 2518720870 ps
T266 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2915783644 Aug 06 06:42:49 PM PDT 24 Aug 06 06:44:31 PM PDT 24 76849750184 ps
T596 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1555496456 Aug 06 06:41:25 PM PDT 24 Aug 06 06:41:31 PM PDT 24 2513482472 ps
T357 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2019344524 Aug 06 06:39:52 PM PDT 24 Aug 06 06:44:51 PM PDT 24 118565574251 ps
T597 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2439899656 Aug 06 06:41:21 PM PDT 24 Aug 06 06:41:24 PM PDT 24 2499392711 ps
T598 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3895616731 Aug 06 06:39:52 PM PDT 24 Aug 06 06:40:01 PM PDT 24 3492177840 ps
T599 /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3935140912 Aug 06 06:40:47 PM PDT 24 Aug 06 06:45:04 PM PDT 24 2423597441796 ps
T600 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1249673711 Aug 06 06:39:01 PM PDT 24 Aug 06 06:39:07 PM PDT 24 2512998302 ps
T601 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.877873158 Aug 06 06:42:06 PM PDT 24 Aug 06 06:42:09 PM PDT 24 3281709875 ps
T97 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2252581259 Aug 06 06:42:34 PM PDT 24 Aug 06 06:42:52 PM PDT 24 33845921889 ps
T602 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.1227225037 Aug 06 06:39:52 PM PDT 24 Aug 06 06:40:34 PM PDT 24 122724643083 ps
T603 /workspace/coverage/default/32.sysrst_ctrl_smoke.2560036711 Aug 06 06:41:01 PM PDT 24 Aug 06 06:41:03 PM PDT 24 2135489914 ps
T604 /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2193310405 Aug 06 06:39:05 PM PDT 24 Aug 06 06:39:09 PM PDT 24 2516364038 ps
T153 /workspace/coverage/default/14.sysrst_ctrl_stress_all.339558841 Aug 06 06:39:29 PM PDT 24 Aug 06 06:39:45 PM PDT 24 11968165610 ps
T605 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2824467432 Aug 06 06:39:01 PM PDT 24 Aug 06 06:39:28 PM PDT 24 94001688970 ps
T606 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.522134283 Aug 06 06:39:44 PM PDT 24 Aug 06 06:39:46 PM PDT 24 2221562877 ps
T123 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1072574593 Aug 06 06:40:43 PM PDT 24 Aug 06 06:43:06 PM PDT 24 64118580200 ps
T607 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.2247367097 Aug 06 06:39:05 PM PDT 24 Aug 06 06:39:09 PM PDT 24 4069086979 ps
T608 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2424197976 Aug 06 06:39:01 PM PDT 24 Aug 06 06:39:03 PM PDT 24 2530845295 ps
T609 /workspace/coverage/default/19.sysrst_ctrl_alert_test.2129556088 Aug 06 06:40:17 PM PDT 24 Aug 06 06:40:19 PM PDT 24 2042272588 ps
T358 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1874991057 Aug 06 06:41:39 PM PDT 24 Aug 06 06:42:26 PM PDT 24 206968389276 ps
T610 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1338066303 Aug 06 06:41:24 PM PDT 24 Aug 06 06:41:30 PM PDT 24 2034919457 ps
T611 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2667535303 Aug 06 06:41:04 PM PDT 24 Aug 06 06:41:34 PM PDT 24 43611414082 ps
T612 /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3533808828 Aug 06 06:38:42 PM PDT 24 Aug 06 06:38:43 PM PDT 24 2657858355 ps
T290 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3346368085 Aug 06 06:38:39 PM PDT 24 Aug 06 06:40:23 PM PDT 24 42009533809 ps
T613 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.939952852 Aug 06 06:39:00 PM PDT 24 Aug 06 06:39:10 PM PDT 24 3616695887 ps
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