SYSRST_CTRL Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.390s	2.108ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.490s	2.458ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.110s	2.182ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.690s	2.333ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.140s	4.031ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.610s	2.053ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	4.536m	76.815ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.560s	2.326ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.680s	2.085ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.610s	2.053ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.560s	2.326ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	7.982m	177.702ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	7.202m	176.344ms	88	100	88.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	12.135m	309.266ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	11.190s	5.067ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.550s	2.513ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.600s	2.140ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	56.300s	219.730ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.590s	2.611ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	6.246m	1.508s	42	50	84.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.616m	38.057ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	7.904m	908.522ms	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	6.030s	2.014ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.100s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.210s	2.181ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.210s	2.181ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.140s	4.031ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.610s	2.053ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.560s	2.326ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	34.550s	8.904ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.140s	4.031ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.610s	2.053ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.560s	2.326ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	34.550s	8.904ms	20	20	100.00
V2		TOTAL			670	692	96.82
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.742m	42.010ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.853m	42.397ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.853m	42.397ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.954m	123.800ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			908	932	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.68	98.90	96.76	100.00	97.44	98.37	99.71	92.55

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 10 failures:

Test sysrst_ctrl_ultra_low_pwr has 8 failures.

4.sysrst_ctrl_ultra_low_pwr.46111794411618132602438206033563944299476252351542906351189977519271032232153
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 3188662224 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 3241162224 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 5121162224 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 5132791438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.sysrst_ctrl_ultra_low_pwr.45920485710067408945723222582280950206010214648619044818341710587977518646635
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 972491093944 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 1171573593944 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 1942218593944 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 1942257853815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

19.sysrst_ctrl_stress_all_with_rand_reset.16756857610196166511867606793174484672643129797092487017025086566876800301400
Line 577, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4929773345 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 4992273345 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 6582273345 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 6589105979 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ultra_low_pwr_vseq
  UVM_INFO @ 8587285979 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:106) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Starting the body from ultra_low_pwr_vseq

37.sysrst_ctrl_stress_all_with_rand_reset.79993574916813130695255775455561295579864163276287636187050150707614994636046
Line 648, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 96359193006 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 227951693006 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 756591693006 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 756605083010 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_access_vseq
  UVM_INFO @ 758601720098 ps: (sysrst_ctrl_pin_access_vseq.sv:17) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Starting the body from pin_access_vseq

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 5 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 5 failures.

29.sysrst_ctrl_combo_detect_with_pre_cond.13283979146845013219269851681521930328520354238315002503599094931877479881840
Line 583, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 50880895440 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 50880895440 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 50880895440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.sysrst_ctrl_combo_detect_with_pre_cond.25329589324302709936626569134985809684046247360229390651062483176620511697574
Line 583, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 30489925244 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 30509925244 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 30529925244 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 40795367898 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30
  UVM_INFO @ 40795388516 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2a

... and 3 more failures.

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all has 1 failures.

5.sysrst_ctrl_stress_all.108325770125770009237896410454213720307005788459430942611131354956652653952518
Line 565, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 9597385663 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 9597385663 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9597385663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 7.sysrst_ctrl_stress_all.22665840283211274686449216126673986018995509900040473846988305950524619214977
    Line 561, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 7457062614 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 7457062614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-* has 1 failures: