| | | | | | |
| tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 1222528304 | 2644700 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 1222527726 | 5888 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 1222528304 | 16453883 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 1222528304 | 209151 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 1222527726 | 6483 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 1222528304 | 18480773 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 1222528304 | 635686 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 1222528304 | 18480773 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 1222528304 | 635686 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 1222528304 | 635686 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 1222528304 | 635686 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 1222527726 | 3841 | 0 | 0 |
|
| tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 1222527726 | 3448 | 0 | 0 |
|
| tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.en2addrHit
| 0 | 0 | 1222527726 | 270322 | 0 | 0 |
|
| tb.dut.u_reg.reAfterRv
| 0 | 0 | 1222527726 | 270322 | 0 | 0 |
|
| tb.dut.u_reg.rePulse
| 0 | 0 | 1222527726 | 143134 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1253372 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1452 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1452 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1452 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1431 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1459 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1086883 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1314 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1314 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1314 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1295 | 0 | 0 |
|
| tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1320 | 0 | 0 |
|
| tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1642074 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1962 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1962 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1962 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1941 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1973 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1588367 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1898 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1925 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1603318 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1896 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1926 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1592897 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1912 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1912 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1912 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1889 | 0 | 0 |
|
| tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1612801 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1943 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1943 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1943 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1951 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1580781 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1918 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1918 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1918 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1898 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1925 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1597915 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1917 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1917 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1917 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1894 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1924 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1556366 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1912 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1912 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1913 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1891 | 0 | 0 |
|
| tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1919 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1147413 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1349 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1349 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1350 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1327 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1358 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1161294 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1375 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1375 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1376 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1352 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1381 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1144081 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1358 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1358 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1358 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1335 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1366 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1128338 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1371 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1371 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1371 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1349 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1377 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6479066 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7071 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7071 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7071 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7042 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7077 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6505146 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7110 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7110 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7111 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7082 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7114 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6408023 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7083 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7083 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7083 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7054 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7090 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6364442 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7151 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7151 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7151 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7123 | 0 | 0 |
|
| tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7159 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 7077711 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7697 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7697 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7697 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7671 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7705 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6950898 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7618 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7618 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7619 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7591 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7626 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6891479 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7624 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7624 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7625 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7598 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7631 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6854564 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7700 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7700 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7701 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7675 | 0 | 0 |
|
| tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7708 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1703151 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 2055 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 2055 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 2055 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 2032 | 0 | 0 |
|
| tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 2064 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 925486 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1127 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1127 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1127 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1104 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1134 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 1722066 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 2080 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 2080 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 2080 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 2057 | 0 | 0 |
|
| tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 2089 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 2610599 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 3033 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 3033 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 3033 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 3011 | 0 | 0 |
|
| tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 3040 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 5375639 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 6173 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 6173 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 6173 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 6149 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 6181 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 6442910 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 7308 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 7308 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 7308 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 7285 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 7318 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 5331818 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 6065 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 6065 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 6066 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 6042 | 0 | 0 |
|
| tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 6075 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 909 | 909 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 945781 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1119 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1119 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1119 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1096 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1125 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 953072 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1119 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1119 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1120 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1097 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1125 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 925906 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1116 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1116 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1117 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1097 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1124 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 937556 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1105 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1222527726 | 1105 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 7600940 | 1105 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1082 | 0 | 0 |
|
| tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1113 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.BusySrcReqChk_A
| 0 | 0 | 1222527726 | 891161 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A
| 0 | 0 | 7600940 | 6784382 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 1222527726 | 1136 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A
| 0 | 0 | 1222527726 | 1222088113 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 7600940 | 778 | 0 | 909 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 7600940 | 778 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 1222527726 | 1914 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 7600940 | 1134 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 7600940 | 1114 | 0 | 0 |
|
| tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1222527726 | 1143 | 0 | 0 |
|
| tb.dut.u_reg.wePulse
| 0 | 0 | 1222527726 | 127188 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntClr_A
| 0 | 0 | 7341965 | 313 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntIncr_A
| 0 | 0 | 7341965 | 80053 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntNoWrap_A
| 0 | 0 | 7341965 | 6708039 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectStDropOut_A
| 0 | 0 | 7341965 | 2 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedOut_A
| 0 | 0 | 7341965 | 961 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedPulseOut_A
| 0 | 0 | 7341965 | 143 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledIdleSt_A
| 0 | 0 | 7341965 | 6621174 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledNoDetection_A
| 0 | 0 | 7341965 | 6623401 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDebounceSt_A
| 0 | 0 | 7341965 | 174 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDetectSt_A
| 0 | 0 | 7341965 | 145 | 0 | 0 |
|
| tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterStableSt_A
| 0 | 0 | 7341965 | 143 | 0 | 0 |
|