Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T21,T24,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T21,T24,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T21,T24,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T24,T25
1	0	Covered	T1,T4,T12
1	1	Covered	T21,T24,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T24,T25
0	1	Covered	T93,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T24,T25
0	1	Covered	T21,T24,T25
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T24,T25
1	-	Covered	T21,T24,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T24,T25
DetectSt	168	Covered	T21,T24,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T21,T24,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T24,T25
DebounceSt->IdleSt	163	Covered	T25,T46,T49
DetectSt->IdleSt	186	Covered	T93,T95
DetectSt->StableSt	191	Covered	T21,T24,T25
IdleSt->DebounceSt	148	Covered	T21,T24,T25
StableSt->IdleSt	206	Covered	T21,T24,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T24,T25
0	1	Covered	T21,T24,T25
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T24,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T24,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T24,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T46,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T24,T25
DetectSt	-	-	-	-	1	-	-	Covered	T93,T95
DetectSt	-	-	-	-	0	1	-	Covered	T21,T24,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T24,T25
StableSt	-	-	-	-	-	-	0	Covered	T21,T24,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	313	0	0
CntIncr_A	7341965	80053	0	0
CntNoWrap_A	7341965	6708039	0	0
DetectStDropOut_A	7341965	2	0	0
DetectedOut_A	7341965	961	0	0
DetectedPulseOut_A	7341965	143	0	0
DisabledIdleSt_A	7341965	6621174	0	0
DisabledNoDetection_A	7341965	6623401	0	0
EnterDebounceSt_A	7341965	174	0	0
EnterDetectSt_A	7341965	145	0	0
EnterStableSt_A	7341965	143	0	0
PulseIsPulse_A	7341965	143	0	0
StayInStableSt	7341965	818	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	6727	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	142	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	313	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	2	0	0
T22	494	0	0	0
T24	749	2	0	0
T25	635	4	0	0
T40	0	4	0	0
T43	0	4	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	0	5	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	4	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	80053	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	41	0	0
T22	494	0	0	0
T24	749	46	0	0
T25	635	104	0	0
T40	0	60	0	0
T43	0	103	0	0
T46	0	100	0	0
T47	0	10	0	0
T49	0	224	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	63	0	0
T86	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708039	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2	0	0
T93	7723	1	0	0
T95	0	1	0	0
T97	402	0	0	0
T98	505	0	0	0
T99	412	0	0	0
T100	493	0	0	0
T101	1742	0	0	0
T102	684	0	0	0
T103	493	0	0	0
T104	890	0	0	0
T105	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	961	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	6	0	0
T22	494	0	0	0
T24	749	4	0	0
T25	635	12	0	0
T40	0	19	0	0
T43	0	16	0	0
T46	0	6	0	0
T47	0	6	0	0
T49	0	15	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	13	0	0
T86	0	11	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	143	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	1	0	0
T22	494	0	0	0
T24	749	1	0	0
T25	635	1	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	2	0	0
T86	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6621174	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6623401	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	174	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	1	0	0
T22	494	0	0	0
T24	749	1	0	0
T25	635	3	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	3	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	2	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	145	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	1	0	0
T22	494	0	0	0
T24	749	1	0	0
T25	635	1	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	2	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	143	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	1	0	0
T22	494	0	0	0
T24	749	1	0	0
T25	635	1	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	2	0	0
T86	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	143	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	1	0	0
T22	494	0	0	0
T24	749	1	0	0
T25	635	1	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	2	0	0
T86	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	818	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	5	0	0
T22	494	0	0	0
T24	749	3	0	0
T25	635	11	0	0
T40	0	17	0	0
T43	0	14	0	0
T46	0	5	0	0
T47	0	5	0	0
T49	0	13	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	11	0	0
T86	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6727	0	0
T1	13698	16	0	0
T2	581	0	0	0
T3	1030	7	0	0
T4	510	7	0	0
T5	943	2	0	0
T6	573	1	0	0
T12	17295	31	0	0
T13	409	0	0	0
T14	420	2	0	0
T15	407	0	0	0
T21	0	22	0	0
T50	0	1	0	0
T51	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	142	0	0
T7	17678	0	0	0
T8	21411	0	0	0
T21	2980	1	0	0
T22	494	0	0	0
T24	749	1	0	0
T25	635	1	0	0
T40	0	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T71	0	2	0	0
T86	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T20,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T4,T12
1	1	Covered	T3,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T58
0	1	Covered	T83,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T58
0	1	Unreachable
1	0	Covered	T3,T20,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T19,T20
DetectSt	168	Covered	T3,T20,T58
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T20,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T20,T58
DebounceSt->IdleSt	163	Covered	T19,T56,T71
DetectSt->IdleSt	186	Covered	T83,T84,T85
DetectSt->StableSt	191	Covered	T3,T20,T58
IdleSt->DebounceSt	148	Covered	T3,T19,T20
StableSt->IdleSt	206	Covered	T3,T20,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T19,T20
0	1	Covered	T3,T19,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T20,T58
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T20,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T56,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T83,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T3,T20,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T20,T58
StableSt	-	-	-	-	-	-	0	Covered	T3,T20,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	189	0	0
CntIncr_A	7341965	81655	0	0
CntNoWrap_A	7341965	6708163	0	0
DetectStDropOut_A	7341965	17	0	0
DetectedOut_A	7341965	343297	0	0
DetectedPulseOut_A	7341965	57	0	0
DisabledIdleSt_A	7341965	5741958	0	0
DisabledNoDetection_A	7341965	5744241	0	0
EnterDebounceSt_A	7341965	116	0	0
EnterDetectSt_A	7341965	74	0	0
EnterStableSt_A	7341965	57	0	0
PulseIsPulse_A	7341965	57	0	0
StayInStableSt	7341965	343240	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	6727	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_sticky_sva.StableStDropOut_A	7341965	535250	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	189	0	0
T3	1030	4	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	3	0	0
T20	0	4	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	3	0	0
T58	0	4	0	0
T71	0	3	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	81655	0	0
T3	1030	30	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	258	0	0
T20	0	170	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	141	0	0
T58	0	90	0	0
T71	0	113	0	0
T72	0	64	0	0
T73	0	62	0	0
T74	0	124	0	0
T75	0	304	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708163	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	625	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	17	0	0
T83	214936	1	0	0
T84	0	2	0	0
T85	0	3	0	0
T110	810	0	0	0
T113	0	1	0	0
T114	0	5	0	0
T115	0	2	0	0
T116	0	3	0	0
T117	406	0	0	0
T118	822	0	0	0
T119	11978	0	0	0
T120	422	0	0	0
T121	22652	0	0	0
T122	412	0	0	0
T123	19020	0	0	0
T124	726	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	343297	0	0
T3	1030	63	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	751	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T58	0	239	0	0
T71	0	74	0	0
T72	0	80	0	0
T73	0	66	0	0
T74	0	456	0	0
T83	0	162872	0	0
T110	0	228	0	0
T112	0	181	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	57	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T58	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	2	0	0
T110	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5741958	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	272	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5744241	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	273	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	116	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	3	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	3	0	0
T58	0	2	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	74	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T58	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	3	0	0
T110	0	1	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	57	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T58	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	2	0	0
T110	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	57	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T58	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	2	0	0
T110	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	343240	0	0
T3	1030	61	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	749	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T58	0	237	0	0
T71	0	73	0	0
T72	0	79	0	0
T73	0	65	0	0
T74	0	454	0	0
T83	0	162870	0	0
T110	0	227	0	0
T112	0	180	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6727	0	0
T1	13698	16	0	0
T2	581	0	0	0
T3	1030	7	0	0
T4	510	7	0	0
T5	943	2	0	0
T6	573	1	0	0
T12	17295	31	0	0
T13	409	0	0	0
T14	420	2	0	0
T15	407	0	0	0
T21	0	22	0	0
T50	0	1	0	0
T51	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	535250	0	0
T3	1030	216	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	136	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T58	0	228	0	0
T71	0	79585	0	0
T72	0	94	0	0
T73	0	91	0	0
T74	0	89	0	0
T83	0	269	0	0
T110	0	46	0	0
T112	0	44	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T3
1	1	Covered	T1,T4,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T4,T3
1	1	Covered	T3,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T20
0	1	Covered	T20,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T20
0	1	Unreachable
1	0	Covered	T3,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T19,T20
DetectSt	168	Covered	T3,T19,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T19,T20
DebounceSt->IdleSt	163	Covered	T58,T72,T75
DetectSt->IdleSt	186	Covered	T20,T81,T82
DetectSt->StableSt	191	Covered	T3,T19,T20
IdleSt->DebounceSt	148	Covered	T3,T19,T20
StableSt->IdleSt	206	Covered	T3,T19,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T19,T20
0	1	Covered	T3,T19,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T19,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T58,T72,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T20,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T3,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T3,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	200	0	0
CntIncr_A	7341965	61708	0	0
CntNoWrap_A	7341965	6708152	0	0
DetectStDropOut_A	7341965	21	0	0
DetectedOut_A	7341965	229030	0	0
DetectedPulseOut_A	7341965	52	0	0
DisabledIdleSt_A	7341965	5741958	0	0
DisabledNoDetection_A	7341965	5744241	0	0
EnterDebounceSt_A	7341965	128	0	0
EnterDetectSt_A	7341965	73	0	0
EnterStableSt_A	7341965	52	0	0
PulseIsPulse_A	7341965	52	0	0
StayInStableSt	7341965	228978	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_sticky_sva.StableStDropOut_A	7341965	668927	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	200	0	0
T3	1030	4	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	2	0	0
T20	0	12	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	2	0	0
T58	0	7	0	0
T71	0	4	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	61708	0	0
T3	1030	60	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	52	0	0
T20	0	462	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	80	0	0
T58	0	252	0	0
T71	0	946	0	0
T72	0	174	0	0
T73	0	70	0	0
T74	0	48	0	0
T75	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708152	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	625	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	21	0	0
T20	2303	5	0	0
T43	629	0	0	0
T44	20791	0	0	0
T61	2358	0	0	0
T65	522	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T125	0	3	0	0
T126	0	2	0	0
T127	0	1	0	0
T128	0	8	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T132	423	0	0	0
T133	341873	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	229030	0	0
T3	1030	160	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	126	0	0
T20	0	79	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	205	0	0
T71	0	872	0	0
T73	0	99	0	0
T74	0	102	0	0
T83	0	122	0	0
T110	0	23	0	0
T111	0	218	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	52	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5741958	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	272	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5744241	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	273	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	128	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	1	0	0
T20	0	6	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T58	0	7	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	73	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	1	0	0
T20	0	6	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	52	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	52	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T83	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	228978	0	0
T3	1030	158	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	125	0	0
T20	0	78	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	204	0	0
T71	0	870	0	0
T73	0	98	0	0
T74	0	100	0	0
T83	0	120	0	0
T110	0	22	0	0
T111	0	217	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	668927	0	0
T3	1030	107	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	215	0	0
T20	0	164	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	187	0	0
T71	0	78012	0	0
T73	0	57	0	0
T74	0	522	0	0
T83	0	209264	0	0
T110	0	321	0	0
T111	0	587	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T3,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T20,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T20
1	0	Covered	T1,T4,T2
1	1	Covered	T3,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T56
0	1	Covered	T71,T72,T74
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T56
0	1	Unreachable
1	0	Covered	T3,T20,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T19,T20
DetectSt	168	Covered	T3,T20,T56
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T20,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T20,T56
DebounceSt->IdleSt	163	Covered	T19,T72,T74
DetectSt->IdleSt	186	Covered	T71,T72,T74
DetectSt->StableSt	191	Covered	T3,T20,T56
IdleSt->DebounceSt	148	Covered	T3,T19,T20
StableSt->IdleSt	206	Covered	T3,T20,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T19,T20
0	1	Covered	T3,T19,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T20,T56
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T20,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T72,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T71,T72,T74
DetectSt	-	-	-	-	0	1	-	Covered	T3,T20,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T20,T56
StableSt	-	-	-	-	-	-	0	Covered	T3,T20,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	176	0	0
CntIncr_A	7341965	307095	0	0
CntNoWrap_A	7341965	6708176	0	0
DetectStDropOut_A	7341965	5	0	0
DetectedOut_A	7341965	40654	0	0
DetectedPulseOut_A	7341965	51	0	0
DisabledIdleSt_A	7341965	5741958	0	0
DisabledNoDetection_A	7341965	5744241	0	0
EnterDebounceSt_A	7341965	121	0	0
EnterDetectSt_A	7341965	56	0	0
EnterStableSt_A	7341965	51	0	0
PulseIsPulse_A	7341965	51	0	0
StayInStableSt	7341965	40603	0	0
gen_high_event_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_sticky_sva.StableStDropOut_A	7341965	612449	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	176	0	0
T3	1030	4	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	3	0	0
T20	0	4	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	2	0	0
T58	0	4	0	0
T71	0	4	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	0	6	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	307095	0	0
T3	1030	30	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	273	0	0
T20	0	102	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	29	0	0
T58	0	50	0	0
T71	0	47459	0	0
T72	0	144	0	0
T73	0	80	0	0
T74	0	144	0	0
T75	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708176	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	625	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5	0	0
T71	92874	1	0	0
T72	85022	1	0	0
T73	896	0	0	0
T74	0	1	0	0
T86	2677	0	0	0
T87	18716	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	31600	0	0	0
T137	681	0	0	0
T138	636	0	0	0
T139	2250	0	0	0
T140	21381	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	40654	0	0
T3	1030	45	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	563	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	123	0	0
T58	0	276	0	0
T71	0	32309	0	0
T73	0	108	0	0
T74	0	39	0	0
T75	0	332	0	0
T83	0	577	0	0
T110	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	51	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T58	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T83	0	2	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5741958	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	272	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5744241	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	273	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	121	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T19	0	3	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T58	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	4	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	56	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T58	0	2	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T83	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	51	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T58	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T83	0	2	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	51	0	0
T3	1030	2	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	2	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	1	0	0
T58	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T83	0	2	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	40603	0	0
T3	1030	43	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	561	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	122	0	0
T58	0	274	0	0
T71	0	32308	0	0
T73	0	107	0	0
T74	0	38	0	0
T75	0	331	0	0
T83	0	575	0	0
T110	0	44	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	612449	0	0
T3	1030	268	0	0
T5	943	0	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T20	0	412	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T56	0	339	0	0
T58	0	263	0	0
T71	0	30	0	0
T73	0	42	0	0
T74	0	202	0	0
T75	0	284	0	0
T83	0	208879	0	0
T110	0	304	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T11,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T11,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T11,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T34
1	0	Covered	T1,T4,T2
1	1	Covered	T6,T11,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T34
0	1	Covered	T34
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T34
0	1	Covered	T34,T40,T39
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T11,T34
1	-	Covered	T34,T40,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T34
DetectSt	168	Covered	T6,T11,T34
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T11,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T34
DebounceSt->IdleSt	163	Covered	T34,T77
DetectSt->IdleSt	186	Covered	T34
DetectSt->StableSt	191	Covered	T6,T11,T34
IdleSt->DebounceSt	148	Covered	T6,T11,T34
StableSt->IdleSt	206	Covered	T11,T34,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T34
0	1	Covered	T6,T11,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T34
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T34
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T34
DetectSt	-	-	-	-	1	-	-	Covered	T34
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T40,T39
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	88	0	0
CntIncr_A	7341965	2403	0	0
CntNoWrap_A	7341965	6708264	0	0
DetectStDropOut_A	7341965	1	0	0
DetectedOut_A	7341965	2985	0	0
DetectedPulseOut_A	7341965	42	0	0
DisabledIdleSt_A	7341965	6643844	0	0
DisabledNoDetection_A	7341965	6646073	0	0
EnterDebounceSt_A	7341965	45	0	0
EnterDetectSt_A	7341965	43	0	0
EnterStableSt_A	7341965	42	0	0
PulseIsPulse_A	7341965	42	0	0
StayInStableSt	7341965	2924	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	88	0	0
T6	573	2	0	0
T7	17678	0	0	0
T11	0	2	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	2	0	0
T34	0	5	0	0
T39	0	4	0	0
T40	0	2	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	2	0	0
T83	0	2	0	0
T141	0	2	0	0
T142	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2403	0	0
T6	573	16	0	0
T7	17678	0	0	0
T11	0	25	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	42	0	0
T34	0	242	0	0
T39	0	144	0	0
T40	0	32	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	17	0	0
T83	0	98	0	0
T141	0	33	0	0
T142	0	148	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708264	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	170	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1	0	0
T20	2303	0	0	0
T34	9517	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T143	412	0	0	0
T144	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2985	0	0
T6	573	59	0	0
T7	17678	0	0	0
T11	0	41	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	18	0	0
T34	0	165	0	0
T39	0	225	0	0
T40	0	40	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	19	0	0
T83	0	117	0	0
T141	0	112	0	0
T142	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	42	0	0
T6	573	1	0	0
T7	17678	0	0	0
T11	0	1	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	1	0	0
T83	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6643844	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	3	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6646073	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	3	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	45	0	0
T6	573	1	0	0
T7	17678	0	0	0
T11	0	1	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	1	0	0
T83	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	43	0	0
T6	573	1	0	0
T7	17678	0	0	0
T11	0	1	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	1	0	0
T83	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	42	0	0
T6	573	1	0	0
T7	17678	0	0	0
T11	0	1	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	1	0	0
T83	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	42	0	0
T6	573	1	0	0
T7	17678	0	0	0
T11	0	1	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	1	0	0
T83	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2924	0	0
T6	573	57	0	0
T7	17678	0	0	0
T11	0	39	0	0
T21	2980	0	0	0
T22	494	0	0	0
T24	749	0	0	0
T33	0	17	0	0
T34	0	164	0	0
T39	0	222	0	0
T40	0	39	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T54	425	0	0	0
T55	0	18	0	0
T83	0	115	0	0
T141	0	111	0	0
T142	0	82	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	22	0	0
T20	2303	0	0	0
T33	0	1	0	0
T34	9517	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T60	491	0	0	0
T104	0	1	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	412	0	0	0
T144	427	0	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T34
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T34,T35
0	1	Covered	T34,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T34,T35
0	1	Covered	T34,T40,T39
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T34,T35
1	-	Covered	T34,T40,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T34,T35
DetectSt	168	Covered	T1,T34,T35
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T34,T35
DebounceSt->IdleSt	163	Covered	T148,T149,T150
DetectSt->IdleSt	186	Covered	T34,T81
DetectSt->StableSt	191	Covered	T1,T34,T35
IdleSt->DebounceSt	148	Covered	T1,T34,T35
StableSt->IdleSt	206	Covered	T34,T40,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T34,T35
0	1	Covered	T1,T34,T35
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T34,T35
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T149,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T34,T81
DetectSt	-	-	-	-	0	1	-	Covered	T1,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T40,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	111	0	0
CntIncr_A	7341965	55965	0	0
CntNoWrap_A	7341965	6708241	0	0
DetectStDropOut_A	7341965	2	0	0
DetectedOut_A	7341965	88903	0	0
DetectedPulseOut_A	7341965	50	0	0
DisabledIdleSt_A	7341965	6469328	0	0
DisabledNoDetection_A	7341965	6471565	0	0
EnterDebounceSt_A	7341965	60	0	0
EnterDetectSt_A	7341965	52	0	0
EnterStableSt_A	7341965	50	0	0
PulseIsPulse_A	7341965	50	0	0
StayInStableSt	7341965	88829	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	2510	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	111	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	6	0	0
T35	0	2	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	4	0	0
T151	0	2	0	0
T152	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	55965	0	0
T1	13698	16	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	56	0	0
T33	0	84	0	0
T34	0	234	0	0
T35	0	22	0	0
T38	0	94	0	0
T39	0	144	0	0
T40	0	64	0	0
T151	0	13	0	0
T152	0	121	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708241	0	0
T1	13698	10063	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2	0	0
T20	2303	0	0	0
T34	9517	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T60	491	0	0	0
T81	0	1	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T143	412	0	0	0
T144	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	88903	0	0
T1	13698	65	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	115	0	0
T33	0	125	0	0
T34	0	83	0	0
T35	0	42	0	0
T38	0	161	0	0
T39	0	82	0	0
T40	0	59	0	0
T151	0	58	0	0
T152	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	50	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6469328	0	0
T1	13698	9979	0	0
T2	581	4	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6471565	0	0
T1	13698	9988	0	0
T2	581	4	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	60	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	52	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	3	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	50	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	50	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	88829	0	0
T1	13698	63	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T32	0	113	0	0
T33	0	122	0	0
T34	0	80	0	0
T35	0	40	0	0
T38	0	159	0	0
T39	0	80	0	0
T40	0	56	0	0
T151	0	57	0	0
T152	0	170	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2510	0	0
T1	13698	9	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	6	0	0
T5	943	1	0	0
T6	573	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	1	0	0
T15	407	0	0	0
T21	0	16	0	0
T22	0	5	0	0
T50	0	2	0	0
T51	0	5	0	0
T52	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	25	0	0
T20	2303	0	0	0
T33	0	1	0	0
T34	9517	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T60	491	0	0	0
T83	0	1	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T143	412	0	0	0
T144	427	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0