Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2113

1

T12

12

T7

8

T8

40

auto[1]

718

1

T1

7

T7

4

T8

12

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2159

1

T1

3

T12

10

T8

23

auto[1]

672

1

T1

4

T12

2

T7

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2144

1

T1

3

T12

10

T7

3

auto[1]

687

1

T1

4

T12

2

T7

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2274

1

T1

3

T12

10

T7

9

auto[1]

557

1

T1

4

T12

2

T7

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2555

1

T1

7

T12

8

T7

12

auto[1]

276

1

T12

4

T8

10

T26

12

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2560

1

T1

7

T12

12

T7

12

auto[1]

271

1

T26

8

T41

4

T44

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2563

1

T1

7

T12

10

T7

12

auto[1]

268

1

T12

2

T8

29

T26

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2515

1

T1

7

T12

12

T7

12

auto[1]

316

1

T8

35

T41

4

T44

14

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2554

1

T1

7

T12

10

T7

12

auto[1]

277

1

T12

2

T8

12

T44

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2230

1

T12

10

T7

11

T8

52

auto[1]

601

1

T1

7

T12

2

T7

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

844

1

T1

7

T7

12

T9

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

58

1

T26

2

T67

4

T226

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

111

1

T31

2

T226

5

T228

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T12

2

T226

5

T338

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T67

3

T194

7

T89

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

51

1

T68

3

T227

1

T338

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23

1

T8

6

T31

2

T339

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T44

6

T161

2

T340

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

84

1

T41

7

T119

2

T341

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T12

2

T342

4

T343

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12

1

T344

1

T345

5

T346

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T239

2

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T8

13

T44

8

T229

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T8

10

T230

7

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T8

6

T347

1

T348

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T119

4

T230

1

T341

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

43

1

T26

2

T330

10

T249

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36

1

T228

1

T349

1

T336

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T338

2

T249

8

T337

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T41

4

T68

3

T119

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T330

6

T350

3

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T70

2

T343

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

22

1

T26

1

T67

2

T335

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T350

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

7

1

T351

5

T352

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

134

1

T8

6

T107

8

T72

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

131

1

T109

26

T68

6

T230

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

87

1

T1

3

T10

4

T42

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

91

1

T9

13

T26

4

T119

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

51

1

T26

1

T140

5

T251

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T12

2

T226

13

T344

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T67

2

T123

3

T330

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

97

1

T71

9

T70

2

T228

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

80

1

T41

4

T67

3

T199

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T227

1

T134

5

T253

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T250

1

T123

3

T335

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

85

1

T108

4

T109

3

T72

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

42

1

T72

3

T250

1

T349

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T10

2

T72

4

T353

13

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T76

1

T303

3

T127

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

111

1

T8

23

T44

6

T30

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

113

1

T8

6

T41

7

T106

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T42

8

T44

8

T30

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T72

12

T200

2

T231

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T42

7

T87

6

T140

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T7

3

T228

1

T251

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

18

1

T30

2

T328

2

T329

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T72

3

T231

1

T119

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

132

1

T12

2

T7

8

T72

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T31

2

T107

2

T89

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

18

1

T106

3

T71

1

T72

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T7

1

T10

1

T232

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T10

3

T107

3

T161

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T328

3

T134

1

T127

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

11

1

T67

4

T121

2

T354

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T1

4

T106

3

T355

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded