Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T4

9

T51

6

T34

17

auto[1]

1059

1

T4

11

T51

14

T34

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

499

1

T4

5

T51

5

T34

12

from_0to1

505

1

T4

5

T51

6

T34

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T4

12

T51

12

T34

18

auto[1]

1051

1

T4

8

T51

8

T34

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T4

12

T51

6

T34

23

auto[1]

1023

1

T4

8

T51

14

T34

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T4

1

T51

1

T34

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T34

2

T40

2

T71

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T4

1

T51

1

T34

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T51

1

T34

2

T40

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T4

1

T34

2

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T4

1

T51

1

T174

3

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T34

2

T40

2

T174

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T34

1

T40

1

T71

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T4

2

T34

2

T174

2

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T51

1

T34

1

T174

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T34

1

T40

2

T375

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T4

1

T51

1

T34

2

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T4

1

T51

1

T34

3

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T51

2

T34

2

T40

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T4

1

T34

2

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T4

1

T51

2

T136

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T4

8

T51

7

T34

19

auto[1]

1042

1

T4

12

T51

13

T34

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T4

7

T51

5

T34

9

from_0to1

499

1

T4

7

T51

6

T34

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T4

7

T51

13

T34

15

auto[1]

1010

1

T4

13

T51

7

T34

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T4

10

T51

11

T34

15

auto[1]

1008

1

T4

10

T51

9

T34

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T34

2

T45

1

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T51

1

T34

1

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T4

1

T34

1

T376

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T4

2

T45

1

T40

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T4

1

T51

2

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T51

1

T34

2

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T4

1

T34

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T4

2

T34

2

T45

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T4

2

T51

1

T40

3

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T4

1

T51

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T51

2

T34

1

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T4

1

T34

3

T174

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T51

1

T71

2

T86

2

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T51

1

T34

2

T40

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T51

1

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T4

2

T45

1

T40

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025

1

T4

15

T51

6

T34

12

auto[1]

1048

1

T4

5

T51

14

T34

28

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T4

4

T51

5

T34

11

from_0to1

500

1

T4

5

T51

5

T34

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T4

9

T51

10

T34

19

auto[1]

986

1

T4

11

T51

10

T34

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T4

6

T51

8

T34

19

auto[1]

1033

1

T4

14

T51

12

T34

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T51

1

T40

2

T71

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T4

2

T45

1

T71

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T4

1

T45

1

T40

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T4

1

T34

1

T40

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T4

2

T45

1

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T4

1

T45

2

T40

4

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T34

3

T45

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T4

1

T51

1

T34

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T34

3

T45

1

T174

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T51

2

T34

4

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T51

1

T34

1

T40

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T51

1

T34

2

T45

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T51

1

T34

2

T45

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T51

1

T40

1

T174

2

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T4

1

T51

1

T34

2

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T51

1

T34

2

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T4

10

T51

10

T34

21

auto[1]

1038

1

T4

10

T51

10

T34

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T4

6

T51

5

T34

10

from_0to1

497

1

T4

7

T51

5

T34

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T4

11

T51

10

T34

22

auto[1]

1038

1

T4

9

T51

10

T34

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T4

7

T51

8

T34

17

auto[1]

1073

1

T4

13

T51

12

T34

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T34

3

T40

1

T71

2

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T4

2

T51

1

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T4

1

T51

1

T34

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T4

1

T45

1

T136

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T4

1

T34

2

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T4

1

T71

1

T136

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T34

1

T45

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T4

1

T51

2

T34

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T45

1

T40

1

T174

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T4

1

T51

1

T34

4

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T4

1

T34

1

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T51

2

T40

3

T174

2

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T51

1

T34

2

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T4

3

T51

1

T34

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T45

1

T40

2

T71

2

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T4

1

T51

1

T34

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T4

11

T51

8

T34

27

auto[1]

1012

1

T4

9

T51

12

T34

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T4

6

T51

6

T34

12

from_0to1

501

1

T4

6

T51

5

T34

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1013

1

T4

11

T51

10

T34

20

auto[1]

1060

1

T4

9

T51

10

T34

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T4

7

T51

13

T34

19

auto[1]

1055

1

T4

13

T51

7

T34

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T51

1

T34

3

T40

2

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T4

2

T34

1

T40

4

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T51

2

T34

3

T158

4

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T4

1

T34

1

T40

4

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T51

1

T45

1

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T4

2

T51

1

T34

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T4

1

T40

2

T174

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T34

3

T40

1

T71

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T4

1

T51

1

T34

2

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T4

1

T40

2

T174

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T51

2

T34

1

T45

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T4

1

T34

1

T40

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T51

1

T40

5

T174

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T34

1

T45

1

T40

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T4

1

T51

1

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T4

2

T51

1

T34

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T4

11

T51

16

T34

20

auto[1]

1055

1

T4

9

T51

4

T34

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

494

1

T4

4

T51

6

T34

10

from_0to1

499

1

T4

5

T51

6

T34

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T4

11

T51

7

T34

18

auto[1]

1022

1

T4

9

T51

13

T34

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T4

14

T51

9

T34

22

auto[1]

1026

1

T4

6

T51

11

T34

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T4

1

T51

1

T45

3

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T51

1

T71

1

T86

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T4

1

T51

2

T34

2

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T4

1

T51

1

T34

3

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T51

1

T34

1

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T51

2

T34

3

T40

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T4

3

T34

3

T40

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T51

1

T34

1

T71

2

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T34

3

T71

2

T136

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T174

1

T71

5

T136

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T4

1

T51

1

T34

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T34

1

T71

1

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T4

1

T51

1

T34

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T4

1

T34

1

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T34

1

T45

2

T174

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T51

1

T174

1

T71

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T4

11

T51

10

T34

22

auto[1]

1028

1

T4

9

T51

10

T34

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

508

1

T4

6

T51

6

T34

9

from_0to1

498

1

T4

6

T51

5

T34

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T4

7

T51

9

T34

19

auto[1]

1049

1

T4

13

T51

11

T34

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T4

8

T51

7

T34

22

auto[1]

1019

1

T4

12

T51

13

T34

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T4

1

T34

1

T71

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T4

2

T51

1

T34

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T4

1

T51

1

T34

2

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T4

1

T51

2

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T51

1

T34

3

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T4

1

T51

2

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T34

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T4

1

T34

1

T40

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T51

1

T45

2

T40

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T34

2

T45

1

T40

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T51

1

T34

1

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T4

1

T34

2

T40

5

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T4

1

T51

1

T34

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T4

1

T51

1

T34

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T34

1

T71

2

T136

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T4

1

T34

1

T45

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T4

7

T51

12

T34

21

auto[1]

1035

1

T4

13

T51

8

T34

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

500

1

T4

4

T51

6

T34

9

from_0to1

490

1

T4

5

T51

6

T34

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T4

8

T51

10

T34

19

auto[1]

1015

1

T4

12

T51

10

T34

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T4

8

T51

9

T34

22

auto[1]

1011

1

T4

12

T51

11

T34

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T4

1

T51

1

T34

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T174

1

T71

2

T136

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T51

1

T34

1

T40

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T4

1

T34

1

T40

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T51

1

T34

2

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T4

1

T51

2

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T51

1

T34

1

T71

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T4

1

T51

1

T34

3

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T51

2

T45

2

T40

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T34

1

T45

2

T40

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T4

1

T51

1

T34

4

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T4

1

T51

1

T34

1

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T34

1

T174

1

T71

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T34

1

T40

1

T71

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T4

1

T45

2

T40

2

auto[1]

from_0to1

auto[1]

auto[1]

44

1

T4

2

T51

1

T71

2