Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157005	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121124

1

T1

280

T4

42

T2

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	145020	1			T1	411		T4	62		T2	6
values[0x0]	65962	1			T1	107		T4	33		T2	4
values[0x1]	67147	1			T1	113		T4	28		T2	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127058	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151071

1

T1

353

T4

50

T2

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	797	1			T1	1		T12	1		T51	2
valid_sources[0x01]	1809	1			T1	2		T12	1		T14	1
valid_sources[0x02]	758	1			T1	1		T12	5		T51	3
valid_sources[0x03]	920	1			T1	2		T12	4		T7	2
valid_sources[0x04]	923	1			T12	3		T21	1		T51	1
valid_sources[0x05]	776	1			T1	2		T12	1		T21	2
valid_sources[0x06]	837	1			T1	5		T12	3		T21	1
valid_sources[0x07]	1545	1			T1	2		T12	7		T21	1
valid_sources[0x08]	1602	1			T1	3		T12	4		T21	1
valid_sources[0x09]	939	1			T1	2		T12	6		T51	1
valid_sources[0x0a]	1178	1			T12	10		T21	1		T51	1
valid_sources[0x0b]	820	1			T1	2		T12	3		T8	9
valid_sources[0x0c]	957	1			T12	6		T21	5		T52	1
valid_sources[0x0d]	837	1			T1	3		T12	3		T8	3
valid_sources[0x0e]	889	1			T1	5		T12	5		T7	3
valid_sources[0x0f]	1218	1			T12	8		T8	4		T26	1
valid_sources[0x10]	804	1			T1	2		T12	2		T21	1
valid_sources[0x11]	1326	1			T1	6		T2	1		T12	1
valid_sources[0x12]	1013	1			T12	2		T21	1		T8	8
valid_sources[0x13]	829	1			T12	6		T21	2		T52	6
valid_sources[0x14]	1235	1			T1	1		T12	3		T8	5
valid_sources[0x15]	1494	1			T21	1		T8	8		T26	1
valid_sources[0x16]	990	1			T12	5		T21	1		T8	5
valid_sources[0x17]	1219	1			T12	1		T51	2		T7	1
valid_sources[0x18]	1166	1			T1	4		T12	3		T21	1
valid_sources[0x19]	958	1			T1	3		T12	7		T21	1
valid_sources[0x1a]	713	1			T12	5		T21	2		T8	3
valid_sources[0x1b]	941	1			T1	2		T12	2		T8	5
valid_sources[0x1c]	758	1			T12	3		T21	3		T8	4
valid_sources[0x1d]	1049	1			T1	1		T12	5		T21	2
valid_sources[0x1e]	900	1			T12	1		T51	2		T8	7
valid_sources[0x1f]	1402	1			T1	1		T12	3		T5	1
valid_sources[0x20]	1116	1			T12	6		T5	1		T21	1
valid_sources[0x21]	920	1			T12	2		T51	3		T8	4
valid_sources[0x22]	1003	1			T1	6		T12	8		T14	1
valid_sources[0x23]	994	1			T1	1		T21	2		T51	1
valid_sources[0x24]	864	1			T1	2		T12	1		T5	1
valid_sources[0x25]	1161	1			T1	7		T12	3		T51	1
valid_sources[0x26]	928	1			T1	1		T12	2		T5	4
valid_sources[0x27]	1571	1			T1	7		T12	2		T8	2
valid_sources[0x28]	819	1			T1	3		T12	5		T21	1
valid_sources[0x29]	1039	1			T1	1		T12	5		T14	1
valid_sources[0x2a]	1065	1			T12	2		T21	1		T7	6
valid_sources[0x2b]	907	1			T1	6		T8	5		T26	1
valid_sources[0x2c]	1087	1			T1	1		T21	1		T7	7
valid_sources[0x2d]	1284	1			T1	4		T12	5		T5	1
valid_sources[0x2e]	903	1			T1	1		T12	1		T13	2
valid_sources[0x2f]	1061	1			T1	13		T12	4		T21	1
valid_sources[0x30]	933	1			T12	1		T21	6		T7	12
valid_sources[0x31]	882	1			T1	1		T13	1		T51	2
valid_sources[0x32]	929	1			T1	8		T12	5		T52	1
valid_sources[0x33]	1057	1			T12	4		T8	6		T26	7
valid_sources[0x34]	853	1			T1	9		T21	1		T8	7
valid_sources[0x35]	936	1			T1	2		T12	3		T21	1
valid_sources[0x36]	1267	1			T12	5		T7	3		T8	7
valid_sources[0x37]	1406	1			T12	7		T21	1		T8	6
valid_sources[0x38]	2281	1			T12	2		T13	1		T8	2
valid_sources[0x39]	1057	1			T1	4		T12	3		T8	7
valid_sources[0x3a]	1534	1			T1	7		T5	1		T7	16
valid_sources[0x3b]	1024	1			T12	5		T6	1		T7	3
valid_sources[0x3c]	1311	1			T12	4		T51	1		T8	2
valid_sources[0x3d]	869	1			T1	3		T12	3		T5	1
valid_sources[0x3e]	904	1			T1	5		T12	3		T5	1
valid_sources[0x3f]	874	1			T1	3		T12	3		T14	1
valid_sources[0x40]	1113	1			T12	3		T51	1		T8	3
valid_sources[0x41]	850	1			T12	3		T21	1		T8	5
valid_sources[0x42]	850	1			T1	2		T12	6		T8	2
valid_sources[0x43]	773	1			T1	1		T12	7		T21	1
valid_sources[0x44]	1144	1			T1	2		T21	1		T8	7
valid_sources[0x45]	1047	1			T12	3		T21	3		T7	4
valid_sources[0x46]	1035	1			T1	6		T12	6		T21	1
valid_sources[0x47]	1604	1			T1	3		T12	2		T21	2
valid_sources[0x48]	875	1			T1	6		T12	1		T21	1
valid_sources[0x49]	819	1			T1	3		T12	5		T21	1
valid_sources[0x4a]	908	1			T1	1		T12	6		T21	1
valid_sources[0x4b]	1463	1			T1	3		T12	6		T5	1
valid_sources[0x4c]	1483	1			T1	4		T12	8		T13	1
valid_sources[0x4d]	1064	1			T1	4		T12	2		T21	1
valid_sources[0x4e]	1088	1			T1	4		T8	5		T63	1
valid_sources[0x4f]	1159	1			T1	8		T12	1		T21	1
valid_sources[0x50]	1213	1			T1	2		T12	4		T21	2
valid_sources[0x51]	971	1			T1	2		T12	3		T21	2
valid_sources[0x52]	1091	1			T1	4		T12	5		T21	2
valid_sources[0x53]	873	1			T1	3		T5	1		T52	1
valid_sources[0x54]	2206	1			T1	4		T12	1		T7	5
valid_sources[0x55]	1900	1			T1	1		T12	3		T21	3
valid_sources[0x56]	1240	1			T12	1		T21	1		T51	1
valid_sources[0x57]	780	1			T1	3		T12	4		T5	1
valid_sources[0x58]	1377	1			T1	4		T12	4		T21	3
valid_sources[0x59]	970	1			T12	4		T21	1		T7	6
valid_sources[0x5a]	875	1			T1	1		T12	6		T21	2
valid_sources[0x5b]	1390	1			T1	2		T12	3		T3	44
valid_sources[0x5c]	837	1			T12	6		T51	3		T8	8
valid_sources[0x5d]	800	1			T12	1		T8	2		T63	1
valid_sources[0x5e]	837	1			T1	3		T12	2		T51	3
valid_sources[0x5f]	879	1			T1	1		T12	4		T51	1
valid_sources[0x60]	1155	1			T1	1		T12	2		T21	2
valid_sources[0x61]	1132	1			T1	6		T12	3		T6	1
valid_sources[0x62]	1699	1			T1	6		T2	2		T12	2
valid_sources[0x63]	864	1			T1	1		T21	1		T51	1
valid_sources[0x64]	1227	1			T1	4		T12	4		T7	5
valid_sources[0x65]	1135	1			T1	4		T12	4		T5	1
valid_sources[0x66]	867	1			T1	6		T12	4		T21	1
valid_sources[0x67]	1147	1			T1	1		T12	7		T21	1
valid_sources[0x68]	990	1			T12	2		T21	2		T51	1
valid_sources[0x69]	844	1			T1	6		T12	10		T8	6
valid_sources[0x6a]	980	1			T1	1		T12	5		T8	5
valid_sources[0x6b]	1057	1			T12	3		T8	7		T26	1
valid_sources[0x6c]	1590	1			T1	6		T12	2		T5	1
valid_sources[0x6d]	1013	1			T1	1		T21	2		T52	2
valid_sources[0x6e]	1031	1			T1	1		T12	1		T21	2
valid_sources[0x6f]	1075	1			T12	5		T14	1		T21	1
valid_sources[0x70]	992	1			T1	5		T51	1		T8	6
valid_sources[0x71]	1161	1			T12	1		T21	3		T7	31
valid_sources[0x72]	858	1			T1	3		T12	3		T21	1
valid_sources[0x73]	1272	1			T1	1		T12	2		T6	1
valid_sources[0x74]	884	1			T1	2		T51	4		T8	8
valid_sources[0x75]	879	1			T1	4		T12	4		T51	3
valid_sources[0x76]	1084	1			T1	2		T12	3		T14	1
valid_sources[0x77]	963	1			T1	7		T12	5		T13	1
valid_sources[0x78]	988	1			T1	1		T12	4		T8	2
valid_sources[0x79]	854	1			T1	7		T12	3		T14	1
valid_sources[0x7a]	1169	1			T1	5		T12	3		T21	1
valid_sources[0x7b]	1087	1			T1	1		T2	3		T12	1
valid_sources[0x7c]	848	1			T1	3		T12	4		T51	1
valid_sources[0x7d]	997	1			T1	3		T12	5		T21	2
valid_sources[0x7e]	1460	1			T1	6		T12	1		T8	5
valid_sources[0x7f]	834	1			T12	1		T8	9		T26	2
valid_sources[0x80]	900	1			T1	2		T12	2		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65779

1

T1

198

T4

27

T2

1

values[0x0]

all_enables

biggest_size

32280

1

T1

49

T4

9

T2

3

values[0x1]

all_enables

biggest_size

23065

1

T1

33

T4

6

T12

51