Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

119 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

263

1

T266

1

T256

2

T261

2

auto[1]

565

1

T21

1

T24

1

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

407

1

T29

1

T265

1

T266

1

auto[1]

863

1

T21

3

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430

1

T266

1

T256

1

T358

1

auto[1]

503

1

T21

1

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

361

1

T29

1

T256

2

T273

1

auto[1]

533

1

T21

3

T24

2

T25

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430

1

T28

1

T29

1

T266

1

auto[1]

434

1

T21

1

T25

1

T45

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

398

1

T28

1

T29

1

T265

1

auto[1]

534

1

T21

2

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

417

1

T28

1

T29

1

T256

1

auto[1]

491

1

T21

3

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

379

1

T266

1

T256

1

T273

1

auto[1]

517

1

T21

2

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

387

1

T28

1

T29

1

T265

1

auto[1]

3224

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430

1

T29

1

T266

1

T256

3

auto[1]

3242

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

309

1

T28

1

T29

1

T265

1

auto[1]

3340

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

369

1

T28

1

T268

1

T256

2

auto[1]

3195

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

355

1

T268

1

T261

1

T262

2

auto[1]

1495

1

T7

20

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

362

1

T29

1

T256

1

T273

1

auto[1]

1635

1

T8

22

T10

20

T42

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314

1

T268

1

T256

1

T273

1

auto[1]

1805

1

T1

13

T7

20

T8

22

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

357

1

T256

1

T261

1

T262

1

auto[1]

1923

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

344

1

T266

1

T273

1

T261

3

auto[1]

1824

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335

1

T256

1

T261

1

T358

3

auto[1]

1531

1

T8

22

T26

14

T34

4

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337

1

T266

1

T256

1

T262

1

auto[1]

1930

1

T12

13

T8

22

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

368

1

T29

1

T266

1

T256

3

auto[1]

1733

1

T7

20

T9

20

T26

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

369

1

T28

1

T29

1

T265

1

auto[1]

1894

1

T12

13

T7

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

395

1

T28

1

T256

2

T261

1

auto[1]

1659

1

T1

13

T7

20

T8

22

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

362

1

T29

1

T265

1

T256

1

auto[1]

1664

1

T1

13

T12

13

T8

22

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350

1

T28

1

T273

1

T261

1

auto[1]

1625

1

T12

13

T7

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

365

1

T261

1

T262

1

T358

2

auto[1]

1571

1

T1

13

T8

22

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329

1

T29

1

T266

1

T256

1

auto[1]

1921

1

T1

13

T7

20

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

375

1

T266

1

T256

2

T326

1

auto[1]

1633

1

T1

13

T7

20

T8

22

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322

1

T29

1

T266

1

T261

1

auto[1]

1659

1

T12

13

T10

20

T42

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

399

1

T28

1

T265

1

T266

1

auto[1]

553

1

T28

1

T29

1

T272

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

410

1

T29

1

T265

1

T256

2

auto[1]

554

1

T28

2

T272

2

T265

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

503

1

T28

1

T29

1

T265

1

auto[1]

416

1

T28

1

T272

2

T265

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

462

1

T29

1

T268

1

T256

3

auto[1]

529

1

T28

2

T272

2

T265

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

352

1

T266

1

T256

2

T261

2

auto[1]

622

1

T12

13

T8

22

T44

21

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341

1

T265

1

T256

3

T261

1

auto[1]

676

1

T26

14

T229

18

T89

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

368

1

T266

1

T256

2

T262

1

auto[1]

743

1

T12

13

T8

22

T26

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

379

1

T29

1

T265

1

T266

1

auto[1]

868

1

T8

22

T41

16

T44

21

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316

1

T29

1

T266

1

T256

1

auto[1]

763

1

T44

21

T31

12

T67

16

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

329

1

T28

1

T265

1

T268

1

auto[1]

828

1

T44

21

T31

12

T229

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

344

1

T28

1

T266

1

T256

1

auto[1]

801

1

T26

14

T44

21

T31

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341

1

T28

1

T29

1

T268

1

auto[1]

899

1

T12

13

T8

22

T26

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

374

1

T28

1

T29

1

T265

1

auto[1]

805

1

T12

13

T8

22

T68

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

363

1

T29

1

T266

1

T256

2

auto[1]

664

1

T26

14

T44

21

T68

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

342

1

T261

1

T262

1

T361

1

auto[1]

788

1

T12

13

T26

14

T44

21

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331

1

T29

1

T256

1

T273

1

auto[1]

885

1

T12

13

T41

16

T68

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

367

1

T265

1

T261

2

T262

1

auto[1]

759

1

T8

22

T229

18

T226

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

359

1

T29

1

T273

1

T261

3

auto[1]

713

1

T8

22

T41

16

T44

21

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

352

1

T29

1

T256

1

T273

1

auto[1]

726

1

T12

13

T8

22

T44

21

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205

1

T265

1

T268

1

T256

1

auto[1]

848

1

T12

13

T26

14

T31

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

280

1

T29

1

T268

1

T266

1

auto[1]

860

1

T26

14

T229

18

T230

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224

1

T268

1

T266

1

T256

2

auto[1]

816

1

T44

21

T341

15

T335

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

218

1

T266

1

T256

2

T273

1

auto[1]

699

1

T8

22

T41

16

T44

21

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

204

1

T265

1

T268

1

T273

1

auto[1]

905

1

T12

13

T8

22

T41

16

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297

1

T265

1

T256

1

T261

3

auto[1]

1646

1

T1

13

T7

20

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303

1

T265

1

T261

1

T262

1

auto[1]

1563

1

T7

20

T8

22

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

364

1

T265

1

T256

2

T273

1

auto[1]

1466

1

T7

20

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

359

1

T265

1

T266

1

T256

3

auto[1]

1259

1

T12

13

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

350

1

T29

1

T265

1

T256

1

auto[1]

1467

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294

1

T256

3

T273

1

T261

2

auto[1]

1430

1

T1

13

T12

13

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

310

1

T266

1

T256

2

T261

2

auto[1]

1434

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

365

1

T256

3

T273

1

T261

1

auto[1]

1700

1

T1

13

T7

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303

1

T256

1

T261

2

T262

3

auto[1]

1652

1

T1

13

T9

20

T26

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294

1

T265

1

T256

2

T261

3

auto[1]

1495

1

T1

13

T12

13

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

240

1

T261

2

T262

2

T361

1

auto[1]

1635

1

T1

13

T7

20

T8

22

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295

1

T29

1

T256

1

T273

1

auto[1]

1549

1

T1

13

T7

20

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255

1

T266

1

T256

2

T262

1

auto[1]

1492

1

T1

13

T12

13

T34

4

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

288

1

T29

1

T256

2

T273

1

auto[1]

1569

1

T1

13

T7

20

T26

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

246

1

T266

1

T256

3

T273

1

auto[1]

1609

1

T1

13

T10

20

T42

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224

1

T265

1

T273

1

T261

1

auto[1]

1403

1

T1

13

T8

22

T34

4

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

281

1

T29

1

T273

1

T261

1

auto[1]

1933

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234

1

T29

1

T256

1

T261

1

auto[1]

1740

1

T1

13

T12

13

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272

1

T29

1

T256

1

T273

1

auto[1]

1553

1

T9

20

T10

20

T26

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267

1

T265

1

T273

1

T262

2

auto[1]

1588

1

T9

20

T10

20

T42

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

460

1

T29

1

T265

1

T268

1

auto[1]

689

1

T11

1

T133

1

T292

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

199

1

T266

1

T256

2

T261

2

auto[1]

455

1

T5

1

T6

1

T34

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170

1

T268

1

T266

1

T256

2

auto[1]

571

1

T5

1

T11

1

T34

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195

1

T256

1

T261

1

T262

2

auto[1]

520

1

T2

1

T5

1

T34

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161

1

T29

1

T266

1

T256

2

auto[1]

457

1

T6

1

T11

1

T34

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

195

1

T268

1

T256

1

T261

1

auto[1]

417

1

T1

1

T2

1

T34

1