Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T11,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T11,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T11,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T34
1	0	Covered	T1,T4,T2
1	1	Covered	T6,T11,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T34
0	1	Covered	T34,T39,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T11,T34
1	-	Covered	T34,T39,T33

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T34
DetectSt	168	Covered	T6,T11,T34
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T11,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T34
DebounceSt->IdleSt	163	Covered	T40,T83,T147
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T11,T34
IdleSt->DebounceSt	148	Covered	T6,T11,T34
StableSt->IdleSt	206	Covered	T11,T34,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T34
0	1	Covered	T6,T11,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T34
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T83,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T39,T33
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	94	0	0
CntIncr_A	7341965	52136	0	0
CntNoWrap_A	7341965	6708258	0	0
DetectStDropOut_A	7341965	0	0	0
DetectedOut_A	7341965	2759	0	0
DetectedPulseOut_A	7341965	44	0	0
DisabledIdleSt_A	7341965	6485958	0	0
DisabledNoDetection_A	7341965	6488185	0	0
EnterDebounceSt_A	7341965	50	0	0
EnterDetectSt_A	7341965	44	0	0
EnterStableSt_A	7341965	44	0	0
PulseIsPulse_A	7341965	44	0	0
StayInStableSt	7341965	2690	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	18	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7341965	94
T6	573	2
T7	17678	0
T11	0	2
T21	2980	0
T22	494	0
T24	749	0
T33	0	4
T34	0	6
T39	0	4
T40	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	2
T83	0	3
T141	0	4
T151	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	7341965	52136
T6	573	16
T7	17678	0
T11	0	25
T21	2980	0
T22	494	0
T24	749	0
T33	0	84
T34	0	234
T39	0	144
T40	0	32
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	17
T83	0	196
T141	0	66
T151	0	26

CntNoWrap_A

Name	Attempts	Real Successes
Total	7341965	6708258
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	542
T6	573	170
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7341965	2759
T6	573	38
T7	17678	0
T11	0	42
T21	2980	0
T22	494	0
T24	749	0
T33	0	147
T34	0	122
T39	0	212
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	19
T83	0	40
T141	0	120
T151	0	94
T154	0	126

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7341965	44
T6	573	1
T7	17678	0
T11	0	1
T21	2980	0
T22	494	0
T24	749	0
T33	0	2
T34	0	3
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T83	0	1
T141	0	2
T151	0	2
T154	0	3

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7341965	6485958
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	542
T6	573	3
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7341965	6488185
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	3
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7341965	50
T6	573	1
T7	17678	0
T11	0	1
T21	2980	0
T22	494	0
T24	749	0
T33	0	2
T34	0	3
T39	0	2
T40	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T83	0	2
T141	0	2
T151	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7341965	44
T6	573	1
T7	17678	0
T11	0	1
T21	2980	0
T22	494	0
T24	749	0
T33	0	2
T34	0	3
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T83	0	1
T141	0	2
T151	0	2
T154	0	3

EnterStableSt_A

Name	Attempts	Real Successes
Total	7341965	44
T6	573	1
T7	17678	0
T11	0	1
T21	2980	0
T22	494	0
T24	749	0
T33	0	2
T34	0	3
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T83	0	1
T141	0	2
T151	0	2
T154	0	3

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7341965	44
T6	573	1
T7	17678	0
T11	0	1
T21	2980	0
T22	494	0
T24	749	0
T33	0	2
T34	0	3
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T83	0	1
T141	0	2
T151	0	2
T154	0	3

StayInStableSt

Name	Attempts	Real Successes
Total	7341965	2690
T6	573	36
T7	17678	0
T11	0	40
T21	2980	0
T22	494	0
T24	749	0
T33	0	145
T34	0	118
T39	0	209
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	18
T83	0	39
T141	0	118
T151	0	91
T154	0	121

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7341965	6710637
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7341965	18
T20	2303	0
T33	0	2
T34	9517	2
T39	0	1
T41	16413	0
T43	629	0
T60	491	0
T83	0	1
T129	402	0
T130	422	0
T131	424	0
T141	0	2
T143	412	0
T144	427	0
T146	0	1
T151	0	1
T154	0	1
T155	0	1
T156	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T34,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T34,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T34,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T34
1	0	Covered	T1,T4,T12
1	1	Covered	T5,T34,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T37
0	1	Covered	T79,T157
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T37
0	1	Covered	T34,T37,T39
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T34,T37
1	-	Covered	T34,T37,T39

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T34,T37
DetectSt	168	Covered	T5,T34,T37
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T34,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T34,T37
DebounceSt->IdleSt	163	Covered	T34,T36,T141
DetectSt->IdleSt	186	Covered	T79,T157
DetectSt->StableSt	191	Covered	T5,T34,T37
IdleSt->DebounceSt	148	Covered	T5,T34,T37
StableSt->IdleSt	206	Covered	T34,T37,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T34,T37
0	1	Covered	T5,T34,T37
0	0	Excluded	T1,T4,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T5,T34,T37
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T34,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T34,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T36,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T34,T37
DetectSt	-	-	-	-	1	-	-	Covered	T79,T157
DetectSt	-	-	-	-	0	1	-	Covered	T5,T34,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T37,T39
StableSt	-	-	-	-	-	-	0	Covered	T5,T34,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	130	0	0
CntIncr_A	7341965	13719	0	0
CntNoWrap_A	7341965	6708222	0	0
DetectStDropOut_A	7341965	2	0	0
DetectedOut_A	7341965	13870	0	0
DetectedPulseOut_A	7341965	58	0	0
DisabledIdleSt_A	7341965	6572342	0	0
DisabledNoDetection_A	7341965	6574574	0	0
EnterDebounceSt_A	7341965	71	0	0
EnterDetectSt_A	7341965	60	0	0
EnterStableSt_A	7341965	58	0	0
PulseIsPulse_A	7341965	58	0	0
StayInStableSt	7341965	13791	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	2845	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	36	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7341965	130
T5	943	2
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	2
T34	0	5
T35	0	2
T36	0	3
T37	0	4
T38	0	2
T39	0	4
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	6
T158	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7341965	13719
T5	943	60
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	56
T34	0	234
T35	0	22
T36	0	152
T37	0	30
T38	0	47
T39	0	144
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	124
T158	0	84

CntNoWrap_A

Name	Attempts	Real Successes
Total	7341965	6708222
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	540
T6	573	172
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7341965	2
T79	907	1
T93	7723	0
T97	402	0
T98	505	0
T99	412	0
T100	493	0
T101	1742	0
T157	0	1
T159	404	0
T160	10810	0
T161	9984	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7341965	13870
T5	943	252
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	115
T34	0	48
T35	0	41
T36	0	42
T37	0	13
T38	0	368
T39	0	233
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	129
T158	0	70

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7341965	58
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	1
T34	0	2
T35	0	1
T36	0	1
T37	0	2
T38	0	1
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	3
T158	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7341965	6572342
T1	13698	10065
T2	581	4
T3	1030	629
T4	510	109
T5	943	3
T6	573	172
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7341965	6574574
T1	13698	10075
T2	581	4
T3	1030	630
T4	510	110
T5	943	3
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7341965	71
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	1
T34	0	3
T35	0	1
T36	0	2
T37	0	2
T38	0	1
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	3
T158	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7341965	60
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	1
T34	0	2
T35	0	1
T36	0	1
T37	0	2
T38	0	1
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	3
T158	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7341965	58
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	1
T34	0	2
T35	0	1
T36	0	1
T37	0	2
T38	0	1
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	3
T158	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7341965	58
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	1
T34	0	2
T35	0	1
T36	0	1
T37	0	2
T38	0	1
T39	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	3
T158	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7341965	13791
T5	943	250
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T32	0	113
T34	0	46
T35	0	39
T36	0	41
T37	0	11
T38	0	367
T39	0	231
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T71	0	124
T158	0	68

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7341965	2845
T1	13698	13
T2	581	0
T3	1030	0
T4	510	6
T5	943	1
T6	573	1
T12	17295	0
T13	409	0
T14	420	1
T15	407	0
T21	0	19
T22	0	5
T50	0	4
T51	0	6
T52	0	8

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7341965	6710637
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7341965	36
T20	2303	0
T34	9517	2
T36	0	1
T37	0	2
T38	0	1
T39	0	2
T41	16413	0
T43	629	0
T60	491	0
T71	0	1
T129	402	0
T130	422	0
T131	424	0
T143	412	0
T144	427	0
T145	0	1
T151	0	2
T152	0	1
T154	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T11,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T11,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T34,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T11,T34
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T11,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T40
0	1	Covered	T33
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T34,T40
0	1	Covered	T34,T40,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T34,T40
1	-	Covered	T34,T40,T33

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T11,T34
DetectSt	168	Covered	T5,T34,T40
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T34,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T34,T40
DebounceSt->IdleSt	163	Covered	T11,T34,T147
DetectSt->IdleSt	186	Covered	T33
DetectSt->StableSt	191	Covered	T5,T34,T40
IdleSt->DebounceSt	148	Covered	T5,T11,T34
StableSt->IdleSt	206	Covered	T34,T40,T33

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T11,T34
0	1	Covered	T5,T11,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T5,T34,T40
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T11,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T34,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T34,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T11,T34
DetectSt	-	-	-	-	1	-	-	Covered	T33
DetectSt	-	-	-	-	0	1	-	Covered	T5,T34,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T40,T33
StableSt	-	-	-	-	-	-	0	Covered	T5,T34,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	108	0	0
CntIncr_A	7341965	45725	0	0
CntNoWrap_A	7341965	6708244	0	0
DetectStDropOut_A	7341965	2	0	0
DetectedOut_A	7341965	89232	0	0
DetectedPulseOut_A	7341965	47	0	0
DisabledIdleSt_A	7341965	6515448	0	0
DisabledNoDetection_A	7341965	6517684	0	0
EnterDebounceSt_A	7341965	59	0	0
EnterDetectSt_A	7341965	49	0	0
EnterStableSt_A	7341965	47	0	0
PulseIsPulse_A	7341965	47	0	0
StayInStableSt	7341965	89165	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	26	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7341965	108
T5	943	2
T6	573	0
T11	0	1
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	6
T34	0	3
T36	0	2
T40	0	4
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	2
T83	0	2
T153	0	4
T162	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7341965	45725
T5	943	60
T6	573	0
T11	0	25
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	126
T34	0	156
T36	0	76
T40	0	64
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	17
T83	0	89
T153	0	148
T162	0	42

CntNoWrap_A

Name	Attempts	Real Successes
Total	7341965	6708244
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	540
T6	573	172
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7341965	2
T33	810	2
T36	1114	0
T58	1058	0
T68	12918	0
T71	92874	0
T87	18716	0
T136	31600	0
T163	505	0
T164	674	0
T165	421	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7341965	89232
T5	943	41
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	17
T34	0	41
T36	0	75
T40	0	81
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	18
T83	0	260
T153	0	113
T154	0	409
T162	0	40

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7341965	47
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	1
T34	0	1
T36	0	1
T40	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	1
T83	0	1
T153	0	2
T154	0	1
T162	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7341965	6515448
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	3
T6	573	172
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7341965	6517684
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	3
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7341965	59
T5	943	1
T6	573	0
T11	0	1
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	3
T34	0	2
T36	0	1
T40	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	1
T83	0	1
T153	0	2
T162	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7341965	49
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	3
T34	0	1
T36	0	1
T40	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	1
T83	0	1
T153	0	2
T154	0	1
T162	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7341965	47
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	1
T34	0	1
T36	0	1
T40	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	1
T83	0	1
T153	0	2
T154	0	1
T162	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7341965	47
T5	943	1
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	1
T34	0	1
T36	0	1
T40	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	1
T83	0	1
T153	0	2
T154	0	1
T162	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7341965	89165
T5	943	39
T6	573	0
T13	409	0
T14	420	0
T15	407	0
T21	2980	0
T33	0	16
T34	0	40
T36	0	74
T40	0	78
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T55	0	17
T83	0	258
T153	0	110
T154	0	407
T162	0	39

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7341965	6710637
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7341965	26
T20	2303	0
T33	0	1
T34	9517	1
T36	0	1
T40	0	1
T41	16413	0
T43	629	0
T60	491	0
T81	0	1
T129	402	0
T130	422	0
T131	424	0
T143	412	0
T144	427	0
T145	0	2
T147	0	1
T153	0	1
T162	0	1
T166	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T34,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T34,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T34,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T34
1	0	Covered	T1,T4,T12
1	1	Covered	T6,T34,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T34,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T34,T37
0	1	Covered	T6,T34,T37
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T34,T37
1	-	Covered	T6,T34,T37

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T34,T37
DetectSt	168	Covered	T6,T34,T37
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T34,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T34,T37
DebounceSt->IdleSt	163	Covered	T77,T167
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T34,T37
IdleSt->DebounceSt	148	Covered	T6,T34,T37
StableSt->IdleSt	206	Covered	T6,T34,T37

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T34,T37
0	1	Covered	T6,T34,T37
0	0	Excluded	T1,T4,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T34,T37
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T34,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T34,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T167
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T34,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T34,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T34,T37
StableSt	-	-	-	-	-	-	0	Covered	T6,T34,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	50	0	0
CntIncr_A	7341965	90386	0	0
CntNoWrap_A	7341965	6708302	0	0
DetectStDropOut_A	7341965	0	0	0
DetectedOut_A	7341965	1413	0	0
DetectedPulseOut_A	7341965	24	0	0
DisabledIdleSt_A	7341965	6449704	0	0
DisabledNoDetection_A	7341965	6451947	0	0
EnterDebounceSt_A	7341965	26	0	0
EnterDetectSt_A	7341965	24	0	0
EnterStableSt_A	7341965	24	0	0
PulseIsPulse_A	7341965	24	0	0
StayInStableSt	7341965	1376	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	6403	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	10	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7341965	50
T6	573	4
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	4
T37	0	2
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	2
T79	0	2
T145	0	4
T147	0	4
T150	0	2
T155	0	4
T168	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7341965	90386
T6	573	32
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	156
T37	0	15
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	17
T79	0	96
T145	0	102
T147	0	116
T150	0	94
T155	0	66
T168	0	28

CntNoWrap_A

Name	Attempts	Real Successes
Total	7341965	6708302
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	542
T6	573	168
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7341965	1413
T6	573	82
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	208
T37	0	8
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	19
T79	0	142
T145	0	232
T147	0	90
T150	0	63
T155	0	81
T168	0	42

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7341965	24
T6	573	2
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	2
T37	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T79	0	1
T145	0	2
T147	0	2
T150	0	1
T155	0	2
T168	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7341965	6449704
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	3
T6	573	3
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7341965	6451947
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	3
T6	573	3
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7341965	26
T6	573	2
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	2
T37	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T79	0	1
T145	0	2
T147	0	2
T150	0	1
T155	0	2
T168	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7341965	24
T6	573	2
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	2
T37	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T79	0	1
T145	0	2
T147	0	2
T150	0	1
T155	0	2
T168	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7341965	24
T6	573	2
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	2
T37	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T79	0	1
T145	0	2
T147	0	2
T150	0	1
T155	0	2
T168	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7341965	24
T6	573	2
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	2
T37	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	1
T79	0	1
T145	0	2
T147	0	2
T150	0	1
T155	0	2
T168	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7341965	1376
T6	573	79
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	205
T37	0	7
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T55	0	18
T79	0	140
T145	0	229
T147	0	87
T150	0	61
T155	0	78
T168	0	40

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7341965	6403
T1	13698	17
T2	581	0
T3	1030	7
T4	510	3
T5	943	0
T6	573	2
T12	17295	23
T13	409	0
T14	420	2
T15	407	0
T21	0	17
T50	0	2
T51	0	5
T52	0	5

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7341965	6710637
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7341965	10
T6	573	1
T7	17678	0
T21	2980	0
T22	494	0
T24	749	0
T34	0	1
T37	0	1
T50	425	0
T51	502	0
T52	525	0
T53	404	0
T54	425	0
T127	0	1
T145	0	1
T147	0	1
T155	0	1
T169	0	1
T170	0	1
T171	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T5,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T5,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T5,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T5,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T11
0	1	Covered	T36,T158,T147
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T11
0	1	Covered	T40,T39,T36
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T11
1	-	Covered	T40,T39,T36

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T11
DetectSt	168	Covered	T1,T5,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T5,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T11
DebounceSt->IdleSt	163	Covered	T34,T71,T78
DetectSt->IdleSt	186	Covered	T36,T158,T147
DetectSt->StableSt	191	Covered	T1,T5,T11
IdleSt->DebounceSt	148	Covered	T1,T5,T11
StableSt->IdleSt	206	Covered	T11,T40,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T11
0	1	Covered	T1,T5,T11
0	0	Excluded	T1,T4,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T11
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T78,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T11
DetectSt	-	-	-	-	1	-	-	Covered	T36,T158,T147
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T39,T36
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	133	0	0
CntIncr_A	7341965	112761	0	0
CntNoWrap_A	7341965	6708219	0	0
DetectStDropOut_A	7341965	5	0	0
DetectedOut_A	7341965	39924	0	0
DetectedPulseOut_A	7341965	56	0	0
DisabledIdleSt_A	7341965	6430127	0	0
DisabledNoDetection_A	7341965	6432358	0	0
EnterDebounceSt_A	7341965	73	0	0
EnterDetectSt_A	7341965	61	0	0
EnterStableSt_A	7341965	56	0	0
PulseIsPulse_A	7341965	56	0	0
StayInStableSt	7341965	39838	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	25	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7341965	133
T1	13698	2
T2	581	0
T3	1030	0
T4	510	0
T5	943	2
T6	573	0
T11	0	2
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	2
T34	0	1
T36	0	4
T39	0	4
T40	0	4
T152	0	4
T158	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	7341965	112761
T1	13698	16
T2	581	0
T3	1030	0
T4	510	0
T5	943	60
T6	573	0
T11	0	25
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	56
T34	0	86
T36	0	152
T39	0	144
T40	0	64
T71	0	2
T158	0	168

CntNoWrap_A

Name	Attempts	Real Successes
Total	7341965	6708219
T1	13698	10063
T2	581	180
T3	1030	629
T4	510	109
T5	943	540
T6	573	172
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7341965	5
T36	1114	1
T58	1058	0
T68	12918	0
T71	92874	0
T72	85022	0
T73	896	0
T87	18716	0
T136	31600	0
T137	681	0
T147	0	1
T158	0	1
T165	421	0
T172	0	1
T173	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	7341965	39924
T1	13698	44
T2	581	0
T3	1030	0
T4	510	0
T5	943	251
T6	573	0
T11	0	55
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	42
T36	0	75
T39	0	235
T40	0	229
T141	0	78
T152	0	42
T158	0	58

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7341965	56
T1	13698	1
T2	581	0
T3	1030	0
T4	510	0
T5	943	1
T6	573	0
T11	0	1
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	1
T36	0	1
T39	0	2
T40	0	2
T141	0	1
T152	0	2
T158	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7341965	6430127
T1	13698	9979
T2	581	180
T3	1030	629
T4	510	109
T5	943	3
T6	573	172
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7341965	6432358
T1	13698	9988
T2	581	181
T3	1030	630
T4	510	110
T5	943	3
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7341965	73
T1	13698	1
T2	581	0
T3	1030	0
T4	510	0
T5	943	1
T6	573	0
T11	0	1
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	1
T34	0	1
T36	0	2
T39	0	2
T40	0	2
T71	0	1
T158	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7341965	61
T1	13698	1
T2	581	0
T3	1030	0
T4	510	0
T5	943	1
T6	573	0
T11	0	1
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	1
T36	0	2
T39	0	2
T40	0	2
T141	0	1
T152	0	2
T158	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	7341965	56
T1	13698	1
T2	581	0
T3	1030	0
T4	510	0
T5	943	1
T6	573	0
T11	0	1
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	1
T36	0	1
T39	0	2
T40	0	2
T141	0	1
T152	0	2
T158	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7341965	56
T1	13698	1
T2	581	0
T3	1030	0
T4	510	0
T5	943	1
T6	573	0
T11	0	1
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	1
T36	0	1
T39	0	2
T40	0	2
T141	0	1
T152	0	2
T158	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7341965	39838
T1	13698	42
T2	581	0
T3	1030	0
T4	510	0
T5	943	249
T6	573	0
T11	0	53
T12	17295	0
T13	409	0
T14	420	0
T15	407	0
T32	0	40
T36	0	74
T39	0	233
T40	0	226
T141	0	76
T152	0	40
T158	0	57

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7341965	6710637
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7341965	25
T33	810	0
T36	0	1
T39	1145	2
T40	11345	1
T79	0	1
T81	0	3
T104	0	1
T145	0	1
T147	0	1
T152	0	2
T158	0	1
T163	505	0
T174	502	0
T175	521	0
T176	683	0
T177	490	0
T178	402	0
T179	494	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T34,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T34,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T34,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T34,T37
1	0	Covered	T1,T4,T2
1	1	Covered	T34,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T37,T38
0	1	Covered	T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T37,T38
0	1	Covered	T38,T141,T181
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T37,T38
1	-	Covered	T38,T141,T181

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T37,T38
DetectSt	168	Covered	T34,T37,T38
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T34,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T37,T38
DebounceSt->IdleSt	163	Covered	T147,T81,T135
DetectSt->IdleSt	186	Covered	T180
DetectSt->StableSt	191	Covered	T34,T37,T38
IdleSt->DebounceSt	148	Covered	T34,T37,T38
StableSt->IdleSt	206	Covered	T34,T38,T141

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T37,T38
0	1	Covered	T34,T37,T38
0	0	Excluded	T1,T4,T2	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T34,T37,T38
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T81,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T37,T38
DetectSt	-	-	-	-	1	-	-	Covered	T180
DetectSt	-	-	-	-	0	1	-	Covered	T34,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T141,T55
StableSt	-	-	-	-	-	-	0	Covered	T34,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	74	0	0
CntIncr_A	7341965	2189	0	0
CntNoWrap_A	7341965	6708278	0	0
DetectStDropOut_A	7341965	1	0	0
DetectedOut_A	7341965	2711	0	0
DetectedPulseOut_A	7341965	33	0	0
DisabledIdleSt_A	7341965	6653243	0	0
DisabledNoDetection_A	7341965	6655476	0	0
EnterDebounceSt_A	7341965	40	0	0
EnterDetectSt_A	7341965	34	0	0
EnterStableSt_A	7341965	33	0	0
PulseIsPulse_A	7341965	33	0	0
StayInStableSt	7341965	2660	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	5950	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	14	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7341965	74
T20	2303	0
T34	9517	2
T37	0	2
T38	0	4
T41	16413	0
T43	629	0
T55	0	2
T60	491	0
T104	0	2
T129	402	0
T130	422	0
T131	424	0
T141	0	2
T143	412	0
T144	427	0
T146	0	2
T154	0	2
T181	0	2
T182	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7341965	2189
T20	2303	0
T34	9517	86
T37	0	15
T38	0	94
T41	16413	0
T43	629	0
T55	0	17
T60	491	0
T104	0	57
T129	402	0
T130	422	0
T131	424	0
T141	0	33
T143	412	0
T144	427	0
T146	0	36
T154	0	84
T181	0	97
T182	0	90

CntNoWrap_A

Name	Attempts	Real Successes
Total	7341965	6708278
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	542
T6	573	172
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7341965	1
T180	669	1
T183	422	0
T184	17720	0
T185	29490	0
T186	527	0
T187	688	0
T188	524	0
T189	811	0
T190	53265	0
T191	34465	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7341965	2711
T20	2303	0
T34	9517	258
T37	0	66
T38	0	160
T41	16413	0
T43	629	0
T55	0	18
T60	491	0
T104	0	264
T129	402	0
T130	422	0
T131	424	0
T141	0	44
T143	412	0
T144	427	0
T146	0	92
T154	0	191
T181	0	41
T182	0	38

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7341965	33
T20	2303	0
T34	9517	1
T37	0	1
T38	0	2
T41	16413	0
T43	629	0
T55	0	1
T60	491	0
T104	0	1
T129	402	0
T130	422	0
T131	424	0
T141	0	1
T143	412	0
T144	427	0
T146	0	1
T154	0	1
T181	0	1
T182	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7341965	6653243
T1	13698	10065
T2	581	180
T3	1030	629
T4	510	109
T5	943	542
T6	573	3
T12	17295	16888
T13	409	8
T14	420	19
T15	407	6

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7341965	6655476
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	3
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7341965	40
T20	2303	0
T34	9517	1
T37	0	1
T38	0	2
T41	16413	0
T43	629	0
T55	0	1
T60	491	0
T104	0	1
T129	402	0
T130	422	0
T131	424	0
T141	0	1
T143	412	0
T144	427	0
T146	0	1
T154	0	1
T181	0	1
T182	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7341965	34
T20	2303	0
T34	9517	1
T37	0	1
T38	0	2
T41	16413	0
T43	629	0
T55	0	1
T60	491	0
T104	0	1
T129	402	0
T130	422	0
T131	424	0
T141	0	1
T143	412	0
T144	427	0
T146	0	1
T154	0	1
T181	0	1
T182	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7341965	33
T20	2303	0
T34	9517	1
T37	0	1
T38	0	2
T41	16413	0
T43	629	0
T55	0	1
T60	491	0
T104	0	1
T129	402	0
T130	422	0
T131	424	0
T141	0	1
T143	412	0
T144	427	0
T146	0	1
T154	0	1
T181	0	1
T182	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7341965	33
T20	2303	0
T34	9517	1
T37	0	1
T38	0	2
T41	16413	0
T43	629	0
T55	0	1
T60	491	0
T104	0	1
T129	402	0
T130	422	0
T131	424	0
T141	0	1
T143	412	0
T144	427	0
T146	0	1
T154	0	1
T181	0	1
T182	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7341965	2660
T20	2303	0
T34	9517	256
T37	0	64
T38	0	158
T41	16413	0
T43	629	0
T55	0	17
T60	491	0
T104	0	262
T129	402	0
T130	422	0
T131	424	0
T141	0	43
T143	412	0
T144	427	0
T146	0	90
T154	0	189
T181	0	40
T182	0	36

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7341965	5950
T1	13698	20
T2	581	1
T3	1030	0
T4	510	3
T5	943	0
T6	573	0
T7	0	14
T12	17295	28
T13	409	0
T14	420	2
T15	407	0
T21	0	15
T50	0	4
T51	0	3
T52	0	5

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7341965	6710637
T1	13698	10075
T2	581	181
T3	1030	630
T4	510	110
T5	943	543
T6	573	173
T12	17295	16892
T13	409	9
T14	420	20
T15	407	7

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7341965	14
T38	910	2
T127	0	1
T135	0	1
T141	0	1
T147	0	1
T151	622	0
T158	8379	0
T166	0	1
T170	0	1
T181	0	1
T192	0	1
T193	0	1
T194	21895	0
T195	446	0
T196	413	0
T197	412	0
T198	435	0
T199	16247	0
T200	16679	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr