Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T4,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T6,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T6,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T6,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T34
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T6,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T39
0	1	Covered	T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T39
0	1	Covered	T1,T6,T39
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T39
1	-	Covered	T1,T6,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T34
DetectSt	168	Covered	T1,T6,T39
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T6,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T39
DebounceSt->IdleSt	163	Covered	T34,T158,T202
DetectSt->IdleSt	186	Covered	T201
DetectSt->StableSt	191	Covered	T1,T6,T39
IdleSt->DebounceSt	148	Covered	T1,T6,T34
StableSt->IdleSt	206	Covered	T1,T6,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T34
0	1	Covered	T1,T6,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T39
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T158,T202
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T34
DetectSt	-	-	-	-	1	-	-	Covered	T201
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	113	0	0
CntIncr_A	7341965	52918	0	0
CntNoWrap_A	7341965	6708239	0	0
DetectStDropOut_A	7341965	1	0	0
DetectedOut_A	7341965	4214	0	0
DetectedPulseOut_A	7341965	50	0	0
DisabledIdleSt_A	7341965	6529831	0	0
DisabledNoDetection_A	7341965	6532067	0	0
EnterDebounceSt_A	7341965	63	0	0
EnterDetectSt_A	7341965	51	0	0
EnterStableSt_A	7341965	50	0	0
PulseIsPulse_A	7341965	50	0	0
StayInStableSt	7341965	4141	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	113	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	4	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T71	0	4	0	0
T78	0	4	0	0
T152	0	2	0	0
T158	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	52918	0	0
T1	13698	16	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	32	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	42	0	0
T34	0	86	0	0
T38	0	47	0	0
T39	0	72	0	0
T71	0	75	0	0
T78	0	72	0	0
T152	0	53	0	0
T158	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708239	0	0
T1	13698	10063	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	168	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1	0	0
T145	3556	0	0	0
T201	678	1	0	0
T202	954	0	0	0
T203	498	0	0	0
T204	2276	0	0	0
T205	425	0	0	0
T206	796	0	0	0
T207	503	0	0	0
T208	524	0	0	0
T209	521	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	4214	0	0
T1	13698	5	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	50	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	186	0	0
T38	0	274	0	0
T39	0	171	0	0
T71	0	162	0	0
T78	0	80	0	0
T142	0	42	0	0
T152	0	45	0	0
T158	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	50	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	2	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T71	0	2	0	0
T78	0	2	0	0
T142	0	1	0	0
T152	0	1	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6529831	0	0
T1	13698	9979	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	3	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6532067	0	0
T1	13698	9988	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	3	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	63	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	2	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T71	0	2	0	0
T78	0	2	0	0
T152	0	1	0	0
T158	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	51	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	2	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T71	0	2	0	0
T78	0	2	0	0
T142	0	1	0	0
T152	0	1	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	50	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	2	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T71	0	2	0	0
T78	0	2	0	0
T142	0	1	0	0
T152	0	1	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	50	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	2	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T71	0	2	0	0
T78	0	2	0	0
T142	0	1	0	0
T152	0	1	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	4141	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	47	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	184	0	0
T38	0	273	0	0
T39	0	170	0	0
T71	0	159	0	0
T78	0	77	0	0
T142	0	40	0	0
T152	0	43	0	0
T158	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	26	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T71	0	1	0	0
T78	0	1	0	0
T145	0	1	0	0
T154	0	2	0	0
T158	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T12
1	1	Covered	T5,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T5,T6,T34
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T6,T11
1	-	Covered	T5,T6,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T11
DetectSt	168	Covered	T5,T6,T11
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T6,T11
DebounceSt->IdleSt	163	Covered	T34,T158,T148
DetectSt->IdleSt	186	Covered	T78
DetectSt->StableSt	191	Covered	T5,T6,T11
IdleSt->DebounceSt	148	Covered	T5,T6,T11
StableSt->IdleSt	206	Covered	T5,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T6,T11
0	1	Covered	T5,T6,T11
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T11
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T34
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T5,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T6,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	98	0	0
CntIncr_A	7341965	62044	0	0
CntNoWrap_A	7341965	6708254	0	0
DetectStDropOut_A	7341965	1	0	0
DetectedOut_A	7341965	23698	0	0
DetectedPulseOut_A	7341965	47	0	0
DisabledIdleSt_A	7341965	6383335	0	0
DisabledNoDetection_A	7341965	6385563	0	0
EnterDebounceSt_A	7341965	52	0	0
EnterDetectSt_A	7341965	48	0	0
EnterStableSt_A	7341965	47	0	0
PulseIsPulse_A	7341965	47	0	0
StayInStableSt	7341965	23625	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	6088	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	98	0	0
T5	943	2	0	0
T6	573	2	0	0
T11	0	2	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T40	0	4	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	2	0	0
T78	0	2	0	0
T152	0	4	0	0
T158	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	62044	0	0
T5	943	60	0	0
T6	573	16	0	0
T11	0	25	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	156	0	0
T35	0	22	0	0
T40	0	64	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	49	0	0
T78	0	36	0	0
T152	0	136	0	0
T158	0	113	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708254	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	540	0	0
T6	573	170	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1	0	0
T78	2196	1	0	0
T88	5122	0	0	0
T89	9937	0	0	0
T90	5166	0	0	0
T210	433	0	0	0
T211	529	0	0	0
T212	522	0	0	0
T213	525	0	0	0
T214	532	0	0	0
T215	682	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	23698	0	0
T5	943	44	0	0
T6	573	63	0	0
T11	0	41	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	164	0	0
T35	0	42	0	0
T40	0	80	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	230	0	0
T141	0	41	0	0
T152	0	280	0	0
T158	0	186	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	47	0	0
T5	943	1	0	0
T6	573	1	0	0
T11	0	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	2	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	1	0	0
T141	0	2	0	0
T152	0	2	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6383335	0	0
T1	13698	10065	0	0
T2	581	4	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	3	0	0
T6	573	3	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6385563	0	0
T1	13698	10075	0	0
T2	581	4	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	3	0	0
T6	573	3	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	52	0	0
T5	943	1	0	0
T6	573	1	0	0
T11	0	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T40	0	2	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	1	0	0
T78	0	1	0	0
T152	0	2	0	0
T158	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	48	0	0
T5	943	1	0	0
T6	573	1	0	0
T11	0	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	2	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	1	0	0
T78	0	1	0	0
T152	0	2	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	47	0	0
T5	943	1	0	0
T6	573	1	0	0
T11	0	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	2	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	1	0	0
T141	0	2	0	0
T152	0	2	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	47	0	0
T5	943	1	0	0
T6	573	1	0	0
T11	0	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	2	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	1	0	0
T141	0	2	0	0
T152	0	2	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	23625	0	0
T5	943	43	0	0
T6	573	62	0	0
T11	0	39	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	163	0	0
T35	0	40	0	0
T40	0	77	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T71	0	228	0	0
T141	0	39	0	0
T152	0	277	0	0
T158	0	185	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6088	0	0
T1	13698	21	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	6	0	0
T5	943	1	0	0
T6	573	1	0	0
T12	17295	24	0	0
T13	409	0	0	0
T14	420	2	0	0
T15	407	0	0	0
T21	0	20	0	0
T50	0	3	0	0
T51	0	6	0	0
T52	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	20	0	0
T5	943	1	0	0
T6	573	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T104	0	1	0	0
T141	0	2	0	0
T152	0	1	0	0
T154	0	2	0	0
T158	0	1	0	0
T216	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T34
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T2,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T34
0	1	Covered	T1,T34,T71
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T34
1	-	Covered	T1,T34,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T34
DetectSt	168	Covered	T1,T2,T34
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T2,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T34
DebounceSt->IdleSt	163	Covered	T35,T217,T218
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T2,T34
IdleSt->DebounceSt	148	Covered	T1,T2,T34
StableSt->IdleSt	206	Covered	T1,T34,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T34
0	1	Covered	T1,T2,T34
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T34
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T217,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T34,T71
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	129	0	0
CntIncr_A	7341965	194431	0	0
CntNoWrap_A	7341965	6708223	0	0
DetectStDropOut_A	7341965	0	0	0
DetectedOut_A	7341965	196400	0	0
DetectedPulseOut_A	7341965	62	0	0
DisabledIdleSt_A	7341965	6214286	0	0
DisabledNoDetection_A	7341965	6216518	0	0
EnterDebounceSt_A	7341965	68	0	0
EnterDetectSt_A	7341965	62	0	0
EnterStableSt_A	7341965	62	0	0
PulseIsPulse_A	7341965	62	0	0
StayInStableSt	7341965	196306	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	129	0	0
T1	13698	2	0	0
T2	581	2	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T55	0	2	0	0
T71	0	4	0	0
T141	0	4	0	0
T142	0	2	0	0
T152	0	2	0	0
T154	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	194431	0	0
T1	13698	16	0	0
T2	581	49	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	78	0	0
T35	0	22	0	0
T55	0	17	0	0
T71	0	75	0	0
T141	0	66	0	0
T142	0	74	0	0
T152	0	68	0	0
T154	0	326	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708223	0	0
T1	13698	10063	0	0
T2	581	178	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	196400	0	0
T1	13698	6	0	0
T2	581	39	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	235	0	0
T55	0	20	0	0
T71	0	45	0	0
T141	0	216	0	0
T142	0	236	0	0
T145	0	85	0	0
T152	0	39	0	0
T154	0	167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	62	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	1	0	0
T55	0	1	0	0
T71	0	2	0	0
T141	0	2	0	0
T142	0	1	0	0
T145	0	2	0	0
T152	0	1	0	0
T154	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6214286	0	0
T1	13698	9979	0	0
T2	581	4	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6216518	0	0
T1	13698	9988	0	0
T2	581	4	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	68	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T55	0	1	0	0
T71	0	2	0	0
T141	0	2	0	0
T142	0	1	0	0
T152	0	1	0	0
T154	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	62	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	1	0	0
T55	0	1	0	0
T71	0	2	0	0
T141	0	2	0	0
T142	0	1	0	0
T145	0	2	0	0
T152	0	1	0	0
T154	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	62	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	1	0	0
T55	0	1	0	0
T71	0	2	0	0
T141	0	2	0	0
T142	0	1	0	0
T145	0	2	0	0
T152	0	1	0	0
T154	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	62	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	1	0	0
T55	0	1	0	0
T71	0	2	0	0
T141	0	2	0	0
T142	0	1	0	0
T145	0	2	0	0
T152	0	1	0	0
T154	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	196306	0	0
T1	13698	5	0	0
T2	581	37	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	234	0	0
T55	0	19	0	0
T71	0	42	0	0
T141	0	213	0	0
T142	0	234	0	0
T145	0	82	0	0
T152	0	38	0	0
T154	0	161	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	29	0	0
T1	13698	1	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	1	0	0
T71	0	1	0	0
T141	0	1	0	0
T145	0	1	0	0
T152	0	1	0	0
T154	0	2	0	0
T166	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T34
1	0	Covered	T1,T4,T12
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T36,T38,T158
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T35,T36
1	-	Covered	T36,T38,T158

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T34,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T150,T77
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T34,T35,T36
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T158
StableSt	-	-	-	-	-	-	0	Covered	T34,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	67	0	0
CntIncr_A	7341965	1982	0	0
CntNoWrap_A	7341965	6708285	0	0
DetectStDropOut_A	7341965	0	0	0
DetectedOut_A	7341965	2512	0	0
DetectedPulseOut_A	7341965	33	0	0
DisabledIdleSt_A	7341965	6545562	0	0
DisabledNoDetection_A	7341965	6547796	0	0
EnterDebounceSt_A	7341965	35	0	0
EnterDetectSt_A	7341965	33	0	0
EnterStableSt_A	7341965	33	0	0
PulseIsPulse_A	7341965	33	0	0
StayInStableSt	7341965	2467	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	6028	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	67	0	0
T20	2303	0	0	0
T34	9517	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	2	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	2	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	2	0	0
T153	0	4	0	0
T158	0	2	0	0
T202	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1982	0	0
T20	2303	0	0	0
T34	9517	164	0	0
T35	0	22	0	0
T36	0	76	0	0
T38	0	47	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	17	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	33	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	68	0	0
T153	0	148	0	0
T158	0	84	0	0
T202	0	180	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708285	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2512	0	0
T20	2303	0	0	0
T34	9517	171	0	0
T35	0	42	0	0
T36	0	74	0	0
T38	0	120	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	19	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	2	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	349	0	0
T153	0	116	0	0
T158	0	185	0	0
T202	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	33	0	0
T20	2303	0	0	0
T34	9517	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	1	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	1	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T158	0	1	0	0
T202	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6545562	0	0
T1	13698	10065	0	0
T2	581	4	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6547796	0	0
T1	13698	10075	0	0
T2	581	4	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	35	0	0
T20	2303	0	0	0
T34	9517	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	1	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	1	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T158	0	1	0	0
T202	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	33	0	0
T20	2303	0	0	0
T34	9517	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	1	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	1	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T158	0	1	0	0
T202	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	33	0	0
T20	2303	0	0	0
T34	9517	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	1	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	1	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T158	0	1	0	0
T202	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	33	0	0
T20	2303	0	0	0
T34	9517	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	1	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	1	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T158	0	1	0	0
T202	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2467	0	0
T20	2303	0	0	0
T34	9517	167	0	0
T35	0	40	0	0
T36	0	73	0	0
T38	0	119	0	0
T41	16413	0	0	0
T43	629	0	0	0
T55	0	18	0	0
T60	491	0	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T141	0	1	0	0
T143	412	0	0	0
T144	427	0	0	0
T152	0	347	0	0
T153	0	113	0	0
T158	0	184	0	0
T202	0	127	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6028	0	0
T1	13698	20	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	4	0	0
T5	943	1	0	0
T6	573	0	0	0
T7	0	10	0	0
T12	17295	27	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	0	21	0	0
T22	0	7	0	0
T50	0	3	0	0
T51	0	3	0	0
T52	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	20	0	0
T36	1114	1	0	0
T38	0	1	0	0
T58	1058	0	0	0
T68	12918	0	0	0
T71	92874	0	0	0
T72	85022	0	0	0
T73	896	0	0	0
T81	0	2	0	0
T87	18716	0	0	0
T136	31600	0	0	0
T137	681	0	0	0
T141	0	1	0	0
T145	0	1	0	0
T153	0	1	0	0
T158	0	1	0	0
T165	421	0	0	0
T202	0	1	0	0
T216	0	3	0	0
T220	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T2,T5

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T4,T12
1	1	Covered	T1,T2,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T5,T145,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T5,T39,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T5
1	-	Covered	T5,T39,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T5
DetectSt	168	Covered	T1,T2,T5
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T2,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T5
DebounceSt->IdleSt	163	Covered	T158,T142,T153
DetectSt->IdleSt	186	Covered	T5,T145,T104
DetectSt->StableSt	191	Covered	T1,T2,T5
IdleSt->DebounceSt	148	Covered	T1,T2,T5
StableSt->IdleSt	206	Covered	T5,T39,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T153,T181
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	1	-	-	Covered	T5,T145,T104
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T5
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T39,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	139	0	0
CntIncr_A	7341965	72587	0	0
CntNoWrap_A	7341965	6708213	0	0
DetectStDropOut_A	7341965	5	0	0
DetectedOut_A	7341965	11149	0	0
DetectedPulseOut_A	7341965	59	0	0
DisabledIdleSt_A	7341965	6417130	0	0
DisabledNoDetection_A	7341965	6419359	0	0
EnterDebounceSt_A	7341965	77	0	0
EnterDetectSt_A	7341965	64	0	0
EnterStableSt_A	7341965	59	0	0
PulseIsPulse_A	7341965	59	0	0
StayInStableSt	7341965	11062	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	139	0	0
T1	13698	2	0	0
T2	581	2	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	4	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	2	0	0
T36	0	4	0	0
T39	0	4	0	0
T78	0	2	0	0
T151	0	4	0	0
T158	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	72587	0	0
T1	13698	16	0	0
T2	581	49	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	120	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	42	0	0
T36	0	152	0	0
T39	0	144	0	0
T78	0	36	0	0
T151	0	26	0	0
T158	0	113	0	0
T182	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708213	0	0
T1	13698	10063	0	0
T2	581	178	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	538	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	5	0	0
T5	943	1	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T81	0	1	0	0
T104	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	11149	0	0
T1	13698	43	0	0
T2	581	122	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	43	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	86	0	0
T36	0	192	0	0
T39	0	460	0	0
T78	0	77	0	0
T151	0	79	0	0
T158	0	42	0	0
T182	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	59	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	1	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T78	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6417130	0	0
T1	13698	9979	0	0
T2	581	4	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	3	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6419359	0	0
T1	13698	9988	0	0
T2	581	4	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	3	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	77	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	2	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T78	0	1	0	0
T151	0	2	0	0
T158	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	64	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	2	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T78	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	59	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	1	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T78	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	59	0	0
T1	13698	1	0	0
T2	581	1	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	1	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T78	0	1	0	0
T151	0	2	0	0
T158	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	11062	0	0
T1	13698	41	0	0
T2	581	120	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	42	0	0
T6	573	0	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T33	0	85	0	0
T36	0	189	0	0
T39	0	457	0	0
T78	0	75	0	0
T151	0	77	0	0
T158	0	41	0	0
T182	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	30	0	0
T5	943	1	0	0
T6	573	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T50	425	0	0	0
T51	502	0	0	0
T52	525	0	0	0
T53	404	0	0	0
T83	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T153	0	1	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T11,T32,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T11,T32,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T11,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T34,T35
1	0	Covered	T1,T4,T12
1	1	Covered	T11,T32,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T32,T33
0	1	Covered	T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T32,T33
0	1	Covered	T36,T153,T147
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T32,T33
1	-	Covered	T36,T153,T147

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T32,T40
DetectSt	168	Covered	T11,T32,T33
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T11,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T32,T33
DebounceSt->IdleSt	163	Covered	T40,T193,T77
DetectSt->IdleSt	186	Covered	T180
DetectSt->StableSt	191	Covered	T11,T32,T33
IdleSt->DebounceSt	148	Covered	T11,T32,T40
StableSt->IdleSt	206	Covered	T11,T36,T83

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T32,T40
0	1	Covered	T11,T32,T40
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T32,T33
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T32,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T32,T40
DetectSt	-	-	-	-	1	-	-	Covered	T180
DetectSt	-	-	-	-	0	1	-	Covered	T11,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T55,T153
StableSt	-	-	-	-	-	-	0	Covered	T11,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	67	0	0
CntIncr_A	7341965	80419	0	0
CntNoWrap_A	7341965	6708285	0	0
DetectStDropOut_A	7341965	1	0	0
DetectedOut_A	7341965	21797	0	0
DetectedPulseOut_A	7341965	31	0	0
DisabledIdleSt_A	7341965	6481658	0	0
DisabledNoDetection_A	7341965	6483889	0	0
EnterDebounceSt_A	7341965	35	0	0
EnterDetectSt_A	7341965	32	0	0
EnterStableSt_A	7341965	31	0	0
PulseIsPulse_A	7341965	31	0	0
StayInStableSt	7341965	21747	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7341965	6727	0	0
gen_low_level_sva.LowLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	67	0	0
T11	2062	2	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	9517	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	2	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	2	0	0
T141	0	2	0	0
T153	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	80419	0	0
T11	2062	25	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	56	0	0
T33	0	42	0	0
T34	9517	0	0	0
T36	0	76	0	0
T38	0	47	0	0
T40	0	32	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	17	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	89	0	0
T141	0	33	0	0
T153	0	148	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6708285	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1	0	0
T180	669	1	0	0
T183	422	0	0	0
T184	17720	0	0	0
T185	29490	0	0	0
T186	527	0	0	0
T187	688	0	0	0
T188	524	0	0	0
T189	811	0	0	0
T190	53265	0	0	0
T191	34465	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	21797	0	0
T11	2062	41	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	42	0	0
T33	0	186	0	0
T34	9517	0	0	0
T36	0	43	0	0
T38	0	118	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	19	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	41	0	0
T141	0	79	0	0
T153	0	210	0	0
T221	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	31	0	0
T11	2062	1	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	9517	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	1	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	1	0	0
T141	0	1	0	0
T153	0	2	0	0
T221	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6481658	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6483889	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	35	0	0
T11	2062	1	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	9517	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	1	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	1	0	0
T141	0	1	0	0
T153	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	32	0	0
T11	2062	1	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	9517	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	1	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	1	0	0
T141	0	1	0	0
T153	0	2	0	0
T221	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	31	0	0
T11	2062	1	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	9517	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	1	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	1	0	0
T141	0	1	0	0
T153	0	2	0	0
T221	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	31	0	0
T11	2062	1	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	9517	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	1	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	1	0	0
T141	0	1	0	0
T153	0	2	0	0
T221	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	21747	0	0
T11	2062	39	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T32	0	40	0	0
T33	0	184	0	0
T34	9517	0	0	0
T36	0	42	0	0
T38	0	116	0	0
T41	16413	0	0	0
T42	33931	0	0	0
T55	0	18	0	0
T57	786	0	0	0
T59	488	0	0	0
T64	522	0	0	0
T83	0	39	0	0
T141	0	77	0	0
T153	0	207	0	0
T221	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6727	0	0
T1	13698	16	0	0
T2	581	0	0	0
T3	1030	7	0	0
T4	510	7	0	0
T5	943	2	0	0
T6	573	1	0	0
T12	17295	31	0	0
T13	409	0	0	0
T14	420	2	0	0
T15	407	0	0	0
T21	0	22	0	0
T50	0	1	0	0
T51	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	11	0	0
T36	1114	1	0	0
T58	1058	0	0	0
T68	12918	0	0	0
T71	92874	0	0	0
T72	85022	0	0	0
T73	896	0	0	0
T87	18716	0	0	0
T127	0	1	0	0
T136	31600	0	0	0
T137	681	0	0	0
T147	0	1	0	0
T153	0	1	0	0
T165	421	0	0	0
T169	0	1	0	0
T180	0	1	0	0
T218	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0
T224	0	1	0	0