Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T8,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T8,T26
1	0	Covered	T12,T8,T26
1	1	Covered	T12,T8,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T26
0	1	Covered	T41,T66,T68
1	0	Covered	T41,T68,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T26
0	1	Covered	T12,T8,T26
1	0	Covered	T41,T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T8,T26
1	-	Covered	T12,T8,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T8,T26
DetectSt	168	Covered	T12,T8,T26
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T12,T8,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T8,T26
DebounceSt->IdleSt	163	Covered	T55,T77
DetectSt->IdleSt	186	Covered	T41,T66,T68
DetectSt->StableSt	191	Covered	T12,T8,T26
IdleSt->DebounceSt	148	Covered	T12,T8,T26
StableSt->IdleSt	206	Covered	T12,T8,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T8,T26
0	1	Covered	T12,T8,T26
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T8,T26
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T8,T26
IdleSt	0	-	-	-	-	-	-	Covered	T12,T8,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T8,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T8,T26
DetectSt	-	-	-	-	1	-	-	Covered	T41,T66,T68
DetectSt	-	-	-	-	0	1	-	Covered	T12,T8,T26
DetectSt	-	-	-	-	0	0	-	Covered	T12,T8,T26
StableSt	-	-	-	-	-	-	1	Covered	T12,T8,T26
StableSt	-	-	-	-	-	-	0	Covered	T12,T8,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	3042	0	0
CntIncr_A	7341965	111607	0	0
CntNoWrap_A	7341965	6705310	0	0
DetectStDropOut_A	7341965	394	0	0
DetectedOut_A	7341965	95858	0	0
DetectedPulseOut_A	7341965	943	0	0
DisabledIdleSt_A	7341965	6207361	0	0
DisabledNoDetection_A	7341965	6209436	0	0
EnterDebounceSt_A	7341965	1524	0	0
EnterDetectSt_A	7341965	1519	0	0
EnterStableSt_A	7341965	943	0	0
PulseIsPulse_A	7341965	943	0	0
StayInStableSt	7341965	94794	0	0
gen_high_event_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	814	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	3042	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	20	0	0
T12	17295	20	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	34	0	0
T31	0	32	0	0
T41	0	52	0	0
T44	0	14	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	46	0	0
T67	0	32	0	0
T68	0	58	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	111607	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	500	0	0
T12	17295	850	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	6307	0	0
T31	0	752	0	0
T41	0	1212	0	0
T44	0	504	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	1882	0	0
T67	0	1376	0	0
T68	0	1676	0	0
T69	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6705310	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16868	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	394	0	0
T20	2303	0	0	0
T41	16413	5	0	0
T43	629	0	0	0
T55	0	1	0	0
T60	491	0	0	0
T66	0	23	0	0
T68	0	4	0	0
T70	0	16	0	0
T88	0	21	0	0
T89	0	13	0	0
T90	0	28	0	0
T94	0	14	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T132	423	0	0	0
T143	412	0	0	0
T144	427	0	0	0
T225	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	95858	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	640	0	0
T12	17295	1223	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	1760	0	0
T31	0	1003	0	0
T41	0	7	0	0
T44	0	238	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	1073	0	0
T69	0	44	0	0
T226	0	2284	0	0
T227	0	1355	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	943	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	10	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	16	0	0
T41	0	7	0	0
T44	0	7	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	16	0	0
T69	0	1	0	0
T226	0	26	0	0
T227	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6207361	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	9230	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6209436	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	9231	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1524	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	10	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	16	0	0
T41	0	26	0	0
T44	0	7	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	23	0	0
T67	0	16	0	0
T68	0	29	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1519	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	10	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	16	0	0
T41	0	26	0	0
T44	0	7	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	23	0	0
T67	0	16	0	0
T68	0	29	0	0
T69	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	943	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	10	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	16	0	0
T41	0	7	0	0
T44	0	7	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	16	0	0
T69	0	1	0	0
T226	0	26	0	0
T227	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	943	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	10	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	16	0	0
T41	0	7	0	0
T44	0	7	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	16	0	0
T69	0	1	0	0
T226	0	26	0	0
T227	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	94794	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	626	0	0
T12	17295	1211	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	1742	0	0
T31	0	985	0	0
T44	0	230	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	1057	0	0
T69	0	42	0	0
T119	0	396	0	0
T226	0	2256	0	0
T227	0	1330	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	814	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	6	0	0
T12	17295	8	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	16	0	0
T31	0	14	0	0
T44	0	6	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	16	0	0
T119	0	11	0	0
T226	0	24	0	0
T227	0	23	0	0
T228	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T7
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T12,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T12,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T12,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Covered	T1,T12,T21
1	1	Covered	T1,T12,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T7
0	1	Covered	T9,T76,T30
1	0	Covered	T55,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T7
0	1	Covered	T1,T7,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T7
1	-	Covered	T1,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T7
DetectSt	168	Covered	T1,T12,T7
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T12,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T7
DebounceSt->IdleSt	163	Covered	T1,T42,T45
DetectSt->IdleSt	186	Covered	T9,T76,T30
DetectSt->StableSt	191	Covered	T1,T12,T7
IdleSt->DebounceSt	148	Covered	T1,T12,T7
StableSt->IdleSt	206	Covered	T1,T12,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T7
0	1	Covered	T1,T12,T7
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T7
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T42,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T7
DetectSt	-	-	-	-	1	-	-	Covered	T9,T76,T30
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	1037	0	0
CntIncr_A	7341965	52703	0	0
CntNoWrap_A	7341965	6707315	0	0
DetectStDropOut_A	7341965	82	0	0
DetectedOut_A	7341965	21281	0	0
DetectedPulseOut_A	7341965	395	0	0
DisabledIdleSt_A	7341965	6316338	0	0
DisabledNoDetection_A	7341965	6317904	0	0
EnterDebounceSt_A	7341965	559	0	0
EnterDetectSt_A	7341965	480	0	0
EnterStableSt_A	7341965	395	0	0
PulseIsPulse_A	7341965	395	0	0
StayInStableSt	7341965	20840	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	348	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1037	0	0
T1	13698	9	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	2	0	0
T8	0	8	0	0
T9	0	2	0	0
T10	0	6	0	0
T12	17295	4	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	2	0	0
T34	0	6	0	0
T42	0	13	0	0
T44	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	52703	0	0
T1	13698	246	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	122	0	0
T8	0	152	0	0
T9	0	98	0	0
T10	0	312	0	0
T12	17295	148	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	218	0	0
T34	0	197	0	0
T42	0	628	0	0
T44	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6707315	0	0
T1	13698	10056	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16884	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	82	0	0
T9	31921	1	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T26	32073	0	0	0
T30	0	6	0	0
T42	33931	0	0	0
T57	786	0	0	0
T63	526	0	0	0
T64	522	0	0	0
T71	0	4	0	0
T72	0	3	0	0
T76	0	3	0	0
T81	0	5	0	0
T87	0	7	0	0
T91	0	4	0	0
T92	0	8	0	0
T96	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	21281	0	0
T1	13698	97	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	57	0	0
T8	0	270	0	0
T10	0	262	0	0
T12	17295	130	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	53	0	0
T34	0	114	0	0
T42	0	165	0	0
T44	0	32	0	0
T106	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	395	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	1	0	0
T8	0	4	0	0
T10	0	3	0	0
T12	17295	2	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	1	0	0
T34	0	3	0	0
T42	0	6	0	0
T44	0	1	0	0
T106	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6316338	0	0
T1	13698	8032	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	15667	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6317904	0	0
T1	13698	8037	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	15669	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	559	0	0
T1	13698	5	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	1	0	0
T8	0	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T12	17295	2	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	1	0	0
T34	0	3	0	0
T42	0	7	0	0
T44	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	480	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	1	0	0
T8	0	4	0	0
T9	0	1	0	0
T10	0	3	0	0
T12	17295	2	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	1	0	0
T34	0	3	0	0
T42	0	6	0	0
T44	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	395	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	1	0	0
T8	0	4	0	0
T10	0	3	0	0
T12	17295	2	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	1	0	0
T34	0	3	0	0
T42	0	6	0	0
T44	0	1	0	0
T106	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	395	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	1	0	0
T8	0	4	0	0
T10	0	3	0	0
T12	17295	2	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	1	0	0
T34	0	3	0	0
T42	0	6	0	0
T44	0	1	0	0
T106	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	20840	0	0
T1	13698	93	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	56	0	0
T8	0	266	0	0
T10	0	259	0	0
T12	17295	126	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	51	0	0
T34	0	110	0	0
T42	0	159	0	0
T44	0	30	0	0
T106	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	348	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	1	0	0
T8	0	4	0	0
T10	0	3	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T34	0	2	0	0
T42	0	6	0	0
T106	0	8	0	0
T107	0	1	0	0
T108	0	3	0	0
T109	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T8,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T8,T26
1	0	Covered	T12,T8,T26
1	1	Covered	T12,T8,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T26
0	1	Covered	T12,T66,T68
1	0	Covered	T12,T68,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T41
0	1	Covered	T8,T26,T41
1	0	Covered	T77,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T26,T41
1	-	Covered	T8,T26,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T8,T26
DetectSt	168	Covered	T12,T8,T26
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T26,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T8,T26
DebounceSt->IdleSt	163	Covered	T55,T77
DetectSt->IdleSt	186	Covered	T12,T66,T68
DetectSt->StableSt	191	Covered	T8,T26,T41
IdleSt->DebounceSt	148	Covered	T12,T8,T26
StableSt->IdleSt	206	Covered	T8,T26,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T8,T26
0	1	Covered	T12,T8,T26
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T8,T26
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T8,T26
IdleSt	0	-	-	-	-	-	-	Covered	T12,T8,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T8,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T8,T26
DetectSt	-	-	-	-	1	-	-	Covered	T12,T66,T68
DetectSt	-	-	-	-	0	1	-	Covered	T8,T26,T41
DetectSt	-	-	-	-	0	0	-	Covered	T12,T8,T26
StableSt	-	-	-	-	-	-	1	Covered	T8,T26,T41
StableSt	-	-	-	-	-	-	0	Covered	T8,T26,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	3005	0	0
CntIncr_A	7341965	102253	0	0
CntNoWrap_A	7341965	6705347	0	0
DetectStDropOut_A	7341965	391	0	0
DetectedOut_A	7341965	94906	0	0
DetectedPulseOut_A	7341965	928	0	0
DisabledIdleSt_A	7341965	6203190	0	0
DisabledNoDetection_A	7341965	6205248	0	0
EnterDebounceSt_A	7341965	1505	0	0
EnterDetectSt_A	7341965	1500	0	0
EnterStableSt_A	7341965	928	0	0
PulseIsPulse_A	7341965	928	0	0
StayInStableSt	7341965	93838	0	0
gen_high_event_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	786	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	3005	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	32	0	0
T12	17295	16	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	20	0	0
T31	0	26	0	0
T41	0	48	0	0
T44	0	12	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	26	0	0
T67	0	24	0	0
T68	0	32	0	0
T70	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	102253	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	784	0	0
T12	17295	1066	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	2400	0	0
T31	0	767	0	0
T41	0	696	0	0
T44	0	498	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	1059	0	0
T67	0	912	0	0
T68	0	920	0	0
T70	0	339	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6705347	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16872	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	391	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T12	17295	3	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T50	425	0	0	0
T51	502	0	0	0
T55	0	1	0	0
T66	0	13	0	0
T68	0	1	0	0
T70	0	1	0	0
T88	0	26	0	0
T90	0	28	0	0
T194	0	1	0	0
T227	0	2	0	0
T229	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	94906	0	0
T8	21411	1478	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	2020	0	0
T31	0	35	0	0
T41	0	1509	0	0
T44	0	716	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	994	0	0
T119	0	1499	0	0
T226	0	8130	0	0
T228	0	371	0	0
T230	0	358	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	928	0	0
T8	21411	16	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	10	0	0
T31	0	13	0	0
T41	0	24	0	0
T44	0	6	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	12	0	0
T119	0	23	0	0
T226	0	29	0	0
T228	0	8	0	0
T230	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6203190	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	9980	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6205248	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	9983	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1505	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	16	0	0
T12	17295	8	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	10	0	0
T31	0	13	0	0
T41	0	24	0	0
T44	0	6	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	13	0	0
T67	0	12	0	0
T68	0	16	0	0
T70	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1500	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	16	0	0
T12	17295	8	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	10	0	0
T31	0	13	0	0
T41	0	24	0	0
T44	0	6	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	13	0	0
T67	0	12	0	0
T68	0	16	0	0
T70	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	928	0	0
T8	21411	16	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	10	0	0
T31	0	13	0	0
T41	0	24	0	0
T44	0	6	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	12	0	0
T119	0	23	0	0
T226	0	29	0	0
T228	0	8	0	0
T230	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	928	0	0
T8	21411	16	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	10	0	0
T31	0	13	0	0
T41	0	24	0	0
T44	0	6	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	12	0	0
T119	0	23	0	0
T226	0	29	0	0
T228	0	8	0	0
T230	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	93838	0	0
T8	21411	1455	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	2010	0	0
T31	0	22	0	0
T41	0	1480	0	0
T44	0	710	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	981	0	0
T119	0	1475	0	0
T226	0	8093	0	0
T228	0	362	0	0
T230	0	342	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	786	0	0
T8	21411	9	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	10	0	0
T31	0	13	0	0
T41	0	19	0	0
T44	0	6	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	11	0	0
T119	0	22	0	0
T226	0	21	0	0
T228	0	7	0	0
T230	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T7
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T12,T21
1	1	Covered	T1,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T106,T108,T87
1	0	Covered	T55,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T8
1	-	Covered	T1,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T8
DetectSt	168	Covered	T1,T7,T8
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T8
DebounceSt->IdleSt	163	Covered	T9,T76,T30
DetectSt->IdleSt	186	Covered	T106,T108,T87
DetectSt->StableSt	191	Covered	T1,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T7,T8
StableSt->IdleSt	206	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T76,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T106,T108,T87
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	831	0	0
CntIncr_A	7341965	40625	0	0
CntNoWrap_A	7341965	6707521	0	0
DetectStDropOut_A	7341965	72	0	0
DetectedOut_A	7341965	19468	0	0
DetectedPulseOut_A	7341965	319	0	0
DisabledIdleSt_A	7341965	6330814	0	0
DisabledNoDetection_A	7341965	6332413	0	0
EnterDebounceSt_A	7341965	437	0	0
EnterDetectSt_A	7341965	396	0	0
EnterStableSt_A	7341965	319	0	0
PulseIsPulse_A	7341965	319	0	0
StayInStableSt	7341965	19109	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	279	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	831	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	8	0	0
T8	0	14	0	0
T9	0	27	0	0
T10	0	2	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T41	0	10	0	0
T42	0	14	0	0
T44	0	4	0	0
T76	0	1	0	0
T106	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	40625	0	0
T1	13698	114	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	392	0	0
T8	0	315	0	0
T9	0	1299	0	0
T10	0	187	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T41	0	165	0	0
T42	0	609	0	0
T44	0	130	0	0
T76	0	65	0	0
T106	0	518	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6707521	0	0
T1	13698	10061	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	72	0	0
T30	27192	0	0	0
T31	11075	0	0	0
T47	684	0	0	0
T48	54057	0	0	0
T67	19548	0	0	0
T81	0	11	0	0
T87	0	4	0	0
T106	24050	4	0	0
T107	26591	0	0	0
T108	12214	6	0	0
T140	0	5	0	0
T199	0	9	0	0
T231	0	1	0	0
T232	0	3	0	0
T233	0	4	0	0
T234	0	1	0	0
T235	449	0	0	0
T236	521	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	19468	0	0
T1	13698	82	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	327	0	0
T8	0	426	0	0
T9	0	68	0	0
T10	0	4	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T30	0	287	0	0
T41	0	246	0	0
T42	0	229	0	0
T44	0	51	0	0
T107	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	319	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	7	0	0
T9	0	13	0	0
T10	0	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T30	0	10	0	0
T41	0	5	0	0
T42	0	7	0	0
T44	0	2	0	0
T107	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6330814	0	0
T1	13698	8152	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6332413	0	0
T1	13698	8159	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	437	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	7	0	0
T9	0	14	0	0
T10	0	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T41	0	5	0	0
T42	0	7	0	0
T44	0	2	0	0
T76	0	1	0	0
T106	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	396	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	7	0	0
T9	0	13	0	0
T10	0	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T30	0	10	0	0
T41	0	5	0	0
T42	0	7	0	0
T44	0	2	0	0
T106	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	319	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	7	0	0
T9	0	13	0	0
T10	0	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T30	0	10	0	0
T41	0	5	0	0
T42	0	7	0	0
T44	0	2	0	0
T107	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	319	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	7	0	0
T9	0	13	0	0
T10	0	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T30	0	10	0	0
T41	0	5	0	0
T42	0	7	0	0
T44	0	2	0	0
T107	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	19109	0	0
T1	13698	80	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	323	0	0
T8	0	419	0	0
T9	0	55	0	0
T10	0	3	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T30	0	277	0	0
T41	0	236	0	0
T42	0	222	0	0
T44	0	49	0	0
T107	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	279	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	7	0	0
T9	0	13	0	0
T10	0	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T30	0	10	0	0
T42	0	7	0	0
T44	0	2	0	0
T107	0	3	0	0
T109	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T8,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T8,T26
1	0	Covered	T12,T8,T26
1	1	Covered	T12,T8,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T26
0	1	Covered	T66,T227,T88
1	0	Covered	T12,T227,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T41
0	1	Covered	T8,T26,T41
1	0	Covered	T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T26,T41
1	-	Covered	T8,T26,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T8,T26
DetectSt	168	Covered	T12,T8,T26
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T26,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T8,T26
DebounceSt->IdleSt	163	Covered	T55,T77
DetectSt->IdleSt	186	Covered	T12,T66,T227
DetectSt->StableSt	191	Covered	T8,T26,T41
IdleSt->DebounceSt	148	Covered	T12,T8,T26
StableSt->IdleSt	206	Covered	T8,T26,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T8,T26
0	1	Covered	T12,T8,T26
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T8,T26
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T8,T26
IdleSt	0	-	-	-	-	-	-	Covered	T12,T8,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T8,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T8,T26
DetectSt	-	-	-	-	1	-	-	Covered	T12,T66,T227
DetectSt	-	-	-	-	0	1	-	Covered	T8,T26,T41
DetectSt	-	-	-	-	0	0	-	Covered	T12,T8,T26
StableSt	-	-	-	-	-	-	1	Covered	T8,T26,T41
StableSt	-	-	-	-	-	-	0	Covered	T8,T26,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	2854	0	0
CntIncr_A	7341965	99321	0	0
CntNoWrap_A	7341965	6705498	0	0
DetectStDropOut_A	7341965	364	0	0
DetectedOut_A	7341965	84084	0	0
DetectedPulseOut_A	7341965	902	0	0
DisabledIdleSt_A	7341965	6214221	0	0
DisabledNoDetection_A	7341965	6216290	0	0
EnterDebounceSt_A	7341965	1429	0	0
EnterDetectSt_A	7341965	1425	0	0
EnterStableSt_A	7341965	902	0	0
PulseIsPulse_A	7341965	902	0	0
StayInStableSt	7341965	83055	0	0
gen_high_event_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	774	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	2854	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	12	0	0
T12	17295	8	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	54	0	0
T31	0	52	0	0
T41	0	34	0	0
T44	0	14	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	58	0	0
T67	0	42	0	0
T68	0	34	0	0
T70	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	99321	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	294	0	0
T12	17295	532	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	6480	0	0
T31	0	1170	0	0
T41	0	612	0	0
T44	0	511	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	2381	0	0
T67	0	1554	0	0
T68	0	799	0	0
T70	0	322	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6705498	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16880	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	364	0	0
T30	27192	0	0	0
T32	580	0	0	0
T35	489	0	0	0
T46	645	0	0	0
T55	0	1	0	0
T56	924	0	0	0
T66	6729	29	0	0
T76	6551	0	0	0
T88	0	5	0	0
T90	0	28	0	0
T94	0	27	0	0
T106	24050	0	0	0
T225	0	4	0	0
T227	0	4	0	0
T237	0	1	0	0
T238	0	11	0	0
T239	0	1	0	0
T240	426	0	0	0
T241	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	84084	0	0
T8	21411	383	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	8781	0	0
T31	0	1212	0	0
T41	0	1077	0	0
T44	0	231	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	2807	0	0
T68	0	827	0	0
T70	0	902	0	0
T194	0	2226	0	0
T229	0	2001	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	902	0	0
T8	21411	6	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	27	0	0
T31	0	26	0	0
T41	0	17	0	0
T44	0	7	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	21	0	0
T68	0	17	0	0
T70	0	7	0	0
T194	0	28	0	0
T229	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6214221	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	9985	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6216290	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	9988	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1429	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	6	0	0
T12	17295	4	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	27	0	0
T31	0	26	0	0
T41	0	17	0	0
T44	0	7	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	29	0	0
T67	0	21	0	0
T68	0	17	0	0
T70	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1425	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	6	0	0
T12	17295	4	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	27	0	0
T31	0	26	0	0
T41	0	17	0	0
T44	0	7	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	29	0	0
T67	0	21	0	0
T68	0	17	0	0
T70	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	902	0	0
T8	21411	6	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	27	0	0
T31	0	26	0	0
T41	0	17	0	0
T44	0	7	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	21	0	0
T68	0	17	0	0
T70	0	7	0	0
T194	0	28	0	0
T229	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	902	0	0
T8	21411	6	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	27	0	0
T31	0	26	0	0
T41	0	17	0	0
T44	0	7	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	21	0	0
T68	0	17	0	0
T70	0	7	0	0
T194	0	28	0	0
T229	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	83055	0	0
T8	21411	375	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	8752	0	0
T31	0	1184	0	0
T41	0	1058	0	0
T44	0	223	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	2783	0	0
T68	0	808	0	0
T70	0	893	0	0
T194	0	2191	0	0
T229	0	1985	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	774	0	0
T8	21411	4	0	0
T9	31921	0	0	0
T10	19546	0	0	0
T11	2062	0	0	0
T19	838	0	0	0
T23	495	0	0	0
T25	635	0	0	0
T26	32073	25	0	0
T31	0	24	0	0
T41	0	15	0	0
T44	0	6	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	18	0	0
T68	0	15	0	0
T70	0	5	0	0
T194	0	21	0	0
T229	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T7
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T12,T21
1	1	Covered	T1,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T42,T71,T92
1	0	Covered	T55,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
1	0	Covered	T26

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T9
1	-	Covered	T1,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T9
DetectSt	168	Covered	T1,T7,T9
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T9
DebounceSt->IdleSt	163	Covered	T10,T42,T76
DetectSt->IdleSt	186	Covered	T42,T71,T55
DetectSt->StableSt	191	Covered	T1,T7,T9
IdleSt->DebounceSt	148	Covered	T1,T7,T9
StableSt->IdleSt	206	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T42,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T42,T71,T55
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	809	0	0
CntIncr_A	7341965	45355	0	0
CntNoWrap_A	7341965	6707543	0	0
DetectStDropOut_A	7341965	27	0	0
DetectedOut_A	7341965	15209	0	0
DetectedPulseOut_A	7341965	354	0	0
DisabledIdleSt_A	7341965	6338551	0	0
DisabledNoDetection_A	7341965	6340169	0	0
EnterDebounceSt_A	7341965	425	0	0
EnterDetectSt_A	7341965	386	0	0
EnterStableSt_A	7341965	354	0	0
PulseIsPulse_A	7341965	354	0	0
StayInStableSt	7341965	14823	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	318	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	809	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	6	0	0
T9	0	6	0	0
T10	0	12	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	8	0	0
T41	0	4	0	0
T42	0	13	0	0
T44	0	2	0	0
T76	0	3	0	0
T106	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	45355	0	0
T1	13698	188	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	474	0	0
T9	0	282	0	0
T10	0	1004	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	812	0	0
T41	0	72	0	0
T42	0	793	0	0
T44	0	62	0	0
T76	0	202	0	0
T106	0	318	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6707543	0	0
T1	13698	10061	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	27	0	0
T20	2303	0	0	0
T34	9517	0	0	0
T41	16413	0	0	0
T42	33931	6	0	0
T43	629	0	0	0
T59	488	0	0	0
T60	491	0	0	0
T71	0	3	0	0
T92	0	2	0	0
T129	402	0	0	0
T143	412	0	0	0
T144	427	0	0	0
T242	0	1	0	0
T243	0	4	0	0
T244	0	1	0	0
T245	0	2	0	0
T246	0	3	0	0
T247	0	3	0	0
T248	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	15209	0	0
T1	13698	8	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	64	0	0
T9	0	12	0	0
T10	0	138	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	276	0	0
T30	0	16	0	0
T41	0	93	0	0
T44	0	27	0	0
T76	0	5	0	0
T106	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	354	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	3	0	0
T9	0	3	0	0
T10	0	4	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	4	0	0
T30	0	3	0	0
T41	0	2	0	0
T44	0	1	0	0
T76	0	1	0	0
T106	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6338551	0	0
T1	13698	8152	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16888	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6340169	0	0
T1	13698	8159	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	425	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	3	0	0
T9	0	3	0	0
T10	0	8	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	4	0	0
T41	0	2	0	0
T42	0	7	0	0
T44	0	1	0	0
T76	0	2	0	0
T106	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	386	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	3	0	0
T9	0	3	0	0
T10	0	4	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	4	0	0
T41	0	2	0	0
T42	0	6	0	0
T44	0	1	0	0
T76	0	1	0	0
T106	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	354	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	3	0	0
T9	0	3	0	0
T10	0	4	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	4	0	0
T30	0	3	0	0
T41	0	2	0	0
T44	0	1	0	0
T76	0	1	0	0
T106	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	354	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	3	0	0
T9	0	3	0	0
T10	0	4	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	4	0	0
T30	0	3	0	0
T41	0	2	0	0
T44	0	1	0	0
T76	0	1	0	0
T106	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	14823	0	0
T1	13698	6	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	61	0	0
T9	0	9	0	0
T10	0	134	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	270	0	0
T30	0	13	0	0
T41	0	89	0	0
T44	0	25	0	0
T76	0	4	0	0
T106	0	66	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	318	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	3	0	0
T9	0	3	0	0
T10	0	4	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	1	0	0
T30	0	3	0	0
T31	0	2	0	0
T76	0	1	0	0
T106	0	3	0	0
T107	0	8	0	0