Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T8,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T12,T8,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T8,T26
1	0	Covered	T12,T8,T26
1	1	Covered	T12,T8,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T26
0	1	Covered	T41,T66,T70
1	0	Covered	T41,T70,T194

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T8,T26
0	1	Covered	T12,T8,T26
1	0	Covered	T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T8,T26
1	-	Covered	T12,T8,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T8,T26
DetectSt	168	Covered	T12,T8,T26
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T12,T8,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T8,T26
DebounceSt->IdleSt	163	Covered	T55,T77
DetectSt->IdleSt	186	Covered	T41,T66,T70
DetectSt->StableSt	191	Covered	T12,T8,T26
IdleSt->DebounceSt	148	Covered	T12,T8,T26
StableSt->IdleSt	206	Covered	T12,T8,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T8,T26
0	1	Covered	T12,T8,T26
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T8,T26
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T12,T8,T26
IdleSt	0	-	-	-	-	-	-	Covered	T12,T8,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T8,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T8,T26
DetectSt	-	-	-	-	1	-	-	Covered	T41,T66,T70
DetectSt	-	-	-	-	0	1	-	Covered	T12,T8,T26
DetectSt	-	-	-	-	0	0	-	Covered	T12,T8,T26
StableSt	-	-	-	-	-	-	1	Covered	T12,T8,T26
StableSt	-	-	-	-	-	-	0	Covered	T12,T8,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	3066	0	0
CntIncr_A	7341965	110492	0	0
CntNoWrap_A	7341965	6705286	0	0
DetectStDropOut_A	7341965	439	0	0
DetectedOut_A	7341965	83977	0	0
DetectedPulseOut_A	7341965	875	0	0
DisabledIdleSt_A	7341965	6220660	0	0
DisabledNoDetection_A	7341965	6222748	0	0
EnterDebounceSt_A	7341965	1535	0	0
EnterDetectSt_A	7341965	1531	0	0
EnterStableSt_A	7341965	875	0	0
PulseIsPulse_A	7341965	875	0	0
StayInStableSt	7341965	82994	0	0
gen_high_event_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	766	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	3066	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	24	0	0
T12	17295	20	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	34	0	0
T31	0	58	0	0
T41	0	30	0	0
T44	0	30	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	46	0	0
T67	0	42	0	0
T68	0	38	0	0
T70	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	110492	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	396	0	0
T12	17295	710	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	3876	0	0
T31	0	1160	0	0
T41	0	695	0	0
T44	0	810	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	1882	0	0
T67	0	1680	0	0
T68	0	703	0	0
T70	0	1513	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6705286	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16868	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	439	0	0
T20	2303	0	0	0
T41	16413	5	0	0
T43	629	0	0	0
T55	0	1	0	0
T60	491	0	0	0
T66	0	23	0	0
T70	0	25	0	0
T88	0	7	0	0
T90	0	18	0	0
T94	0	8	0	0
T129	402	0	0	0
T130	422	0	0	0
T131	424	0	0	0
T132	423	0	0	0
T143	412	0	0	0
T144	427	0	0	0
T194	0	8	0	0
T229	0	3	0	0
T249	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	83977	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	1165	0	0
T12	17295	1945	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	5017	0	0
T31	0	1173	0	0
T44	0	1408	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	2072	0	0
T68	0	1429	0	0
T89	0	2056	0	0
T226	0	1722	0	0
T227	0	347	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	875	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	12	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	29	0	0
T44	0	15	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	21	0	0
T68	0	19	0	0
T89	0	22	0	0
T226	0	14	0	0
T227	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6220660	0	0
T1	13698	10065	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	8658	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6222748	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	8659	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1535	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	12	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	29	0	0
T41	0	15	0	0
T44	0	15	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	23	0	0
T67	0	21	0	0
T68	0	19	0	0
T70	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	1531	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	12	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	29	0	0
T41	0	15	0	0
T44	0	15	0	0
T50	425	0	0	0
T51	502	0	0	0
T66	0	23	0	0
T67	0	21	0	0
T68	0	19	0	0
T70	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	875	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	12	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	29	0	0
T44	0	15	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	21	0	0
T68	0	19	0	0
T89	0	22	0	0
T226	0	14	0	0
T227	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	875	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	12	0	0
T12	17295	10	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	17	0	0
T31	0	29	0	0
T44	0	15	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	21	0	0
T68	0	19	0	0
T89	0	22	0	0
T226	0	14	0	0
T227	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	82994	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	1151	0	0
T12	17295	1933	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	4998	0	0
T31	0	1144	0	0
T44	0	1387	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	2048	0	0
T68	0	1408	0	0
T89	0	2033	0	0
T226	0	1706	0	0
T227	0	336	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	766	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T8	0	10	0	0
T12	17295	8	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	15	0	0
T31	0	29	0	0
T44	0	9	0	0
T50	425	0	0	0
T51	502	0	0	0
T67	0	18	0	0
T68	0	17	0	0
T89	0	21	0	0
T226	0	12	0	0
T227	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T12,T7
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T12,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T12,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T12,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Covered	T1,T12,T21
1	1	Covered	T1,T12,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T7
0	1	Covered	T1,T9,T76
1	0	Covered	T55,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T7,T8
0	1	Covered	T7,T8,T10
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T7,T8
1	-	Covered	T7,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T7
DetectSt	168	Covered	T1,T12,T7
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T12,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T7
DebounceSt->IdleSt	163	Covered	T10,T42,T76
DetectSt->IdleSt	186	Covered	T1,T9,T76
DetectSt->StableSt	191	Covered	T12,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T12,T7
StableSt->IdleSt	206	Covered	T12,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T7
0	1	Covered	T1,T12,T7
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T7
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T42,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T7
DetectSt	-	-	-	-	1	-	-	Covered	T1,T9,T76
DetectSt	-	-	-	-	0	1	-	Covered	T12,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T12,T7
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T12,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7341965	835	0	0
CntIncr_A	7341965	46904	0	0
CntNoWrap_A	7341965	6707517	0	0
DetectStDropOut_A	7341965	56	0	0
DetectedOut_A	7341965	15120	0	0
DetectedPulseOut_A	7341965	333	0	0
DisabledIdleSt_A	7341965	6336606	0	0
DisabledNoDetection_A	7341965	6338238	0	0
EnterDebounceSt_A	7341965	443	0	0
EnterDetectSt_A	7341965	394	0	0
EnterStableSt_A	7341965	333	0	0
PulseIsPulse_A	7341965	333	0	0
StayInStableSt	7341965	14747	0	0
gen_high_level_sva.HighLevelEvent_A	7341965	6710637	0	0
gen_not_sticky_sva.StableStDropOut_A	7341965	291	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	835	0	0
T1	13698	4	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	8	0	0
T8	0	4	0	0
T9	0	2	0	0
T10	0	5	0	0
T12	17295	2	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	4	0	0
T42	0	17	0	0
T44	0	12	0	0
T76	0	27	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	46904	0	0
T1	13698	196	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	448	0	0
T8	0	80	0	0
T9	0	98	0	0
T10	0	422	0	0
T12	17295	99	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	450	0	0
T42	0	916	0	0
T44	0	462	0	0
T76	0	1928	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6707517	0	0
T1	13698	10061	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	16886	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	56	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T9	0	1	0	0
T12	17295	0	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T76	0	13	0	0
T199	0	1	0	0
T200	0	7	0	0
T250	0	1	0	0
T251	0	3	0	0
T252	0	6	0	0
T253	0	5	0	0
T254	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	15120	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	271	0	0
T8	0	131	0	0
T10	0	54	0	0
T12	17295	41	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	93	0	0
T30	0	48	0	0
T31	0	53	0	0
T42	0	122	0	0
T44	0	75	0	0
T50	425	0	0	0
T51	502	0	0	0
T106	0	183	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	333	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	2	0	0
T10	0	2	0	0
T12	17295	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T42	0	8	0	0
T44	0	6	0	0
T50	425	0	0	0
T51	502	0	0	0
T106	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6336606	0	0
T1	13698	8152	0	0
T2	581	180	0	0
T3	1030	629	0	0
T4	510	109	0	0
T5	943	542	0	0
T6	573	172	0	0
T12	17295	14944	0	0
T13	409	8	0	0
T14	420	19	0	0
T15	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6338238	0	0
T1	13698	8159	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	14946	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	443	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	3	0	0
T12	17295	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	2	0	0
T42	0	9	0	0
T44	0	6	0	0
T76	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	394	0	0
T1	13698	2	0	0
T2	581	0	0	0
T3	1030	0	0	0
T4	510	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T12	17295	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T26	0	2	0	0
T42	0	8	0	0
T44	0	6	0	0
T76	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	333	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	2	0	0
T10	0	2	0	0
T12	17295	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T42	0	8	0	0
T44	0	6	0	0
T50	425	0	0	0
T51	502	0	0	0
T106	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	333	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	4	0	0
T8	0	2	0	0
T10	0	2	0	0
T12	17295	1	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T42	0	8	0	0
T44	0	6	0	0
T50	425	0	0	0
T51	502	0	0	0
T106	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	14747	0	0
T3	1030	0	0	0
T5	943	0	0	0
T6	573	0	0	0
T7	0	267	0	0
T8	0	129	0	0
T10	0	52	0	0
T12	17295	39	0	0
T13	409	0	0	0
T14	420	0	0	0
T15	407	0	0	0
T21	2980	0	0	0
T26	0	89	0	0
T30	0	46	0	0
T31	0	52	0	0
T42	0	114	0	0
T44	0	63	0	0
T50	425	0	0	0
T51	502	0	0	0
T106	0	180	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	6710637	0	0
T1	13698	10075	0	0
T2	581	181	0	0
T3	1030	630	0	0
T4	510	110	0	0
T5	943	543	0	0
T6	573	173	0	0
T12	17295	16892	0	0
T13	409	9	0	0
T14	420	20	0	0
T15	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7341965	291	0	0
T7	17678	4	0	0
T8	21411	2	0	0
T9	31921	0	0	0
T10	19546	2	0	0
T11	2062	0	0	0
T22	494	0	0	0
T25	635	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T42	0	8	0	0
T54	425	0	0	0
T63	526	0	0	0
T64	522	0	0	0
T67	0	3	0	0
T106	0	3	0	0
T107	0	2	0	0
T109	0	13	0	0