Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1222527726	11362	0	0
auto_block_debounce_ctl_rd_A	1222527726	2268	0	0
auto_block_out_ctl_rd_A	1222527726	3280	0	0
com_det_ctl_0_rd_A	1222527726	4750	0	0
com_det_ctl_1_rd_A	1222527726	4726	0	0
com_det_ctl_2_rd_A	1222527726	4711	0	0
com_det_ctl_3_rd_A	1222527726	4763	0	0
com_out_ctl_0_rd_A	1222527726	5592	0	0
com_out_ctl_1_rd_A	1222527726	5532	0	0
com_out_ctl_2_rd_A	1222527726	5366	0	0
com_out_ctl_3_rd_A	1222527726	5368	0	0
com_pre_det_ctl_0_rd_A	1222527726	1921	0	0
com_pre_det_ctl_1_rd_A	1222527726	1908	0	0
com_pre_det_ctl_2_rd_A	1222527726	2025	0	0
com_pre_det_ctl_3_rd_A	1222527726	1962	0	0
com_pre_sel_ctl_0_rd_A	1222527726	5365	0	0
com_pre_sel_ctl_1_rd_A	1222527726	5762	0	0
com_pre_sel_ctl_2_rd_A	1222527726	5418	0	0
com_pre_sel_ctl_3_rd_A	1222527726	5470	0	0
com_sel_ctl_0_rd_A	1222527726	5818	0	0
com_sel_ctl_1_rd_A	1222527726	5513	0	0
com_sel_ctl_2_rd_A	1222527726	5702	0	0
com_sel_ctl_3_rd_A	1222527726	5527	0	0
ec_rst_ctl_rd_A	1222527726	3007	0	0
intr_enable_rd_A	1222527726	2520	0	0
key_intr_ctl_rd_A	1222527726	4840	0	0
key_intr_debounce_ctl_rd_A	1222527726	2009	0	0
key_invert_ctl_rd_A	1222527726	6369	0	0
pin_allowed_ctl_rd_A	1222527726	6955	0	0
pin_out_ctl_rd_A	1222527726	5520	0	0
pin_out_value_rd_A	1222527726	5192	0	0
regwen_rd_A	1222527726	2204	0	0
ulp_ac_debounce_ctl_rd_A	1222527726	2197	0	0
ulp_ctl_rd_A	1222527726	2185	0	0
ulp_lid_debounce_ctl_rd_A	1222527726	2154	0	0
ulp_pwrb_debounce_ctl_rd_A	1222527726	2126	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	11362	0	0
T1	651520	9	0	0
T2	145344	0	0	0
T3	60716	0	0	0
T4	43386	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	0	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T34	0	4	0	0
T40	0	13	0	0
T45	0	8	0	0
T71	0	4	0	0
T78	0	6	0	0
T83	0	10	0	0
T112	0	9	0	0
T139	0	5	0	0
T158	0	10	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2268	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	3	0	0
T66	437444	0	0	0
T71	0	23	0	0
T83	0	26	0	0
T86	0	6	0	0
T124	0	10	0	0
T136	0	11	0	0
T139	0	25	0	0
T158	0	40	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T281	0	4	0	0
T283	0	18	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	3280	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	16	0	0
T66	437444	0	0	0
T71	0	16	0	0
T83	0	29	0	0
T86	0	6	0	0
T124	0	4	0	0
T136	0	12	0	0
T139	0	10	0	0
T158	0	41	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T281	0	16	0	0
T283	0	23	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	4750	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	19	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	47	0	0
T42	0	39	0	0
T45	0	14	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	54	0	0
T71	0	68	0	0
T72	0	260	0	0
T76	0	46	0	0
T87	0	65	0	0
T106	0	34	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	4726	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	32	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	44	0	0
T42	0	39	0	0
T45	0	11	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	21	0	0
T71	0	82	0	0
T72	0	223	0	0
T76	0	50	0	0
T87	0	74	0	0
T106	0	39	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	4711	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	36	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	33	0	0
T42	0	44	0	0
T45	0	6	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	35	0	0
T71	0	77	0	0
T72	0	276	0	0
T76	0	38	0	0
T87	0	90	0	0
T106	0	37	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	4763	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	19	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	61	0	0
T42	0	48	0	0
T45	0	8	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	37	0	0
T71	0	85	0	0
T72	0	312	0	0
T76	0	45	0	0
T87	0	74	0	0
T106	0	58	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5592	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	30	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	47	0	0
T42	0	29	0	0
T45	0	8	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	20	0	0
T71	0	77	0	0
T72	0	236	0	0
T76	0	35	0	0
T87	0	94	0	0
T106	0	62	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5532	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	40	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	32	0	0
T42	0	37	0	0
T45	0	13	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	25	0	0
T71	0	66	0	0
T72	0	265	0	0
T76	0	43	0	0
T87	0	75	0	0
T106	0	47	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5366	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	11	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	61	0	0
T42	0	34	0	0
T45	0	8	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	23	0	0
T71	0	54	0	0
T72	0	280	0	0
T76	0	38	0	0
T87	0	79	0	0
T106	0	44	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5368	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	54	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	42	0	0
T42	0	18	0	0
T45	0	14	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	24	0	0
T71	0	65	0	0
T72	0	274	0	0
T76	0	34	0	0
T87	0	68	0	0
T106	0	50	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	1921	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	4	0	0
T66	437444	0	0	0
T71	0	9	0	0
T83	0	36	0	0
T139	0	1	0	0
T158	0	14	0	0
T216	0	21	0	0
T223	0	27	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T244	0	10	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T287	0	32	0	0
T288	0	15	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	1908	0	0
T71	109236	13	0	0
T72	101749	0	0	0
T73	231912	0	0	0
T83	0	24	0	0
T86	133903	0	0	0
T87	102943	0	0	0
T136	218653	0	0	0
T137	81803	0	0	0
T138	76411	0	0	0
T139	108020	5	0	0
T140	534545	0	0	0
T158	0	38	0	0
T216	0	27	0	0
T223	0	17	0	0
T244	0	10	0	0
T287	0	33	0	0
T288	0	16	0	0
T289	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2025	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	7	0	0
T66	437444	0	0	0
T71	0	11	0	0
T83	0	43	0	0
T139	0	13	0	0
T158	0	49	0	0
T216	0	32	0	0
T223	0	26	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T244	0	14	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T287	0	17	0	0
T288	0	13	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	1962	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	1	0	0
T66	437444	0	0	0
T71	0	10	0	0
T83	0	28	0	0
T139	0	13	0	0
T158	0	33	0	0
T216	0	15	0	0
T223	0	31	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T244	0	19	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T287	0	27	0	0
T288	0	27	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5365	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	36	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	56	0	0
T42	0	49	0	0
T45	0	21	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	15	0	0
T71	0	73	0	0
T72	0	283	0	0
T76	0	33	0	0
T87	0	82	0	0
T106	0	34	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5762	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	36	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	27	0	0
T42	0	61	0	0
T45	0	15	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	47	0	0
T71	0	86	0	0
T72	0	304	0	0
T76	0	37	0	0
T87	0	59	0	0
T106	0	34	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5418	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	20	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	52	0	0
T42	0	38	0	0
T45	0	3	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	24	0	0
T71	0	76	0	0
T72	0	247	0	0
T76	0	36	0	0
T87	0	58	0	0
T106	0	45	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5470	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	8	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	58	0	0
T42	0	44	0	0
T45	0	17	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	46	0	0
T71	0	78	0	0
T72	0	295	0	0
T76	0	34	0	0
T87	0	55	0	0
T106	0	25	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5818	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	42	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	62	0	0
T42	0	27	0	0
T45	0	11	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	44	0	0
T71	0	76	0	0
T72	0	261	0	0
T76	0	45	0	0
T87	0	57	0	0
T106	0	54	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5513	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	49	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	62	0	0
T42	0	26	0	0
T45	0	11	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	45	0	0
T71	0	77	0	0
T72	0	322	0	0
T76	0	36	0	0
T87	0	57	0	0
T106	0	42	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5702	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	43	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	59	0	0
T42	0	50	0	0
T45	0	5	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	53	0	0
T71	0	50	0	0
T72	0	286	0	0
T76	0	65	0	0
T87	0	70	0	0
T106	0	32	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5527	0	0
T3	60716	0	0	0
T5	90581	0	0	0
T6	259317	0	0	0
T12	121066	14	0	0
T13	45028	0	0	0
T14	101034	0	0	0
T15	48834	0	0	0
T21	147516	0	0	0
T26	0	58	0	0
T42	0	60	0	0
T45	0	7	0	0
T50	55305	0	0	0
T51	240934	0	0	0
T68	0	57	0	0
T71	0	84	0	0
T72	0	305	0	0
T76	0	38	0	0
T87	0	75	0	0
T106	0	74	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	3007	0	0
T19	56425	0	0	0
T23	245115	0	0	0
T26	157158	17	0	0
T34	111466	0	0	0
T41	196962	0	0	0
T42	103495	32	0	0
T45	0	24	0	0
T57	76286	0	0	0
T59	234530	0	0	0
T68	0	11	0	0
T71	0	21	0	0
T72	0	121	0	0
T87	0	29	0	0
T106	0	20	0	0
T139	0	2	0	0
T143	24724	0	0	0
T144	49125	0	0	0
T290	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2520	0	0
T45	116172	11	0	0
T61	58941	18	0	0
T71	0	13	0	0
T83	0	41	0	0
T134	0	23	0	0
T139	0	23	0	0
T158	0	52	0	0
T216	0	18	0	0
T244	0	37	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T287	0	43	0	0
T290	29353	0	0	0
T291	130869	0	0	0
T292	58972	0	0	0
T293	98208	0	0	0
T294	62923	0	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	4840	0	0
T11	237182	5	0	0
T19	56425	0	0	0
T23	245115	0	0	0
T26	157158	0	0	0
T33	0	1	0	0
T34	111466	0	0	0
T41	196962	0	0	0
T42	103495	0	0	0
T45	0	1	0	0
T57	76286	0	0	0
T59	234530	0	0	0
T64	251013	0	0	0
T71	0	13	0	0
T79	0	7	0	0
T83	0	34	0	0
T139	0	1	0	0
T141	0	8	0	0
T158	0	44	0	0
T219	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2009	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	11	0	0
T66	437444	0	0	0
T71	0	11	0	0
T83	0	36	0	0
T139	0	18	0	0
T158	0	55	0	0
T216	0	34	0	0
T223	0	16	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T244	0	16	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T287	0	18	0	0
T288	0	18	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	6369	0	0
T8	102768	0	0	0
T9	782066	0	0	0
T10	547310	0	0	0
T11	237182	0	0	0
T22	244794	90	0	0
T25	161983	0	0	0
T26	157158	0	0	0
T45	0	63	0	0
T54	72391	0	0	0
T59	0	49	0	0
T61	0	46	0	0
T63	65815	0	0	0
T64	251013	0	0	0
T71	0	79	0	0
T136	0	167	0	0
T139	0	6	0	0
T158	0	38	0	0
T177	0	39	0	0
T295	0	76	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	6955	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	66	0	0
T66	437444	0	0	0
T71	0	206	0	0
T83	0	45	0	0
T86	0	65	0	0
T136	0	81	0	0
T139	0	13	0	0
T158	0	161	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T296	0	139	0	0
T297	0	67	0	0
T298	0	71	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5520	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	62	0	0
T66	437444	0	0	0
T71	0	244	0	0
T83	0	27	0	0
T86	0	61	0	0
T136	0	93	0	0
T139	0	11	0	0
T158	0	170	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T296	0	129	0	0
T297	0	71	0	0
T298	0	54	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	5192	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	53	0	0
T66	437444	0	0	0
T71	0	221	0	0
T83	0	39	0	0
T86	0	67	0	0
T136	0	81	0	0
T139	0	15	0	0
T158	0	160	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T296	0	111	0	0
T297	0	62	0	0
T298	0	61	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2204	0	0
T32	110176	0	0	0
T35	58733	0	0	0
T37	109031	0	0	0
T45	116172	10	0	0
T66	437444	0	0	0
T71	0	15	0	0
T83	0	38	0	0
T139	0	14	0	0
T158	0	36	0	0
T216	0	25	0	0
T223	0	13	0	0
T240	42629	0	0	0
T241	170943	0	0	0
T244	0	3	0	0
T284	201308	0	0	0
T285	101465	0	0	0
T286	48837	0	0	0
T287	0	23	0	0
T288	0	18	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2197	0	0
T20	245883	4	0	0
T43	84956	0	0	0
T44	249488	0	0	0
T45	0	12	0	0
T61	58941	0	0	0
T65	128195	0	0	0
T71	0	19	0	0
T72	0	9	0	0
T83	0	48	0	0
T129	201318	0	0	0
T130	202719	0	0	0
T131	61534	0	0	0
T132	101669	0	0	0
T133	444430	0	0	0
T134	0	6	0	0
T136	0	9	0	0
T158	0	38	0	0
T299	0	4	0	0
T300	0	1	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2185	0	0
T20	245883	5	0	0
T34	111466	0	0	0
T41	196962	0	0	0
T42	103495	0	0	0
T43	84956	0	0	0
T45	0	13	0	0
T57	76286	9	0	0
T59	234530	0	0	0
T60	235536	0	0	0
T71	0	15	0	0
T72	0	3	0	0
T83	0	59	0	0
T136	0	6	0	0
T139	0	13	0	0
T143	24724	0	0	0
T144	49125	0	0	0
T158	0	43	0	0
T299	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2154	0	0
T20	245883	12	0	0
T34	111466	0	0	0
T41	196962	0	0	0
T42	103495	0	0	0
T43	84956	0	0	0
T45	0	16	0	0
T57	76286	5	0	0
T59	234530	0	0	0
T60	235536	0	0	0
T71	0	16	0	0
T72	0	2	0	0
T83	0	33	0	0
T134	0	5	0	0
T139	0	8	0	0
T143	24724	0	0	0
T144	49125	0	0	0
T158	0	45	0	0
T299	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1222527726	2126	0	0
T20	245883	10	0	0
T34	111466	0	0	0
T41	196962	0	0	0
T42	103495	0	0	0
T43	84956	0	0	0
T45	0	9	0	0
T57	76286	13	0	0
T59	234530	0	0	0
T60	235536	0	0	0
T71	0	19	0	0
T72	0	1	0	0
T83	0	53	0	0
T136	0	8	0	0
T139	0	5	0	0
T143	24724	0	0	0
T144	49125	0	0	0
T158	0	56	0	0
T299	0	11	0	0