Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1286

1

T1

5

T8

2

T9

6

auto[1]

1719

1

T1

11

T8

5

T9

10

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2536

1

T1

16

T8

5

T9

11

auto[1]

469

1

T8

2

T9

5

T11

10

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2837

1

T1

16

T8

7

T9

12

auto[1]

168

1

T9

4

T25

5

T26

1

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2893

1

T1

13

T8

5

T9

16

auto[1]

112

1

T1

3

T8

2

T27

1

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2828

1

T1

16

T8

5

T9

12

auto[1]

177

1

T8

2

T9

4

T28

1

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1963

1

T1

16

T8

7

T9

5

auto[1]

1042

1

T9

11

T11

24

T62

20

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1265

1

T1

1

T8

2

T9

8

auto[1]

1740

1

T1

15

T8

5

T9

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1243

1

T1

5

T8

3

T9

5

auto[1]

1762

1

T1

11

T8

4

T9

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1316

1

T1

2

T8

4

T9

9

auto[1]

1689

1

T1

14

T8

3

T9

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T1

14

T8

1

T9

8

auto[1]

1871

1

T1

2

T8

6

T9

8

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T11

1

T25

2

T233

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T9

1

T27

1

T239

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T26

1

T57

3

T67

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T239

1

T272

1

T81

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T25

1

T28

1

T26

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T61

2

T154

1

T155

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T8

1

T25

3

T57

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T62

1

T242

1

T313

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T22

1

T25

2

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T11

1

T272

1

T242

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T11

1

T62

1

T155

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T22

1

T62

1

T67

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T61

1

T239

1

T272

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

46

1

T109

1

T96

2

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T11

1

T61

1

T221

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T9

2

T25

2

T58

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T9

1

T11

1

T272

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T22

1

T25

1

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T11

1

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T25

3

T28

1

T67

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T61

2

T239

1

T272

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

55

1

T25

6

T32

1

T61

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T9

1

T11

1

T61

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T1

1

T25

3

T67

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T242

1

T155

1

T149

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T272

2

T242

1

T79

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

70

1

T25

5

T58

1

T241

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

43

1

T11

2

T62

2

T61

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

63

1

T96

2

T241

1

T224

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

34

1

T62

1

T61

3

T239

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

32

1

T28

1

T57

1

T233

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T9

1

T62

1

T243

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T57

1

T58

2

T67

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T9

1

T62

1

T165

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T1

2

T38

3

T57

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T11

1

T239

1

T234

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

83

1

T57

15

T58

1

T67

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T11

1

T221

7

T272

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T1

2

T22

1

T74

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T62

1

T242

2

T236

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T1

1

T96

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T62

2

T272

1

T236

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T22

1

T38

9

T58

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T67

2

T242

1

T79

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T58

2

T67

1

T233

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

36

1

T67

6

T109

9

T61

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T58

1

T67

1

T232

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T11

1

T62

1

T236

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T26

1

T235

1

T314

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T62

2

T61

1

T234

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T8

1

T58

1

T96

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T11

1

T62

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

79

1

T232

9

T96

4

T315

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T239

1

T234

4

T236

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

70

1

T28

1

T26

1

T58

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T154

1

T79

1

T237

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T1

10

T22

9

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T239

3

T234

1

T68

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

104

1

T26

8

T58

13

T74

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T67

1

T239

1

T242

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

246

1

T8

3

T9

3

T28

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T11

2

T61

1

T272

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T61

1

T154

1

T226

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T316

1

T79

1

T317

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T62

1

T154

1

T317

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T9

1

T11

1

T154

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T239

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T237

1

T153

2

T318

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T9

1

T11

1

T149

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T221

4

T154

1

T183

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

10

1

T61

1

T236

1

T154

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T239

1

T317

1

T69

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T67

1

T154

1

T183

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T27

1

T236

1

T237

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T11

1

T238

1

T153

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T98

1

T81

1

T82

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T241

3

T313

6

T223

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T241

5

T154

1

T183

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T272

1

T243

1

T153

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T317

1

T319

1

T320

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T98

1

T317

1

T153

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T239

1

T321

3

T153

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T239

1

T236

1

T154

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T62

1

T272

1

T69

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T67

3

T239

1

T237

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T317

1

T153

2

T319

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T79

1

T153

1

T318

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T165

2

T153

1

T320

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T79

1

T243

1

T203

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T62

1

T239

1

T243

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T236

1

T238

1

T153

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T9

1

T226

1

T322

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T11

1

T67

2

T153

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

118

1

T9

2

T11

6

T62

2

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T11

1

T25

2

T233

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T9

1

T61

1

T27

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T26

1

T57

3

T67

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T239

1

T272

1

T316

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T8

1

T25

1

T28

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T62

1

T61

2

T154

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T8

1

T25

3

T57

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T9

1

T11

1

T62

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T22

1

T25

2

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T11

1

T239

1

T272

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T11

1

T62

1

T155

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T22

1

T62

1

T67

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

31

1

T9

1

T11

1

T61

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T109

1

T96

2

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32

1

T11

1

T61

1

T221

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T9

2

T25

2

T58

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T9

1

T11

1

T61

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T22

1

T25

1

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T9

1

T11

1

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T25

1

T28

1

T67

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T67

1

T61

2

T239

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T25

6

T32

1

T61

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T9

1

T11

1

T61

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T1

1

T25

3

T67

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T11

1

T242

1

T155

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T98

1

T272

2

T242

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T25

2

T58

1

T241

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

63

1

T11

2

T62

2

T61

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

67

1

T96

2

T241

1

T224

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T62

1

T61

3

T239

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

35

1

T28

1

T57

1

T233

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T9

1

T62

1

T272

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T8

1

T57

1

T58

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T62

1

T165

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T1

2

T38

3

T57

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T11

1

T98

1

T239

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

79

1

T57

10

T58

1

T67

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

40

1

T11

1

T239

1

T221

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T1

2

T22

1

T74

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T62

1

T239

1

T242

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T1

1

T96

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T62

3

T272

2

T236

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T22

1

T38

9

T58

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T67

3

T239

1

T242

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T58

2

T233

8

T235

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

42

1

T67

6

T109

9

T61

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T58

1

T67

1

T232

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T11

1

T62

1

T236

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T235

1

T314

1

T323

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T62

2

T61

1

T234

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T8

1

T58

1

T96

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T11

1

T62

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

72

1

T232

9

T96

4

T315

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

57

1

T62

1

T239

2

T234

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T28

1

T26

1

T58

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T236

1

T154

1

T79

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

77

1

T1

10

T22

9

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T9

1

T239

3

T234

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

103

1

T26

8

T58

8

T74

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T11

1

T67

3

T239

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

163

1

T8

3

T9

1

T28

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

108

1

T11

8

T62

2

T61

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T241

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T67

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T203

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

24

1

T9

2

T27

1

T239

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	31	65	67.71	31
Automatically Generated Cross Bins	96	31	65	67.71	31
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T11

1

T25

2

T233

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T9

1

T61

1

T27

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T26

1

T57

3

T67

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T239

1

T272

1

T316

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T8

1

T25

1

T28

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T62

1

T61

2

T154

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T8

1

T25

3

T57

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T9

1

T11

1

T62

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T22

1

T25

2

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T11

1

T239

1

T272

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T11

1

T62

1

T155

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T22

1

T62

1

T67

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

31

1

T9

1

T11

1

T61

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

45

1

T109

1

T96

2

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32

1

T11

1

T61

1

T221

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T9

2

T25

2

T58

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T9

1

T11

1

T61

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T22

1

T25

1

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T9

1

T11

1

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T25

3

T28

1

T67

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T67

1

T61

2

T239

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

62

1

T25

6

T32

1

T61

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T9

1

T11

1

T61

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T1

1

T25

3

T67

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T11

1

T242

1

T155

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T98

1

T272

2

T242

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

71

1

T25

5

T58

1

T241

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

64

1

T11

2

T62

2

T61

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

67

1

T96

2

T241

1

T224

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T62

1

T61

3

T239

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

35

1

T28

1

T57

1

T233

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T9

1

T62

1

T272

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T8

1

T57

1

T58

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T62

1

T165

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T1

2

T38

3

T57

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T11

1

T98

1

T239

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

85

1

T57

15

T58

1

T67

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

40

1

T11

1

T239

1

T221

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T1

1

T22

1

T74

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T62

1

T239

1

T242

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T1

1

T96

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T62

3

T272

2

T236

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T22

1

T38

9

T58

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T67

5

T239

1

T242

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

78

1

T58

2

T67

1

T233

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

42

1

T67

6

T109

9

T61

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T58

1

T67

1

T232

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T11

1

T62

1

T236

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T26

1

T235

1

T314

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T62

2

T61

1

T234

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T8

1

T58

1

T96

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T11

1

T62

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

83

1

T232

9

T96

4

T315

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

57

1

T62

1

T239

2

T234

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

72

1

T28

1

T26

1

T58

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T236

1

T154

1

T79

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T1

8

T22

9

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T9

1

T239

3

T234

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

108

1

T26

8

T58

13

T74

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T11

1

T67

3

T239

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

171

1

T8

1

T9

3

T28

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

122

1

T9

2

T11

8

T62

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T27

1

T153

1

T319

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T11

1

T25

2

T233

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T9

1

T61

1

T27

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T26

1

T57

3

T67

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T239

1

T272

1

T316

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

63

1

T8

1

T25

1

T28

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T62

1

T61

2

T154

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T8

1

T25

3

T57

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T9

1

T11

1

T62

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T22

1

T25

2

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T11

1

T239

1

T272

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T11

1

T62

1

T155

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T22

1

T62

1

T67

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

31

1

T9

1

T11

1

T61

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43

1

T109

1

T96

2

T235

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32

1

T11

1

T61

1

T221

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T9

2

T25

2

T58

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T9

1

T11

1

T61

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T22

1

T25

1

T234

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T9

1

T11

1

T62

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T25

3

T28

1

T67

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T67

1

T61

2

T239

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

60

1

T25

6

T32

1

T61

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T9

1

T11

1

T61

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T1

1

T25

3

T67

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T11

1

T242

1

T155

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T96

1

T235

2

T234

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T98

1

T272

2

T242

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

71

1

T25

5

T58

1

T241

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

64

1

T11

2

T62

2

T61

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

65

1

T96

2

T241

1

T224

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T62

1

T61

3

T239

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

35

1

T28

1

T57

1

T233

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T9

1

T62

1

T272

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T8

1

T57

1

T58

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T9

1

T62

1

T165

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T1

2

T38

3

T57

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T11

1

T98

1

T239

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

79

1

T57

15

T58

1

T67

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

39

1

T11

1

T239

1

T221

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T1

2

T22

1

T74

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T62

1

T239

1

T242

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T1

1

T96

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T62

3

T272

2

T236

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T22

1

T38

9

T58

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T67

5

T239

1

T242

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

81

1

T58

2

T67

1

T233

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

42

1

T67

6

T109

9

T61

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T58

1

T67

1

T232

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T11

1

T62

1

T236

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T26

1

T235

1

T314

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T62

2

T61

1

T234

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T8

1

T58

1

T96

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

41

1

T11

1

T62

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

81

1

T232

9

T96

4

T315

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

57

1

T62

1

T239

2

T234

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

70

1

T28

1

T26

1

T58

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T236

1

T154

1

T79

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

76

1

T1

10

T22

9

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T9

1

T239

3

T234

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

95

1

T26

8

T58

13

T74

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T11

1

T67

3

T239

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

151

1

T8

1

T235

1

T98

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

104

1

T9

1

T11

8

T62

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T183

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T321

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

28

1

T9

1

T62

1

T27

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded