Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.99 99.38 96.68 100.00 98.08 98.82 99.52 93.42


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
54.19 54.19 78.15 78.15 64.79 64.79 63.01 63.01 15.38 15.38 78.93 78.93 69.08 69.08 9.97 9.97 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1468629735
74.96 20.77 91.04 12.89 84.76 19.97 86.76 23.74 35.90 20.51 91.72 12.79 81.70 12.62 52.86 42.88 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.954670165
83.13 8.17 95.45 4.40 88.98 4.22 86.76 0.00 71.79 35.90 95.75 4.03 87.86 6.17 55.32 2.47 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.893556998
87.15 4.02 97.01 1.57 90.90 1.92 86.76 0.00 84.62 12.82 96.78 1.04 93.16 5.30 60.79 5.47 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1565009549
89.79 2.64 97.85 0.84 92.19 1.29 87.44 0.68 89.74 5.13 97.30 0.52 96.15 2.99 67.86 7.07 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1278467206
91.38 1.59 97.85 0.00 92.39 0.20 94.75 7.31 89.74 0.00 97.30 0.00 96.44 0.29 71.20 3.34 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.4275988346
92.51 1.12 97.93 0.07 93.58 1.19 95.43 0.68 89.74 0.00 97.41 0.11 96.44 0.00 77.01 5.81 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4046472820
93.43 0.93 98.28 0.35 94.16 0.58 98.06 2.63 91.03 1.28 97.74 0.33 96.92 0.48 77.83 0.82 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1365127543
94.27 0.84 98.41 0.13 94.34 0.18 98.06 0.00 91.67 0.64 97.89 0.15 97.01 0.10 82.53 4.70 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3913744318
94.85 0.58 98.84 0.43 94.36 0.03 98.06 0.00 94.87 3.21 98.30 0.41 97.01 0.00 82.53 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2054376208
95.29 0.44 98.97 0.13 94.49 0.13 98.06 0.00 95.51 0.64 98.34 0.04 97.01 0.00 84.66 2.13 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2413878714
95.64 0.35 99.07 0.09 94.62 0.13 98.06 0.00 96.79 1.28 98.45 0.11 97.40 0.39 85.09 0.44 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2740629186
95.92 0.28 99.07 0.00 94.64 0.03 99.66 1.60 96.79 0.00 98.45 0.00 97.50 0.10 85.33 0.24 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1610542320
96.12 0.20 99.07 0.00 94.67 0.03 99.66 0.00 96.79 0.00 98.45 0.00 97.59 0.10 86.64 1.31 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.1541067300
96.31 0.19 99.10 0.04 94.67 0.00 99.66 0.00 96.79 0.00 98.45 0.00 97.59 0.00 87.90 1.26 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2624162829
96.47 0.16 99.10 0.00 94.67 0.00 99.66 0.00 96.79 0.00 98.45 0.00 97.59 0.00 89.01 1.11 /workspace/coverage/default/46.sysrst_ctrl_stress_all.804706717
96.62 0.15 99.14 0.04 94.77 0.10 99.66 0.00 96.79 0.00 98.52 0.07 98.17 0.58 89.25 0.24 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3576258503
96.75 0.13 99.20 0.06 94.82 0.05 99.66 0.00 97.44 0.64 98.60 0.07 98.27 0.10 89.25 0.00 /workspace/coverage/default/42.sysrst_ctrl_stress_all.2963593611
96.87 0.12 99.23 0.04 94.84 0.03 99.66 0.00 98.08 0.64 98.63 0.04 98.36 0.10 89.25 0.00 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3507181806
96.98 0.12 99.23 0.00 95.65 0.81 99.66 0.00 98.08 0.00 98.63 0.00 98.36 0.00 89.25 0.00 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4032070847
97.08 0.10 99.27 0.04 95.73 0.08 99.66 0.00 98.08 0.00 98.71 0.07 98.55 0.19 89.55 0.29 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.650753232
97.16 0.08 99.27 0.00 95.75 0.03 99.66 0.00 98.08 0.00 98.71 0.00 98.65 0.10 89.98 0.44 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4201412887
97.22 0.07 99.33 0.06 95.83 0.08 100.00 0.34 98.08 0.00 98.71 0.00 98.65 0.00 89.98 0.00 /workspace/coverage/default/20.sysrst_ctrl_alert_test.3597651177
97.29 0.06 99.33 0.00 96.13 0.30 100.00 0.00 98.08 0.00 98.71 0.00 98.75 0.10 90.03 0.05 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4006709359
97.35 0.06 99.33 0.00 96.23 0.10 100.00 0.00 98.08 0.00 98.71 0.00 98.84 0.10 90.27 0.24 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2447064404
97.41 0.06 99.33 0.00 96.23 0.00 100.00 0.00 98.08 0.00 98.71 0.00 98.84 0.00 90.71 0.44 /workspace/coverage/default/19.sysrst_ctrl_combo_detect.506252988
97.46 0.05 99.33 0.00 96.23 0.00 100.00 0.00 98.08 0.00 98.71 0.00 98.84 0.00 91.05 0.34 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.7621903
97.51 0.05 99.33 0.00 96.23 0.00 100.00 0.00 98.08 0.00 98.71 0.00 98.94 0.10 91.29 0.24 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3984748845
97.55 0.04 99.33 0.00 96.23 0.00 100.00 0.00 98.08 0.00 98.71 0.00 98.94 0.00 91.58 0.29 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1433209078
97.59 0.04 99.33 0.00 96.31 0.08 100.00 0.00 98.08 0.00 98.71 0.00 99.13 0.19 91.58 0.00 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.905177129
97.62 0.03 99.33 0.00 96.31 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.13 0.00 91.77 0.19 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1808466370
97.65 0.03 99.33 0.00 96.31 0.00 100.00 0.00 98.08 0.00 98.71 0.00 99.13 0.00 91.97 0.19 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3574960173
97.67 0.03 99.35 0.02 96.33 0.03 100.00 0.00 98.08 0.00 98.74 0.04 99.23 0.10 91.97 0.00 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.844068295
97.70 0.03 99.35 0.00 96.51 0.18 100.00 0.00 98.08 0.00 98.74 0.00 99.23 0.00 91.97 0.00 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.605487501
97.72 0.02 99.35 0.00 96.54 0.03 100.00 0.00 98.08 0.00 98.74 0.00 99.33 0.10 92.01 0.05 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1120558453
97.74 0.02 99.35 0.00 96.59 0.05 100.00 0.00 98.08 0.00 98.74 0.00 99.42 0.10 92.01 0.00 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4119447505
97.76 0.02 99.35 0.00 96.59 0.00 100.00 0.00 98.08 0.00 98.74 0.00 99.42 0.00 92.16 0.15 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.1038743683
97.78 0.02 99.35 0.00 96.59 0.00 100.00 0.00 98.08 0.00 98.74 0.00 99.42 0.00 92.30 0.15 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2123470846
97.80 0.02 99.35 0.00 96.61 0.03 100.00 0.00 98.08 0.00 98.74 0.00 99.52 0.10 92.30 0.00 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1821450687
97.81 0.01 99.35 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.74 0.00 99.52 0.00 92.40 0.10 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.676865710
97.83 0.01 99.35 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.74 0.00 99.52 0.00 92.50 0.10 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1074517173
97.84 0.01 99.35 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.74 0.00 99.52 0.00 92.59 0.10 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.317279613
97.86 0.01 99.35 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.74 0.00 99.52 0.00 92.69 0.10 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.2651241615
97.87 0.01 99.35 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.74 0.00 99.52 0.00 92.79 0.10 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3109568624
97.88 0.01 99.37 0.02 96.61 0.00 100.00 0.00 98.08 0.00 98.78 0.04 99.52 0.00 92.79 0.00 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.2189710563
97.89 0.01 99.38 0.02 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.04 99.52 0.00 92.79 0.00 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.704676378
97.89 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 92.84 0.05 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.747339575
97.90 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 92.88 0.05 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.395747359
97.91 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 92.93 0.05 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2680735386
97.91 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 92.98 0.05 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.447588355
97.92 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.03 0.05 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3694535796
97.93 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.08 0.05 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2508360522
97.93 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.13 0.05 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3060498888
97.94 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.18 0.05 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3041917170
97.95 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.22 0.05 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3213794101
97.95 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.27 0.05 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3105536339
97.96 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.32 0.05 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.981136041
97.97 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.37 0.05 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.481806101
97.98 0.01 99.38 0.00 96.61 0.00 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.42 0.05 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.85348220
97.98 0.01 99.38 0.00 96.64 0.03 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.42 0.00 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2654613826
97.98 0.01 99.38 0.00 96.66 0.03 100.00 0.00 98.08 0.00 98.82 0.00 99.52 0.00 93.42 0.00 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.4131586616


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1746416337
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3807446037
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.325280482
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4048410339
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3431009590
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3890809857
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.973550790
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4191760774
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1433619605
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1660254735
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.146851156
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1334255936
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1082403473
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3622840827
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3457460342
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3254982794
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.4107809998
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1833655493
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1650309941
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2372643298
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1968497283
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.576622102
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.130696078
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2786449344
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1548844119
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.193150300
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3918599519
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3907648473
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3994110747
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.123618960
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3631378934
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2550619479
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3478582039
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3819392852
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.997746907
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1182679653
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1243640893
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.505974593
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.4284780047
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3190730465
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3718516575
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.960565107
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1503948794
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2864306564
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.833895935
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1248110330
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.425999406
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3101648880
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3084467603
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2318147247
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3630564378
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2420088008
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2062926629
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3589758167
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.4242642976
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2173726206
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.572045499
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3849762860
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2828447610
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1619625844
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3549832076
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2809441473
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3695067601
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2775837329
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1736013588
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3592457769
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1520625914
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3437670541
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3044848197
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3528025895
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3133392586
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1800542796
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3135936655
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1024341140
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2242826192
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3686364527
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1787131404
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3833674358
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3711264321
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2219749400
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1974113110
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2361147380
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2100825715
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3810398131
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.824296184
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1579678780
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3827867471
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3333656014
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1824804768
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4033885538
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1202439993
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1786394893
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3553883136
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.766825282
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1925919638
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3592002015
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.294164261
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3122667752
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/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3031698187
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1757764427
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2167522883
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1031790267
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.106194290
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1423360059
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1702513088
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.4225654555
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3154936411
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1666546199
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1026711435
/workspace/coverage/default/43.sysrst_ctrl_smoke.2302088884
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3647390888
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3623359223
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3315680350
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1848894644
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.462000155
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2875670058
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.23558768
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.63358266
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3358404327
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1968065424
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2253420972
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3787965582
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3250960574
/workspace/coverage/default/44.sysrst_ctrl_smoke.3640944874
/workspace/coverage/default/44.sysrst_ctrl_stress_all.770483148
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.253512703
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2154112050
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.672571492
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.523941955
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2687702434
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.38154031
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1698059688
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2539879389
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1758430110
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.158502347
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.4127375213
/workspace/coverage/default/45.sysrst_ctrl_smoke.2193879038
/workspace/coverage/default/45.sysrst_ctrl_stress_all.1183313631
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1082286950
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1624223859
/workspace/coverage/default/46.sysrst_ctrl_alert_test.253764204
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2449570019
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.2370122427
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.48129208
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1183762937
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3629432808
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2325019007
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1434326953
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.4105920850
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.350844114
/workspace/coverage/default/46.sysrst_ctrl_smoke.2634157482
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3534733186
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.719046507
/workspace/coverage/default/47.sysrst_ctrl_alert_test.4242306934
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3586375970
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3045916349
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3380435334
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1777745409
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1616815163
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3632835758
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1828008824
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2827301663
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3834766346
/workspace/coverage/default/47.sysrst_ctrl_smoke.3691485180
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1410385934
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3634467277
/workspace/coverage/default/48.sysrst_ctrl_alert_test.1002570061
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.251756090
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.351477833
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.875636441
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3310434589
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1994009771
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.261805204
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3692700262
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3089171913
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3688759860
/workspace/coverage/default/48.sysrst_ctrl_smoke.2654083420
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2613799093
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.4192287554
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1875847687
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1627896161
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3310279231
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1417114475
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3192785746
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1115084845
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1277915787
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4275120609
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.65347441
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1798588773
/workspace/coverage/default/49.sysrst_ctrl_smoke.1436920833
/workspace/coverage/default/49.sysrst_ctrl_stress_all.3331719620
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2236138438
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2667919290
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3339598168
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3906806191
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1483782300
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3125221819
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1450109423
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1541950199
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2678602680
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3464551021
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2249887052
/workspace/coverage/default/5.sysrst_ctrl_smoke.2378180043
/workspace/coverage/default/5.sysrst_ctrl_stress_all.1161847742
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.255680302
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2995391719
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1823168066
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.563655266
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3952313364
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.849488177
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3557375358
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1095797543
/workspace/coverage/default/6.sysrst_ctrl_alert_test.505571627
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3864871470
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1476425356
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2270131902
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3626635497
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.3485387508
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2784732556
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1067307478
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4119623739
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.235264383
/workspace/coverage/default/6.sysrst_ctrl_smoke.4103738173
/workspace/coverage/default/6.sysrst_ctrl_stress_all.2861086594
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.945482081
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3498414605
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.405337533
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.456220386
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3401613354
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4242453894
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3162054992
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.81957469
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2700248397
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1575089304
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3747154082
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2708968931
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2001174452
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1729998984
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.2813999114
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1207141614
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1880524644
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2117191361
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2203529735
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1900748919
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2546833736
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3548719478
/workspace/coverage/default/7.sysrst_ctrl_smoke.3473996002
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3533946042
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3050014102
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3318413615
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1873609320
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1389693011
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3468161530
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.561772158
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2382807801
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.4233891183
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.329854205
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2376538581
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3119117308
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3908148642
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1280253185
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3076337393
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3644872308
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2488954603
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1331166339
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3804125158
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.816512050
/workspace/coverage/default/8.sysrst_ctrl_smoke.2594533992
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2704322004
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1200223155
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3739604812
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.4051260034
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2722382138
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.973585043
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1569011584
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1846686845
/workspace/coverage/default/9.sysrst_ctrl_alert_test.604126129
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2117369640
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2230248084
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.119356927
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3709900635
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2964773989
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1779512498
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.498651247
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.410768001
/workspace/coverage/default/9.sysrst_ctrl_smoke.470154767
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1278418882
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1839025155
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3238820551
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1291343331
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4260869804
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.111548493
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2314703659
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2838794666
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.56732114
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2303111494




Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1468629735 Aug 08 06:06:47 PM PDT 24 Aug 08 06:07:34 PM PDT 24 69798214960 ps
T4 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.4233891183 Aug 08 06:07:28 PM PDT 24 Aug 08 06:07:59 PM PDT 24 22839254553 ps
T2 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1280431359 Aug 08 06:06:05 PM PDT 24 Aug 08 06:06:07 PM PDT 24 3235824261 ps
T12 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.207441385 Aug 08 06:06:52 PM PDT 24 Aug 08 06:07:01 PM PDT 24 3295508093 ps
T13 /workspace/coverage/default/28.sysrst_ctrl_stress_all.2151384417 Aug 08 06:06:45 PM PDT 24 Aug 08 06:06:47 PM PDT 24 6926495715 ps
T14 /workspace/coverage/default/33.sysrst_ctrl_stress_all.197979970 Aug 08 06:06:55 PM PDT 24 Aug 08 06:07:28 PM PDT 24 13664043237 ps
T3 /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2117191361 Aug 08 06:06:13 PM PDT 24 Aug 08 06:06:22 PM PDT 24 3225890552 ps
T5 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.1038743683 Aug 08 06:06:30 PM PDT 24 Aug 08 06:06:51 PM PDT 24 31296079244 ps
T6 /workspace/coverage/default/35.sysrst_ctrl_edge_detect.2251459779 Aug 08 06:06:55 PM PDT 24 Aug 08 06:06:57 PM PDT 24 2410235784 ps
T15 /workspace/coverage/default/20.sysrst_ctrl_alert_test.3597651177 Aug 08 06:06:39 PM PDT 24 Aug 08 06:06:45 PM PDT 24 2012525947 ps
T7 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3290323275 Aug 08 06:05:53 PM PDT 24 Aug 08 06:06:02 PM PDT 24 11091668811 ps
T8 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1365127543 Aug 08 06:06:10 PM PDT 24 Aug 08 06:09:40 PM PDT 24 88730870350 ps
T9 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1488498819 Aug 08 06:06:53 PM PDT 24 Aug 08 06:07:52 PM PDT 24 103157254324 ps
T24 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.777180798 Aug 08 06:06:34 PM PDT 24 Aug 08 06:06:40 PM PDT 24 3497269506 ps
T21 /workspace/coverage/default/2.sysrst_ctrl_stress_all.3679113450 Aug 08 06:05:59 PM PDT 24 Aug 08 06:06:42 PM PDT 24 21004604362 ps
T33 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.887377459 Aug 08 06:06:00 PM PDT 24 Aug 08 06:07:04 PM PDT 24 183292447325 ps
T22 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3747154082 Aug 08 06:07:26 PM PDT 24 Aug 08 06:09:38 PM PDT 24 50407604634 ps
T10 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.954670165 Aug 08 06:06:43 PM PDT 24 Aug 08 06:08:57 PM PDT 24 95883021494 ps
T41 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.119356927 Aug 08 06:06:20 PM PDT 24 Aug 08 06:06:32 PM PDT 24 4088215550 ps
T34 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1729998984 Aug 08 06:06:05 PM PDT 24 Aug 08 06:06:14 PM PDT 24 3356357596 ps
T42 /workspace/coverage/default/1.sysrst_ctrl_smoke.1633406112 Aug 08 06:05:51 PM PDT 24 Aug 08 06:05:52 PM PDT 24 2195783045 ps
T46 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.496879226 Aug 08 06:07:07 PM PDT 24 Aug 08 06:07:09 PM PDT 24 2777162375 ps
T95 /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.125158816 Aug 08 06:06:43 PM PDT 24 Aug 08 06:06:47 PM PDT 24 2259328173 ps
T11 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.4275988346 Aug 08 06:05:58 PM PDT 24 Aug 08 06:09:20 PM PDT 24 78745969248 ps
T103 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4037720154 Aug 08 06:06:52 PM PDT 24 Aug 08 06:06:57 PM PDT 24 4332056122 ps
T104 /workspace/coverage/default/3.sysrst_ctrl_alert_test.3257504835 Aug 08 06:05:55 PM PDT 24 Aug 08 06:06:01 PM PDT 24 2013821435 ps
T53 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1411849206 Aug 08 06:06:34 PM PDT 24 Aug 08 06:06:37 PM PDT 24 2530989020 ps
T54 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2874615609 Aug 08 06:06:07 PM PDT 24 Aug 08 06:06:15 PM PDT 24 2511690654 ps
T55 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1968065424 Aug 08 06:07:11 PM PDT 24 Aug 08 06:07:12 PM PDT 24 2658698320 ps
T228 /workspace/coverage/default/37.sysrst_ctrl_smoke.1947952408 Aug 08 06:07:10 PM PDT 24 Aug 08 06:07:16 PM PDT 24 2113909908 ps
T229 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3258385641 Aug 08 06:06:23 PM PDT 24 Aug 08 06:06:30 PM PDT 24 2114475014 ps
T29 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.855734541 Aug 08 06:06:24 PM PDT 24 Aug 08 06:06:34 PM PDT 24 4893680205 ps
T230 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1787326307 Aug 08 06:06:40 PM PDT 24 Aug 08 06:06:44 PM PDT 24 2091943967 ps
T35 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1394438236 Aug 08 06:06:51 PM PDT 24 Aug 08 06:06:52 PM PDT 24 3059728566 ps
T356 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1862368611 Aug 08 06:06:49 PM PDT 24 Aug 08 06:06:59 PM PDT 24 3367814633 ps
T293 /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1026711435 Aug 08 06:07:20 PM PDT 24 Aug 08 06:07:22 PM PDT 24 2523044735 ps
T47 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.144458872 Aug 08 06:06:00 PM PDT 24 Aug 08 06:06:12 PM PDT 24 258638139732 ps
T36 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3906806191 Aug 08 06:05:52 PM PDT 24 Aug 08 06:14:14 PM PDT 24 197094245172 ps
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T43 /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3739604812 Aug 08 06:05:55 PM PDT 24 Aug 08 06:06:03 PM PDT 24 6565572334 ps
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T56 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3360104724 Aug 08 06:06:13 PM PDT 24 Aug 08 06:07:19 PM PDT 24 26832201469 ps
T57 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.561772158 Aug 08 06:07:37 PM PDT 24 Aug 08 06:08:35 PM PDT 24 85502816116 ps
T194 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2567382342 Aug 08 06:06:30 PM PDT 24 Aug 08 06:06:36 PM PDT 24 2036950408 ps
T195 /workspace/coverage/default/15.sysrst_ctrl_stress_all.3087322794 Aug 08 06:06:30 PM PDT 24 Aug 08 06:06:38 PM PDT 24 11176101374 ps
T196 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1974756319 Aug 08 06:06:06 PM PDT 24 Aug 08 06:06:09 PM PDT 24 4279615491 ps
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T355 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.235264383 Aug 08 06:05:55 PM PDT 24 Aug 08 06:06:03 PM PDT 24 2509549017 ps
T364 /workspace/coverage/default/34.sysrst_ctrl_smoke.4261166956 Aug 08 06:06:52 PM PDT 24 Aug 08 06:06:53 PM PDT 24 2137156482 ps
T100 /workspace/coverage/default/10.sysrst_ctrl_stress_all.2784842362 Aug 08 06:06:01 PM PDT 24 Aug 08 06:06:39 PM PDT 24 18784528538 ps
T277 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2592447534 Aug 08 06:06:39 PM PDT 24 Aug 08 06:06:42 PM PDT 24 2510447390 ps
T365 /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3753494654 Aug 08 06:06:33 PM PDT 24 Aug 08 06:06:41 PM PDT 24 2458359911 ps
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T367 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.63358266 Aug 08 06:07:17 PM PDT 24 Aug 08 06:07:23 PM PDT 24 2599667956 ps
T368 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1701260220 Aug 08 06:06:58 PM PDT 24 Aug 08 06:07:00 PM PDT 24 2584017829 ps
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T371 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.861067549 Aug 08 06:07:02 PM PDT 24 Aug 08 06:07:09 PM PDT 24 2614200352 ps
T58 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.447588355 Aug 08 06:06:27 PM PDT 24 Aug 08 06:12:28 PM PDT 24 150879847872 ps
T372 /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1541950199 Aug 08 06:05:52 PM PDT 24 Aug 08 06:05:54 PM PDT 24 2633564275 ps
T373 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1445543292 Aug 08 06:06:05 PM PDT 24 Aug 08 06:06:12 PM PDT 24 2464277079 ps
T374 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3631543093 Aug 08 06:06:34 PM PDT 24 Aug 08 06:06:37 PM PDT 24 2475685870 ps
T32 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.650753232 Aug 08 06:06:12 PM PDT 24 Aug 08 06:07:43 PM PDT 24 98539703808 ps
T170 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.2743281554 Aug 08 06:06:27 PM PDT 24 Aug 08 06:06:34 PM PDT 24 2510547742 ps
T171 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3888516924 Aug 08 06:06:01 PM PDT 24 Aug 08 06:06:03 PM PDT 24 2158193536 ps
T172 /workspace/coverage/default/23.sysrst_ctrl_alert_test.2797312078 Aug 08 06:06:34 PM PDT 24 Aug 08 06:06:36 PM PDT 24 2037298462 ps
T60 /workspace/coverage/default/42.sysrst_ctrl_stress_all.2963593611 Aug 08 06:07:12 PM PDT 24 Aug 08 06:07:30 PM PDT 24 15738261566 ps
T70 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3534733186 Aug 08 06:07:37 PM PDT 24 Aug 08 06:08:21 PM PDT 24 35654601446 ps
T108 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3964325693 Aug 08 06:06:43 PM PDT 24 Aug 08 06:06:44 PM PDT 24 2063610028 ps
T74 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1690843156 Aug 08 06:06:11 PM PDT 24 Aug 08 06:07:17 PM PDT 24 53983412689 ps
T67 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2413878714 Aug 08 06:07:28 PM PDT 24 Aug 08 06:12:14 PM PDT 24 110601060722 ps
T109 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1569011584 Aug 08 06:07:37 PM PDT 24 Aug 08 06:08:50 PM PDT 24 55649260374 ps
T64 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2635898127 Aug 08 06:06:41 PM PDT 24 Aug 08 06:06:44 PM PDT 24 3299563499 ps
T86 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3464551021 Aug 08 06:05:51 PM PDT 24 Aug 08 06:05:53 PM PDT 24 2147661703 ps
T87 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.135260818 Aug 08 06:07:04 PM PDT 24 Aug 08 06:07:06 PM PDT 24 2537063069 ps
T88 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.196023326 Aug 08 06:05:51 PM PDT 24 Aug 08 06:05:59 PM PDT 24 4002217843 ps
T89 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1240212712 Aug 08 06:06:15 PM PDT 24 Aug 08 06:06:56 PM PDT 24 17718653521 ps
T61 /workspace/coverage/default/45.sysrst_ctrl_stress_all.1183313631 Aug 08 06:07:24 PM PDT 24 Aug 08 06:08:44 PM PDT 24 68420689773 ps
T90 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1874313818 Aug 08 06:06:57 PM PDT 24 Aug 08 06:07:34 PM PDT 24 17203522182 ps
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T92 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.703623539 Aug 08 06:06:49 PM PDT 24 Aug 08 06:06:56 PM PDT 24 2609806860 ps
T27 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1565009549 Aug 08 06:07:17 PM PDT 24 Aug 08 06:08:27 PM PDT 24 126302389535 ps
T375 /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2249887052 Aug 08 06:05:54 PM PDT 24 Aug 08 06:06:01 PM PDT 24 2512813014 ps
T97 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3315680350 Aug 08 06:07:16 PM PDT 24 Aug 08 06:07:20 PM PDT 24 8625992112 ps
T376 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2453372618 Aug 08 06:07:01 PM PDT 24 Aug 08 06:07:10 PM PDT 24 2942006961 ps
T75 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.85348220 Aug 08 06:07:39 PM PDT 24 Aug 08 06:08:54 PM PDT 24 29579382981 ps
T232 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3396832233 Aug 08 06:06:29 PM PDT 24 Aug 08 06:07:41 PM PDT 24 42047596760 ps
T377 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1797455441 Aug 08 06:06:20 PM PDT 24 Aug 08 06:06:22 PM PDT 24 3494659224 ps
T378 /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3581801247 Aug 08 06:06:00 PM PDT 24 Aug 08 06:06:02 PM PDT 24 2060294662 ps
T379 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1307495926 Aug 08 06:06:30 PM PDT 24 Aug 08 06:06:34 PM PDT 24 4793192789 ps
T96 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3207202329 Aug 08 06:06:47 PM PDT 24 Aug 08 06:07:17 PM PDT 24 67938284462 ps
T380 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1584157215 Aug 08 06:05:47 PM PDT 24 Aug 08 06:05:53 PM PDT 24 2327331130 ps
T381 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1023652296 Aug 08 06:06:49 PM PDT 24 Aug 08 06:06:56 PM PDT 24 2511488846 ps
T233 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1483782300 Aug 08 06:05:55 PM PDT 24 Aug 08 06:09:02 PM PDT 24 75743651930 ps
T382 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2238883401 Aug 08 06:06:50 PM PDT 24 Aug 08 06:06:53 PM PDT 24 2631591898 ps
T383 /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2957609817 Aug 08 06:06:12 PM PDT 24 Aug 08 06:06:18 PM PDT 24 2108029624 ps
T384 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.232418900 Aug 08 06:06:46 PM PDT 24 Aug 08 06:06:50 PM PDT 24 2619485377 ps
T385 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.261805204 Aug 08 06:07:32 PM PDT 24 Aug 08 06:07:34 PM PDT 24 2661924681 ps
T279 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.834562156 Aug 08 06:05:53 PM PDT 24 Aug 08 06:05:56 PM PDT 24 2521206105 ps
T386 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1338267883 Aug 08 06:06:42 PM PDT 24 Aug 08 06:06:45 PM PDT 24 2934891540 ps
T387 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3716357797 Aug 08 06:06:37 PM PDT 24 Aug 08 06:06:39 PM PDT 24 2475993657 ps
T388 /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2162746792 Aug 08 06:06:24 PM PDT 24 Aug 08 06:06:27 PM PDT 24 3041079772 ps
T389 /workspace/coverage/default/45.sysrst_ctrl_smoke.2193879038 Aug 08 06:07:12 PM PDT 24 Aug 08 06:07:15 PM PDT 24 2139629064 ps
T268 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.832711764 Aug 08 06:06:34 PM PDT 24 Aug 08 06:06:37 PM PDT 24 3343375792 ps
T390 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3403193733 Aug 08 06:06:15 PM PDT 24 Aug 08 06:06:18 PM PDT 24 2026567733 ps
T391 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3089171913 Aug 08 06:07:26 PM PDT 24 Aug 08 06:07:32 PM PDT 24 2183336252 ps
T235 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.678801345 Aug 08 06:06:55 PM PDT 24 Aug 08 06:08:44 PM PDT 24 85435481032 ps
T392 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.350844114 Aug 08 06:07:23 PM PDT 24 Aug 08 06:07:30 PM PDT 24 2512522949 ps
T122 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3644872308 Aug 08 06:06:28 PM PDT 24 Aug 08 06:06:37 PM PDT 24 2947804908 ps
T393 /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3381689670 Aug 08 06:05:59 PM PDT 24 Aug 08 06:06:09 PM PDT 24 4024327339 ps
T394 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1660254200 Aug 08 06:06:45 PM PDT 24 Aug 08 06:06:53 PM PDT 24 2612193369 ps
T98 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2508360522 Aug 08 06:05:55 PM PDT 24 Aug 08 06:09:16 PM PDT 24 79444935670 ps
T395 /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2775034783 Aug 08 06:05:53 PM PDT 24 Aug 08 06:05:59 PM PDT 24 2063335891 ps
T239 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1074517173 Aug 08 06:06:11 PM PDT 24 Aug 08 06:06:53 PM PDT 24 113826143272 ps
T396 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1393754346 Aug 08 06:06:37 PM PDT 24 Aug 08 06:06:38 PM PDT 24 2774586828 ps
T99 /workspace/coverage/default/31.sysrst_ctrl_stress_all.2687429394 Aug 08 06:06:49 PM PDT 24 Aug 08 06:08:21 PM PDT 24 437031344431 ps
T397 /workspace/coverage/default/12.sysrst_ctrl_stress_all.2410478846 Aug 08 06:06:00 PM PDT 24 Aug 08 06:06:12 PM PDT 24 9102845591 ps
T234 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2838794666 Aug 08 06:07:44 PM PDT 24 Aug 08 06:08:48 PM PDT 24 96401287511 ps
T141 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2048753419 Aug 08 06:06:57 PM PDT 24 Aug 08 06:07:00 PM PDT 24 3583927401 ps
T162 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3223325601 Aug 08 06:06:06 PM PDT 24 Aug 08 06:06:13 PM PDT 24 2614681594 ps
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T163 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.48129208 Aug 08 06:07:34 PM PDT 24 Aug 08 06:09:30 PM PDT 24 47831665907 ps
T164 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3574960173 Aug 08 06:06:54 PM PDT 24 Aug 08 06:07:29 PM PDT 24 52296436416 ps
T140 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3312435163 Aug 08 06:06:47 PM PDT 24 Aug 08 06:06:54 PM PDT 24 4554036625 ps
T68 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.4131586616 Aug 08 06:07:14 PM PDT 24 Aug 08 06:07:42 PM PDT 24 41613728147 ps
T165 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4201412887 Aug 08 06:07:32 PM PDT 24 Aug 08 06:11:39 PM PDT 24 96268857244 ps
T166 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2539879389 Aug 08 06:07:35 PM PDT 24 Aug 08 06:07:42 PM PDT 24 2613326860 ps
T167 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1446042699 Aug 08 06:05:48 PM PDT 24 Aug 08 06:05:50 PM PDT 24 5324674648 ps
T221 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2346674052 Aug 08 06:06:00 PM PDT 24 Aug 08 06:07:18 PM PDT 24 113109355302 ps
T398 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.4105920850 Aug 08 06:07:22 PM PDT 24 Aug 08 06:07:24 PM PDT 24 2126854236 ps
T241 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3213794101 Aug 08 06:06:45 PM PDT 24 Aug 08 06:09:46 PM PDT 24 143468620210 ps
T280 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.938049142 Aug 08 06:06:52 PM PDT 24 Aug 08 06:06:54 PM PDT 24 2534687526 ps
T399 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3375693431 Aug 08 06:05:40 PM PDT 24 Aug 08 06:05:45 PM PDT 24 2479904159 ps
T400 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1880524644 Aug 08 06:06:16 PM PDT 24 Aug 08 06:06:22 PM PDT 24 3514847469 ps
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T402 /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.1862891329 Aug 08 06:06:46 PM PDT 24 Aug 08 06:06:52 PM PDT 24 2109416311 ps
T272 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1440222824 Aug 08 06:06:32 PM PDT 24 Aug 08 06:07:23 PM PDT 24 64344307155 ps
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T404 /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3548719478 Aug 08 06:06:03 PM PDT 24 Aug 08 06:06:07 PM PDT 24 2520166944 ps
T224 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1017525653 Aug 08 06:06:47 PM PDT 24 Aug 08 06:07:08 PM PDT 24 32677186998 ps
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T406 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3928189204 Aug 08 06:07:09 PM PDT 24 Aug 08 06:07:17 PM PDT 24 2459812687 ps
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T283 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.383797640 Aug 08 06:07:17 PM PDT 24 Aug 08 06:07:19 PM PDT 24 6180623421 ps
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T411 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3743159730 Aug 08 06:06:46 PM PDT 24 Aug 08 06:07:04 PM PDT 24 6986729737 ps
T412 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4011487910 Aug 08 06:05:45 PM PDT 24 Aug 08 06:05:47 PM PDT 24 2250066230 ps
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T414 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.4284762774 Aug 08 06:07:10 PM PDT 24 Aug 08 06:07:13 PM PDT 24 2454554754 ps
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T278 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1758430110 Aug 08 06:07:26 PM PDT 24 Aug 08 06:07:29 PM PDT 24 2488283467 ps
T416 /workspace/coverage/default/1.sysrst_ctrl_alert_test.3907584104 Aug 08 06:05:54 PM PDT 24 Aug 08 06:05:56 PM PDT 24 2046816307 ps
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T417 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.571333981 Aug 08 06:06:32 PM PDT 24 Aug 08 06:09:18 PM PDT 24 143078997835 ps
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T418 /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3430726206 Aug 08 06:06:26 PM PDT 24 Aug 08 06:06:28 PM PDT 24 2627665152 ps
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T420 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1704212151 Aug 08 06:06:56 PM PDT 24 Aug 08 06:07:03 PM PDT 24 2614304580 ps
T421 /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.2181408455 Aug 08 06:06:41 PM PDT 24 Aug 08 06:06:43 PM PDT 24 2501108646 ps
T422 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2655934859 Aug 08 06:06:46 PM PDT 24 Aug 08 06:06:48 PM PDT 24 2837299272 ps
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T423 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.498651247 Aug 08 06:05:56 PM PDT 24 Aug 08 06:06:02 PM PDT 24 2052091979 ps
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T424 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3768689077 Aug 08 06:06:45 PM PDT 24 Aug 08 06:06:48 PM PDT 24 2463150098 ps
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T284 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.639970889 Aug 08 06:06:20 PM PDT 24 Aug 08 06:06:22 PM PDT 24 8857119465 ps
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T270 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2117369640 Aug 08 06:06:00 PM PDT 24 Aug 08 06:06:10 PM PDT 24 3655026711 ps
T286 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3356842194 Aug 08 06:06:07 PM PDT 24 Aug 08 06:07:13 PM PDT 24 24285935789 ps
T426 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1486809831 Aug 08 06:06:44 PM PDT 24 Aug 08 06:06:48 PM PDT 24 2614638964 ps
T285 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1398716992 Aug 08 06:06:48 PM PDT 24 Aug 08 06:06:50 PM PDT 24 6826151900 ps
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T240 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1417114475 Aug 08 06:07:27 PM PDT 24 Aug 08 06:13:38 PM PDT 24 137423342419 ps
T125 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.899760122 Aug 08 06:05:56 PM PDT 24 Aug 08 06:07:00 PM PDT 24 357425826592 ps
T77 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2314703659 Aug 08 06:07:38 PM PDT 24 Aug 08 06:08:43 PM PDT 24 25079087550 ps
T271 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1732700171 Aug 08 06:06:52 PM PDT 24 Aug 08 06:06:54 PM PDT 24 3438489077 ps
T313 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2624162829 Aug 08 06:07:40 PM PDT 24 Aug 08 06:09:54 PM PDT 24 192506960348 ps
T427 /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.364506716 Aug 08 06:06:37 PM PDT 24 Aug 08 06:06:47 PM PDT 24 3412354275 ps
T428 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3510816983 Aug 08 06:05:59 PM PDT 24 Aug 08 06:06:06 PM PDT 24 5549427176 ps
T429 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3154936411 Aug 08 06:07:17 PM PDT 24 Aug 08 06:07:18 PM PDT 24 2560436642 ps
T287 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1609187564 Aug 08 06:06:32 PM PDT 24 Aug 08 06:08:08 PM PDT 24 34896645134 ps
T430 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3034575088 Aug 08 06:05:54 PM PDT 24 Aug 08 06:06:04 PM PDT 24 3409425739 ps
T431 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1762145745 Aug 08 06:06:52 PM PDT 24 Aug 08 06:06:59 PM PDT 24 4195787372 ps
T120 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.434429800 Aug 08 06:06:49 PM PDT 24 Aug 08 06:06:53 PM PDT 24 4698258676 ps
T432 /workspace/coverage/default/42.sysrst_ctrl_alert_test.1040042265 Aug 08 06:07:23 PM PDT 24 Aug 08 06:07:25 PM PDT 24 2042595618 ps
T433 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3552108601 Aug 08 06:06:34 PM PDT 24 Aug 08 06:06:37 PM PDT 24 2146098050 ps
T434 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1779512498 Aug 08 06:06:02 PM PDT 24 Aug 08 06:06:04 PM PDT 24 2489679818 ps
T323 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2303111494 Aug 08 06:07:42 PM PDT 24 Aug 08 06:08:43 PM PDT 24 99954097460 ps
T435 /workspace/coverage/default/17.sysrst_ctrl_smoke.1370585162 Aug 08 06:06:28 PM PDT 24 Aug 08 06:06:30 PM PDT 24 2128404105 ps
T78 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.2855595072 Aug 08 06:06:31 PM PDT 24 Aug 08 06:07:34 PM PDT 24 24581843447 ps
T219 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1280253185 Aug 08 06:05:56 PM PDT 24 Aug 08 06:06:14 PM PDT 24 26713134958 ps
T65 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3507181806 Aug 08 06:07:03 PM PDT 24 Aug 08 06:07:10 PM PDT 24 2623050736 ps
T154 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.2657263893 Aug 08 06:06:31 PM PDT 24 Aug 08 06:07:30 PM PDT 24 116862904090 ps
T155 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2203232155 Aug 08 06:06:42 PM PDT 24 Aug 08 06:07:12 PM PDT 24 198127504151 ps
T156 /workspace/coverage/default/36.sysrst_ctrl_alert_test.994468402 Aug 08 06:06:52 PM PDT 24 Aug 08 06:06:58 PM PDT 24 2012167858 ps
T157 /workspace/coverage/default/18.sysrst_ctrl_stress_all.1594806916 Aug 08 06:06:24 PM PDT 24 Aug 08 06:06:26 PM PDT 24 6890788484 ps
T126 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.4125549472 Aug 08 06:07:07 PM PDT 24 Aug 08 06:08:41 PM PDT 24 45076289273 ps
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