Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T8 |
9 |
|
T9 |
9 |
|
T21 |
11 |
| auto[1] |
887 |
1 |
|
|
T8 |
11 |
|
T9 |
11 |
|
T21 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T8 |
9 |
|
T9 |
11 |
|
T21 |
8 |
| auto[1] |
920 |
1 |
|
|
T8 |
11 |
|
T9 |
9 |
|
T21 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T8 |
14 |
|
T9 |
10 |
|
T21 |
7 |
| auto[1] |
905 |
1 |
|
|
T8 |
6 |
|
T9 |
10 |
|
T21 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T8 |
12 |
|
T9 |
11 |
|
T21 |
9 |
| auto[1] |
883 |
1 |
|
|
T8 |
8 |
|
T9 |
9 |
|
T21 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T8 |
11 |
|
T9 |
11 |
|
T21 |
9 |
| auto[1] |
903 |
1 |
|
|
T8 |
9 |
|
T9 |
9 |
|
T21 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
856 |
1 |
|
|
T8 |
8 |
|
T9 |
11 |
|
T21 |
11 |
| auto[1] |
924 |
1 |
|
|
T8 |
12 |
|
T9 |
9 |
|
T21 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
900 |
1 |
|
|
T8 |
12 |
|
T9 |
8 |
|
T21 |
11 |
| auto[1] |
880 |
1 |
|
|
T8 |
8 |
|
T9 |
12 |
|
T21 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T8 |
8 |
|
T9 |
4 |
|
T21 |
8 |
| auto[1] |
866 |
1 |
|
|
T8 |
12 |
|
T9 |
16 |
|
T21 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T8 |
10 |
|
T9 |
9 |
|
T21 |
7 |
| auto[1] |
879 |
1 |
|
|
T8 |
10 |
|
T9 |
11 |
|
T21 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T8 |
14 |
|
T9 |
13 |
|
T21 |
10 |
| auto[1] |
912 |
1 |
|
|
T8 |
6 |
|
T9 |
7 |
|
T21 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
886 |
1 |
|
|
T8 |
11 |
|
T9 |
9 |
|
T21 |
12 |
| auto[1] |
894 |
1 |
|
|
T8 |
9 |
|
T9 |
11 |
|
T21 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T8 |
11 |
|
T9 |
13 |
|
T21 |
10 |
| auto[1] |
909 |
1 |
|
|
T8 |
9 |
|
T9 |
7 |
|
T21 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T8 |
7 |
|
T9 |
9 |
|
T21 |
11 |
| auto[1] |
913 |
1 |
|
|
T8 |
13 |
|
T9 |
11 |
|
T21 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
860 |
1 |
|
|
T8 |
9 |
|
T9 |
11 |
|
T21 |
8 |
| auto[1] |
920 |
1 |
|
|
T8 |
11 |
|
T9 |
9 |
|
T21 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
928 |
1 |
|
|
T8 |
15 |
|
T9 |
10 |
|
T21 |
11 |
| auto[1] |
852 |
1 |
|
|
T8 |
5 |
|
T9 |
10 |
|
T21 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T8 |
13 |
|
T9 |
7 |
|
T21 |
7 |
| auto[1] |
888 |
1 |
|
|
T8 |
7 |
|
T9 |
13 |
|
T21 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
896 |
1 |
|
|
T8 |
10 |
|
T9 |
10 |
|
T21 |
9 |
| auto[1] |
884 |
1 |
|
|
T8 |
10 |
|
T9 |
10 |
|
T21 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
919 |
1 |
|
|
T8 |
9 |
|
T9 |
10 |
|
T21 |
11 |
| auto[1] |
861 |
1 |
|
|
T8 |
11 |
|
T9 |
10 |
|
T21 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
932 |
1 |
|
|
T8 |
11 |
|
T9 |
10 |
|
T21 |
7 |
| auto[1] |
848 |
1 |
|
|
T8 |
9 |
|
T9 |
10 |
|
T21 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T8 |
7 |
|
T9 |
8 |
|
T21 |
8 |
| auto[1] |
900 |
1 |
|
|
T8 |
13 |
|
T9 |
12 |
|
T21 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T8 |
7 |
|
T9 |
6 |
|
T21 |
9 |
| auto[1] |
909 |
1 |
|
|
T8 |
13 |
|
T9 |
14 |
|
T21 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
892 |
1 |
|
|
T8 |
9 |
|
T9 |
10 |
|
T21 |
8 |
| auto[1] |
888 |
1 |
|
|
T8 |
11 |
|
T9 |
10 |
|
T21 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
900 |
1 |
|
|
T8 |
12 |
|
T9 |
8 |
|
T21 |
12 |
| auto[1] |
880 |
1 |
|
|
T8 |
8 |
|
T9 |
12 |
|
T21 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
871 |
1 |
|
|
T8 |
11 |
|
T9 |
13 |
|
T21 |
10 |
| auto[1] |
909 |
1 |
|
|
T8 |
9 |
|
T9 |
7 |
|
T21 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
457 |
1 |
|
|
T8 |
10 |
|
T9 |
6 |
|
T21 |
4 |
| auto[0] |
auto[1] |
471 |
1 |
|
|
T8 |
5 |
|
T9 |
4 |
|
T21 |
7 |
| auto[1] |
auto[0] |
418 |
1 |
|
|
T8 |
4 |
|
T9 |
4 |
|
T21 |
3 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T8 |
1 |
|
T9 |
6 |
|
T21 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T8 |
8 |
|
T9 |
5 |
|
T21 |
3 |
| auto[0] |
auto[1] |
442 |
1 |
|
|
T8 |
5 |
|
T9 |
2 |
|
T21 |
4 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T8 |
4 |
|
T9 |
6 |
|
T21 |
6 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T8 |
3 |
|
T9 |
7 |
|
T21 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T8 |
5 |
|
T9 |
5 |
|
T21 |
4 |
| auto[0] |
auto[1] |
465 |
1 |
|
|
T8 |
5 |
|
T9 |
5 |
|
T21 |
5 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T8 |
6 |
|
T9 |
6 |
|
T21 |
5 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T8 |
4 |
|
T9 |
4 |
|
T21 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
432 |
1 |
|
|
T8 |
3 |
|
T9 |
5 |
|
T21 |
6 |
| auto[0] |
auto[1] |
487 |
1 |
|
|
T8 |
6 |
|
T9 |
5 |
|
T21 |
5 |
| auto[1] |
auto[0] |
424 |
1 |
|
|
T8 |
5 |
|
T9 |
6 |
|
T21 |
5 |
| auto[1] |
auto[1] |
437 |
1 |
|
|
T8 |
6 |
|
T9 |
4 |
|
T21 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
463 |
1 |
|
|
T8 |
6 |
|
T9 |
6 |
|
T21 |
4 |
| auto[0] |
auto[1] |
469 |
1 |
|
|
T8 |
5 |
|
T9 |
4 |
|
T21 |
3 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T8 |
6 |
|
T9 |
2 |
|
T21 |
7 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T8 |
3 |
|
T9 |
8 |
|
T21 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
444 |
1 |
|
|
T8 |
2 |
|
T9 |
3 |
|
T21 |
3 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T8 |
5 |
|
T9 |
5 |
|
T21 |
5 |
| auto[1] |
auto[0] |
470 |
1 |
|
|
T8 |
6 |
|
T9 |
1 |
|
T21 |
5 |
| auto[1] |
auto[1] |
430 |
1 |
|
|
T8 |
7 |
|
T9 |
11 |
|
T21 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T8 |
7 |
|
T9 |
5 |
|
T21 |
4 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T8 |
2 |
|
T9 |
5 |
|
T21 |
4 |
| auto[1] |
auto[0] |
437 |
1 |
|
|
T8 |
7 |
|
T9 |
8 |
|
T21 |
6 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T8 |
4 |
|
T9 |
2 |
|
T21 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
444 |
1 |
|
|
T8 |
7 |
|
T9 |
2 |
|
T21 |
7 |
| auto[0] |
auto[1] |
456 |
1 |
|
|
T8 |
5 |
|
T9 |
6 |
|
T21 |
5 |
| auto[1] |
auto[0] |
442 |
1 |
|
|
T8 |
4 |
|
T9 |
7 |
|
T21 |
5 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T8 |
4 |
|
T9 |
5 |
|
T21 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T8 |
5 |
|
T9 |
3 |
|
T21 |
8 |
| auto[0] |
auto[1] |
436 |
1 |
|
|
T8 |
2 |
|
T9 |
6 |
|
T21 |
3 |
| auto[1] |
auto[0] |
462 |
1 |
|
|
T8 |
4 |
|
T9 |
6 |
|
T21 |
3 |
| auto[1] |
auto[1] |
451 |
1 |
|
|
T8 |
9 |
|
T9 |
5 |
|
T21 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
860 |
1 |
|
|
T8 |
9 |
|
T9 |
11 |
|
T21 |
8 |
| auto[1] |
auto[1] |
920 |
1 |
|
|
T8 |
11 |
|
T9 |
9 |
|
T21 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T8 |
4 |
|
T9 |
3 |
|
T21 |
3 |
| auto[0] |
auto[1] |
432 |
1 |
|
|
T8 |
3 |
|
T9 |
3 |
|
T21 |
6 |
| auto[1] |
auto[0] |
462 |
1 |
|
|
T8 |
6 |
|
T9 |
6 |
|
T21 |
4 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T8 |
7 |
|
T9 |
8 |
|
T21 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
871 |
1 |
|
|
T8 |
11 |
|
T9 |
13 |
|
T21 |
10 |
| auto[1] |
auto[1] |
909 |
1 |
|
|
T8 |
9 |
|
T9 |
7 |
|
T21 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
186 |
1 |
|
|
T9 |
8 |
|
T10 |
11 |
|
T28 |
7 |
| auto[1] |
214 |
1 |
|
|
T9 |
12 |
|
T10 |
9 |
|
T28 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T9 |
11 |
|
T10 |
10 |
|
T28 |
12 |
| auto[1] |
197 |
1 |
|
|
T9 |
9 |
|
T10 |
10 |
|
T28 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
200 |
1 |
|
|
T9 |
10 |
|
T10 |
8 |
|
T28 |
8 |
| auto[1] |
200 |
1 |
|
|
T9 |
10 |
|
T10 |
12 |
|
T28 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
208 |
1 |
|
|
T9 |
12 |
|
T10 |
13 |
|
T28 |
7 |
| auto[1] |
192 |
1 |
|
|
T9 |
8 |
|
T10 |
7 |
|
T28 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T9 |
8 |
|
T10 |
9 |
|
T28 |
11 |
| auto[1] |
197 |
1 |
|
|
T9 |
12 |
|
T10 |
11 |
|
T28 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
198 |
1 |
|
|
T9 |
12 |
|
T10 |
8 |
|
T28 |
12 |
| auto[1] |
202 |
1 |
|
|
T9 |
8 |
|
T10 |
12 |
|
T28 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
180 |
1 |
|
|
T9 |
6 |
|
T10 |
9 |
|
T28 |
11 |
| auto[1] |
220 |
1 |
|
|
T9 |
14 |
|
T10 |
11 |
|
T28 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
211 |
1 |
|
|
T9 |
10 |
|
T10 |
12 |
|
T28 |
12 |
| auto[1] |
189 |
1 |
|
|
T9 |
10 |
|
T10 |
8 |
|
T28 |
8 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
201 |
1 |
|
|
T9 |
12 |
|
T10 |
6 |
|
T28 |
9 |
| auto[1] |
199 |
1 |
|
|
T9 |
8 |
|
T10 |
14 |
|
T28 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
218 |
1 |
|
|
T9 |
10 |
|
T10 |
12 |
|
T28 |
13 |
| auto[1] |
182 |
1 |
|
|
T9 |
10 |
|
T10 |
8 |
|
T28 |
7 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
201 |
1 |
|
|
T9 |
9 |
|
T10 |
8 |
|
T28 |
6 |
| auto[1] |
199 |
1 |
|
|
T9 |
11 |
|
T10 |
12 |
|
T28 |
14 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T9 |
6 |
|
T10 |
9 |
|
T28 |
9 |
| auto[1] |
223 |
1 |
|
|
T9 |
14 |
|
T10 |
11 |
|
T28 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T9 |
10 |
|
T10 |
8 |
|
T28 |
11 |
| auto[1] |
210 |
1 |
|
|
T9 |
10 |
|
T10 |
12 |
|
T28 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T9 |
11 |
|
T10 |
10 |
|
T28 |
12 |
| auto[1] |
197 |
1 |
|
|
T9 |
9 |
|
T10 |
10 |
|
T28 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
193 |
1 |
|
|
T9 |
9 |
|
T10 |
11 |
|
T28 |
8 |
| auto[1] |
207 |
1 |
|
|
T9 |
11 |
|
T10 |
9 |
|
T28 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
193 |
1 |
|
|
T9 |
7 |
|
T10 |
10 |
|
T28 |
9 |
| auto[1] |
207 |
1 |
|
|
T9 |
13 |
|
T10 |
10 |
|
T28 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
176 |
1 |
|
|
T9 |
6 |
|
T10 |
9 |
|
T28 |
13 |
| auto[1] |
224 |
1 |
|
|
T9 |
14 |
|
T10 |
11 |
|
T28 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
199 |
1 |
|
|
T9 |
8 |
|
T10 |
8 |
|
T28 |
6 |
| auto[1] |
201 |
1 |
|
|
T9 |
12 |
|
T10 |
12 |
|
T28 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
196 |
1 |
|
|
T9 |
9 |
|
T10 |
12 |
|
T28 |
9 |
| auto[1] |
204 |
1 |
|
|
T9 |
11 |
|
T10 |
8 |
|
T28 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
213 |
1 |
|
|
T9 |
7 |
|
T10 |
7 |
|
T28 |
12 |
| auto[1] |
187 |
1 |
|
|
T9 |
13 |
|
T10 |
13 |
|
T28 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
193 |
1 |
|
|
T9 |
11 |
|
T10 |
7 |
|
T28 |
8 |
| auto[1] |
207 |
1 |
|
|
T9 |
9 |
|
T10 |
13 |
|
T28 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
206 |
1 |
|
|
T9 |
12 |
|
T10 |
8 |
|
T28 |
8 |
| auto[1] |
194 |
1 |
|
|
T9 |
8 |
|
T10 |
12 |
|
T28 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
191 |
1 |
|
|
T9 |
9 |
|
T10 |
12 |
|
T28 |
7 |
| auto[1] |
209 |
1 |
|
|
T9 |
11 |
|
T10 |
8 |
|
T28 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T9 |
6 |
|
T10 |
9 |
|
T28 |
9 |
| auto[1] |
223 |
1 |
|
|
T9 |
14 |
|
T10 |
11 |
|
T28 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
91 |
1 |
|
|
T9 |
4 |
|
T10 |
5 |
|
T28 |
3 |
| auto[0] |
auto[1] |
102 |
1 |
|
|
T9 |
5 |
|
T10 |
6 |
|
T28 |
5 |
| auto[1] |
auto[0] |
109 |
1 |
|
|
T9 |
6 |
|
T10 |
3 |
|
T28 |
5 |
| auto[1] |
auto[1] |
98 |
1 |
|
|
T9 |
5 |
|
T10 |
6 |
|
T28 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
95 |
1 |
|
|
T9 |
4 |
|
T10 |
7 |
|
T28 |
3 |
| auto[0] |
auto[1] |
98 |
1 |
|
|
T9 |
3 |
|
T10 |
3 |
|
T28 |
6 |
| auto[1] |
auto[0] |
113 |
1 |
|
|
T9 |
8 |
|
T10 |
6 |
|
T28 |
4 |
| auto[1] |
auto[1] |
94 |
1 |
|
|
T9 |
5 |
|
T10 |
4 |
|
T28 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
102 |
1 |
|
|
T9 |
3 |
|
T10 |
3 |
|
T28 |
9 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T9 |
3 |
|
T10 |
6 |
|
T28 |
4 |
| auto[1] |
auto[0] |
101 |
1 |
|
|
T9 |
5 |
|
T10 |
6 |
|
T28 |
2 |
| auto[1] |
auto[1] |
123 |
1 |
|
|
T9 |
9 |
|
T10 |
5 |
|
T28 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
111 |
1 |
|
|
T9 |
6 |
|
T10 |
2 |
|
T28 |
6 |
| auto[0] |
auto[1] |
88 |
1 |
|
|
T9 |
2 |
|
T10 |
6 |
|
T52 |
4 |
| auto[1] |
auto[0] |
87 |
1 |
|
|
T9 |
6 |
|
T10 |
6 |
|
T28 |
6 |
| auto[1] |
auto[1] |
114 |
1 |
|
|
T9 |
6 |
|
T10 |
6 |
|
T28 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
91 |
1 |
|
|
T9 |
3 |
|
T10 |
6 |
|
T28 |
4 |
| auto[0] |
auto[1] |
105 |
1 |
|
|
T9 |
6 |
|
T10 |
6 |
|
T28 |
5 |
| auto[1] |
auto[0] |
89 |
1 |
|
|
T9 |
3 |
|
T10 |
3 |
|
T28 |
7 |
| auto[1] |
auto[1] |
115 |
1 |
|
|
T9 |
8 |
|
T10 |
5 |
|
T28 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
115 |
1 |
|
|
T9 |
4 |
|
T10 |
5 |
|
T28 |
6 |
| auto[0] |
auto[1] |
98 |
1 |
|
|
T9 |
3 |
|
T10 |
2 |
|
T28 |
6 |
| auto[1] |
auto[0] |
96 |
1 |
|
|
T9 |
6 |
|
T10 |
7 |
|
T28 |
6 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T9 |
7 |
|
T10 |
6 |
|
T28 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
111 |
1 |
|
|
T9 |
5 |
|
T10 |
7 |
|
T28 |
5 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T9 |
7 |
|
T10 |
1 |
|
T28 |
3 |
| auto[1] |
auto[0] |
107 |
1 |
|
|
T9 |
5 |
|
T10 |
5 |
|
T28 |
8 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T9 |
3 |
|
T10 |
7 |
|
T28 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
95 |
1 |
|
|
T9 |
3 |
|
T10 |
7 |
|
T28 |
1 |
| auto[0] |
auto[1] |
96 |
1 |
|
|
T9 |
6 |
|
T10 |
5 |
|
T28 |
6 |
| auto[1] |
auto[0] |
106 |
1 |
|
|
T9 |
6 |
|
T10 |
1 |
|
T28 |
5 |
| auto[1] |
auto[1] |
103 |
1 |
|
|
T9 |
5 |
|
T10 |
7 |
|
T28 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
91 |
1 |
|
|
T9 |
3 |
|
T10 |
4 |
|
T28 |
4 |
| auto[0] |
auto[1] |
99 |
1 |
|
|
T9 |
7 |
|
T10 |
4 |
|
T28 |
7 |
| auto[1] |
auto[0] |
95 |
1 |
|
|
T9 |
5 |
|
T10 |
7 |
|
T28 |
3 |
| auto[1] |
auto[1] |
115 |
1 |
|
|
T9 |
5 |
|
T10 |
5 |
|
T28 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
203 |
1 |
|
|
T9 |
11 |
|
T10 |
10 |
|
T28 |
12 |
| auto[1] |
auto[1] |
197 |
1 |
|
|
T9 |
9 |
|
T10 |
10 |
|
T28 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
98 |
1 |
|
|
T9 |
6 |
|
T10 |
2 |
|
T28 |
3 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T9 |
5 |
|
T10 |
5 |
|
T28 |
5 |
| auto[1] |
auto[0] |
103 |
1 |
|
|
T9 |
6 |
|
T10 |
4 |
|
T28 |
6 |
| auto[1] |
auto[1] |
104 |
1 |
|
|
T9 |
3 |
|
T10 |
9 |
|
T28 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
177 |
1 |
|
|
T9 |
6 |
|
T10 |
9 |
|
T28 |
9 |
| auto[1] |
auto[1] |
223 |
1 |
|
|
T9 |
14 |
|
T10 |
11 |
|
T28 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T10 |
9 |
|
T90 |
10 |
|
T27 |
12 |
| auto[1] |
125 |
1 |
|
|
T10 |
11 |
|
T90 |
10 |
|
T27 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T10 |
10 |
|
T90 |
7 |
|
T27 |
5 |
| auto[1] |
124 |
1 |
|
|
T10 |
10 |
|
T90 |
13 |
|
T27 |
15 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T10 |
16 |
|
T90 |
13 |
|
T27 |
10 |
| auto[1] |
105 |
1 |
|
|
T10 |
4 |
|
T90 |
7 |
|
T27 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T10 |
9 |
|
T90 |
10 |
|
T27 |
9 |
| auto[1] |
123 |
1 |
|
|
T10 |
11 |
|
T90 |
10 |
|
T27 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T10 |
10 |
|
T90 |
11 |
|
T27 |
13 |
| auto[1] |
125 |
1 |
|
|
T10 |
10 |
|
T90 |
9 |
|
T27 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T10 |
9 |
|
T90 |
9 |
|
T27 |
11 |
| auto[1] |
117 |
1 |
|
|
T10 |
11 |
|
T90 |
11 |
|
T27 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T10 |
9 |
|
T90 |
9 |
|
T27 |
11 |
| auto[1] |
121 |
1 |
|
|
T10 |
11 |
|
T90 |
11 |
|
T27 |
9 |