Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T1 |
8 |
|
T5 |
5 |
|
T9 |
7 |
| auto[1] |
816 |
1 |
|
|
T1 |
12 |
|
T5 |
15 |
|
T9 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T1 |
13 |
|
T5 |
8 |
|
T9 |
15 |
| auto[1] |
815 |
1 |
|
|
T1 |
7 |
|
T5 |
12 |
|
T9 |
5 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T1 |
9 |
|
T5 |
10 |
|
T9 |
10 |
| auto[1] |
821 |
1 |
|
|
T1 |
11 |
|
T5 |
10 |
|
T9 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T1 |
12 |
|
T5 |
10 |
|
T9 |
9 |
| auto[1] |
780 |
1 |
|
|
T1 |
8 |
|
T5 |
10 |
|
T9 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
835 |
1 |
|
|
T1 |
11 |
|
T5 |
9 |
|
T9 |
6 |
| auto[1] |
825 |
1 |
|
|
T1 |
9 |
|
T5 |
11 |
|
T9 |
14 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
856 |
1 |
|
|
T1 |
6 |
|
T5 |
10 |
|
T9 |
11 |
| auto[1] |
804 |
1 |
|
|
T1 |
14 |
|
T5 |
10 |
|
T9 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T1 |
11 |
|
T5 |
12 |
|
T9 |
9 |
| auto[1] |
798 |
1 |
|
|
T1 |
9 |
|
T5 |
8 |
|
T9 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
838 |
1 |
|
|
T1 |
15 |
|
T5 |
9 |
|
T9 |
10 |
| auto[1] |
822 |
1 |
|
|
T1 |
5 |
|
T5 |
11 |
|
T9 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T1 |
7 |
|
T5 |
10 |
|
T9 |
11 |
| auto[1] |
830 |
1 |
|
|
T1 |
13 |
|
T5 |
10 |
|
T9 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T1 |
11 |
|
T5 |
7 |
|
T9 |
12 |
| auto[1] |
816 |
1 |
|
|
T1 |
9 |
|
T5 |
13 |
|
T9 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
805 |
1 |
|
|
T1 |
5 |
|
T5 |
8 |
|
T9 |
12 |
| auto[1] |
855 |
1 |
|
|
T1 |
15 |
|
T5 |
12 |
|
T9 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T1 |
7 |
|
T5 |
14 |
|
T9 |
9 |
| auto[1] |
815 |
1 |
|
|
T1 |
13 |
|
T5 |
6 |
|
T9 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T1 |
7 |
|
T5 |
10 |
|
T9 |
9 |
| auto[1] |
816 |
1 |
|
|
T1 |
13 |
|
T5 |
10 |
|
T9 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T1 |
13 |
|
T5 |
8 |
|
T9 |
15 |
| auto[1] |
815 |
1 |
|
|
T1 |
7 |
|
T5 |
12 |
|
T9 |
5 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T1 |
9 |
|
T5 |
11 |
|
T9 |
10 |
| auto[1] |
813 |
1 |
|
|
T1 |
11 |
|
T5 |
9 |
|
T9 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T1 |
10 |
|
T5 |
9 |
|
T9 |
9 |
| auto[1] |
826 |
1 |
|
|
T1 |
10 |
|
T5 |
11 |
|
T9 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T1 |
8 |
|
T5 |
15 |
|
T9 |
15 |
| auto[1] |
854 |
1 |
|
|
T1 |
12 |
|
T5 |
5 |
|
T9 |
5 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
815 |
1 |
|
|
T1 |
7 |
|
T5 |
8 |
|
T9 |
12 |
| auto[1] |
845 |
1 |
|
|
T1 |
13 |
|
T5 |
12 |
|
T9 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T1 |
6 |
|
T5 |
12 |
|
T9 |
12 |
| auto[1] |
813 |
1 |
|
|
T1 |
14 |
|
T5 |
8 |
|
T9 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T1 |
8 |
|
T5 |
9 |
|
T9 |
7 |
| auto[1] |
841 |
1 |
|
|
T1 |
12 |
|
T5 |
11 |
|
T9 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T1 |
11 |
|
T5 |
9 |
|
T9 |
9 |
| auto[1] |
802 |
1 |
|
|
T1 |
9 |
|
T5 |
11 |
|
T9 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
817 |
1 |
|
|
T1 |
9 |
|
T5 |
7 |
|
T9 |
8 |
| auto[1] |
843 |
1 |
|
|
T1 |
11 |
|
T5 |
13 |
|
T9 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
854 |
1 |
|
|
T1 |
15 |
|
T5 |
10 |
|
T9 |
4 |
| auto[1] |
806 |
1 |
|
|
T1 |
5 |
|
T5 |
10 |
|
T9 |
16 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T1 |
7 |
|
T5 |
14 |
|
T9 |
9 |
| auto[1] |
815 |
1 |
|
|
T1 |
13 |
|
T5 |
6 |
|
T9 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T1 |
5 |
|
T5 |
6 |
|
T9 |
4 |
| auto[0] |
auto[1] |
417 |
1 |
|
|
T1 |
4 |
|
T5 |
5 |
|
T9 |
6 |
| auto[1] |
auto[0] |
409 |
1 |
|
|
T1 |
4 |
|
T5 |
4 |
|
T9 |
6 |
| auto[1] |
auto[1] |
404 |
1 |
|
|
T1 |
7 |
|
T5 |
5 |
|
T9 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
444 |
1 |
|
|
T1 |
7 |
|
T5 |
5 |
|
T9 |
3 |
| auto[0] |
auto[1] |
390 |
1 |
|
|
T1 |
3 |
|
T5 |
4 |
|
T9 |
6 |
| auto[1] |
auto[0] |
436 |
1 |
|
|
T1 |
5 |
|
T5 |
5 |
|
T9 |
6 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T1 |
5 |
|
T5 |
6 |
|
T9 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
410 |
1 |
|
|
T1 |
6 |
|
T5 |
6 |
|
T9 |
3 |
| auto[0] |
auto[1] |
396 |
1 |
|
|
T1 |
2 |
|
T5 |
9 |
|
T9 |
12 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T1 |
5 |
|
T5 |
3 |
|
T9 |
3 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T1 |
7 |
|
T5 |
2 |
|
T9 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T1 |
3 |
|
T5 |
3 |
|
T9 |
4 |
| auto[0] |
auto[1] |
390 |
1 |
|
|
T1 |
4 |
|
T5 |
5 |
|
T9 |
8 |
| auto[1] |
auto[0] |
431 |
1 |
|
|
T1 |
3 |
|
T5 |
7 |
|
T9 |
7 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T1 |
10 |
|
T5 |
5 |
|
T9 |
1 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T1 |
3 |
|
T5 |
7 |
|
T9 |
6 |
| auto[0] |
auto[1] |
397 |
1 |
|
|
T1 |
3 |
|
T5 |
5 |
|
T9 |
6 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T1 |
8 |
|
T5 |
5 |
|
T9 |
3 |
| auto[1] |
auto[1] |
401 |
1 |
|
|
T1 |
6 |
|
T5 |
3 |
|
T9 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
424 |
1 |
|
|
T1 |
6 |
|
T5 |
4 |
|
T9 |
4 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T1 |
2 |
|
T5 |
5 |
|
T9 |
3 |
| auto[1] |
auto[0] |
414 |
1 |
|
|
T1 |
9 |
|
T5 |
5 |
|
T9 |
6 |
| auto[1] |
auto[1] |
427 |
1 |
|
|
T1 |
3 |
|
T5 |
6 |
|
T9 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
410 |
1 |
|
|
T1 |
5 |
|
T5 |
2 |
|
T9 |
6 |
| auto[0] |
auto[1] |
407 |
1 |
|
|
T1 |
4 |
|
T5 |
5 |
|
T9 |
2 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T1 |
6 |
|
T5 |
5 |
|
T9 |
6 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T1 |
5 |
|
T5 |
8 |
|
T9 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
409 |
1 |
|
|
T1 |
5 |
|
T5 |
4 |
|
T9 |
4 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T1 |
10 |
|
T5 |
6 |
|
T57 |
6 |
| auto[1] |
auto[0] |
396 |
1 |
|
|
T5 |
4 |
|
T9 |
8 |
|
T57 |
8 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T1 |
5 |
|
T5 |
6 |
|
T9 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T1 |
3 |
|
T5 |
3 |
|
T9 |
4 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T1 |
4 |
|
T5 |
7 |
|
T9 |
5 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T1 |
5 |
|
T5 |
2 |
|
T9 |
3 |
| auto[1] |
auto[1] |
391 |
1 |
|
|
T1 |
8 |
|
T5 |
8 |
|
T9 |
8 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
845 |
1 |
|
|
T1 |
13 |
|
T5 |
8 |
|
T9 |
15 |
| auto[1] |
auto[1] |
815 |
1 |
|
|
T1 |
7 |
|
T5 |
12 |
|
T9 |
5 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T1 |
4 |
|
T5 |
3 |
|
T9 |
4 |
| auto[0] |
auto[1] |
424 |
1 |
|
|
T1 |
7 |
|
T5 |
6 |
|
T9 |
5 |
| auto[1] |
auto[0] |
396 |
1 |
|
|
T1 |
3 |
|
T5 |
7 |
|
T9 |
7 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T1 |
6 |
|
T5 |
4 |
|
T9 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
845 |
1 |
|
|
T1 |
7 |
|
T5 |
14 |
|
T9 |
9 |
| auto[1] |
auto[1] |
815 |
1 |
|
|
T1 |
13 |
|
T5 |
6 |
|
T9 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
9 |
| auto[1] |
96 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
12 |
| auto[1] |
85 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T1 |
11 |
|
T9 |
8 |
|
T36 |
13 |
| auto[1] |
86 |
1 |
|
|
T1 |
9 |
|
T9 |
12 |
|
T36 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T1 |
10 |
|
T9 |
9 |
|
T36 |
9 |
| auto[1] |
91 |
1 |
|
|
T1 |
10 |
|
T9 |
11 |
|
T36 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T1 |
9 |
|
T9 |
6 |
|
T36 |
10 |
| auto[1] |
98 |
1 |
|
|
T1 |
11 |
|
T9 |
14 |
|
T36 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
98 |
1 |
|
|
T1 |
13 |
|
T9 |
8 |
|
T36 |
11 |
| auto[1] |
82 |
1 |
|
|
T1 |
7 |
|
T9 |
12 |
|
T36 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
102 |
1 |
|
|
T1 |
13 |
|
T9 |
12 |
|
T36 |
13 |
| auto[1] |
78 |
1 |
|
|
T1 |
7 |
|
T9 |
8 |
|
T36 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T1 |
12 |
|
T9 |
10 |
|
T36 |
10 |
| auto[1] |
88 |
1 |
|
|
T1 |
8 |
|
T9 |
10 |
|
T36 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T1 |
14 |
|
T9 |
12 |
|
T36 |
9 |
| auto[1] |
89 |
1 |
|
|
T1 |
6 |
|
T9 |
8 |
|
T36 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T1 |
10 |
|
T9 |
11 |
|
T36 |
9 |
| auto[1] |
92 |
1 |
|
|
T1 |
10 |
|
T9 |
9 |
|
T36 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
98 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
11 |
| auto[1] |
82 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T1 |
10 |
|
T9 |
9 |
|
T36 |
10 |
| auto[1] |
89 |
1 |
|
|
T1 |
10 |
|
T9 |
11 |
|
T36 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T1 |
8 |
|
T9 |
8 |
|
T36 |
11 |
| auto[1] |
95 |
1 |
|
|
T1 |
12 |
|
T9 |
12 |
|
T36 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
12 |
| auto[1] |
85 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T1 |
9 |
|
T9 |
11 |
|
T36 |
12 |
| auto[1] |
88 |
1 |
|
|
T1 |
11 |
|
T9 |
9 |
|
T36 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
93 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
8 |
| auto[1] |
87 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T1 |
11 |
|
T9 |
9 |
|
T36 |
13 |
| auto[1] |
88 |
1 |
|
|
T1 |
9 |
|
T9 |
11 |
|
T36 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T1 |
9 |
|
T9 |
9 |
|
T36 |
6 |
| auto[1] |
98 |
1 |
|
|
T1 |
11 |
|
T9 |
11 |
|
T36 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
77 |
1 |
|
|
T1 |
10 |
|
T9 |
9 |
|
T36 |
6 |
| auto[1] |
103 |
1 |
|
|
T1 |
10 |
|
T9 |
11 |
|
T36 |
14 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T1 |
9 |
|
T9 |
13 |
|
T36 |
7 |
| auto[1] |
89 |
1 |
|
|
T1 |
11 |
|
T9 |
7 |
|
T36 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T1 |
9 |
|
T9 |
4 |
|
T36 |
15 |
| auto[1] |
81 |
1 |
|
|
T1 |
11 |
|
T9 |
16 |
|
T36 |
5 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T1 |
9 |
|
T9 |
7 |
|
T36 |
10 |
| auto[1] |
86 |
1 |
|
|
T1 |
11 |
|
T9 |
13 |
|
T36 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
96 |
1 |
|
|
T1 |
9 |
|
T9 |
10 |
|
T36 |
12 |
| auto[1] |
84 |
1 |
|
|
T1 |
11 |
|
T9 |
10 |
|
T36 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T1 |
10 |
|
T9 |
9 |
|
T36 |
10 |
| auto[1] |
89 |
1 |
|
|
T1 |
10 |
|
T9 |
11 |
|
T36 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T1 |
5 |
|
T9 |
3 |
|
T36 |
10 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T1 |
4 |
|
T9 |
8 |
|
T36 |
2 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T1 |
6 |
|
T9 |
5 |
|
T36 |
3 |
| auto[1] |
auto[1] |
40 |
1 |
|
|
T1 |
5 |
|
T9 |
4 |
|
T36 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
44 |
1 |
|
|
T1 |
5 |
|
T9 |
3 |
|
T36 |
6 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T1 |
5 |
|
T9 |
7 |
|
T36 |
2 |
| auto[1] |
auto[0] |
45 |
1 |
|
|
T1 |
5 |
|
T9 |
6 |
|
T36 |
3 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T1 |
5 |
|
T9 |
4 |
|
T36 |
9 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T1 |
7 |
|
T9 |
1 |
|
T36 |
6 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T1 |
4 |
|
T9 |
8 |
|
T36 |
7 |
| auto[1] |
auto[0] |
40 |
1 |
|
|
T1 |
2 |
|
T9 |
5 |
|
T36 |
4 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T1 |
7 |
|
T9 |
6 |
|
T36 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T1 |
8 |
|
T9 |
2 |
|
T36 |
3 |
| auto[0] |
auto[1] |
37 |
1 |
|
|
T1 |
1 |
|
T9 |
7 |
|
T36 |
3 |
| auto[1] |
auto[0] |
53 |
1 |
|
|
T1 |
5 |
|
T9 |
6 |
|
T36 |
8 |
| auto[1] |
auto[1] |
45 |
1 |
|
|
T1 |
6 |
|
T9 |
5 |
|
T36 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
43 |
1 |
|
|
T1 |
8 |
|
T9 |
4 |
|
T36 |
4 |
| auto[0] |
auto[1] |
34 |
1 |
|
|
T1 |
2 |
|
T9 |
5 |
|
T36 |
2 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T1 |
5 |
|
T9 |
8 |
|
T36 |
9 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T1 |
5 |
|
T9 |
3 |
|
T36 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T1 |
7 |
|
T9 |
5 |
|
T36 |
3 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T1 |
2 |
|
T9 |
8 |
|
T36 |
4 |
| auto[1] |
auto[0] |
47 |
1 |
|
|
T1 |
5 |
|
T9 |
5 |
|
T36 |
7 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T1 |
6 |
|
T9 |
2 |
|
T36 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T1 |
6 |
|
T9 |
5 |
|
T36 |
5 |
| auto[0] |
auto[1] |
49 |
1 |
|
|
T1 |
3 |
|
T9 |
2 |
|
T36 |
5 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T1 |
4 |
|
T9 |
6 |
|
T36 |
4 |
| auto[1] |
auto[1] |
43 |
1 |
|
|
T1 |
7 |
|
T9 |
7 |
|
T36 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T1 |
6 |
|
T9 |
6 |
|
T36 |
7 |
| auto[0] |
auto[1] |
45 |
1 |
|
|
T1 |
3 |
|
T9 |
4 |
|
T36 |
5 |
| auto[1] |
auto[0] |
47 |
1 |
|
|
T1 |
4 |
|
T9 |
4 |
|
T36 |
4 |
| auto[1] |
auto[1] |
37 |
1 |
|
|
T1 |
7 |
|
T9 |
6 |
|
T36 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T1 |
5 |
|
T9 |
4 |
|
T36 |
4 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T1 |
3 |
|
T9 |
4 |
|
T36 |
7 |
| auto[1] |
auto[0] |
45 |
1 |
|
|
T1 |
5 |
|
T9 |
6 |
|
T36 |
5 |
| auto[1] |
auto[1] |
50 |
1 |
|
|
T1 |
7 |
|
T9 |
6 |
|
T36 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
95 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
12 |
| auto[1] |
auto[1] |
85 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T1 |
4 |
|
T9 |
2 |
|
T36 |
7 |
| auto[0] |
auto[1] |
54 |
1 |
|
|
T1 |
5 |
|
T9 |
2 |
|
T36 |
8 |
| auto[1] |
auto[0] |
46 |
1 |
|
|
T1 |
10 |
|
T9 |
10 |
|
T36 |
2 |
| auto[1] |
auto[1] |
35 |
1 |
|
|
T1 |
1 |
|
T9 |
6 |
|
T36 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
91 |
1 |
|
|
T1 |
10 |
|
T9 |
9 |
|
T36 |
10 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T1 |
10 |
|
T9 |
11 |
|
T36 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T9 |
7 |
|
T282 |
10 |
|
T105 |
7 |
| auto[1] |
46 |
1 |
|
|
T9 |
13 |
|
T282 |
10 |
|
T105 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T9 |
11 |
|
T282 |
11 |
|
T105 |
11 |
| auto[1] |
38 |
1 |
|
|
T9 |
9 |
|
T282 |
9 |
|
T105 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
38 |
1 |
|
|
T9 |
10 |
|
T282 |
7 |
|
T105 |
9 |
| auto[1] |
42 |
1 |
|
|
T9 |
10 |
|
T282 |
13 |
|
T105 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T9 |
14 |
|
T282 |
8 |
|
T105 |
11 |
| auto[1] |
37 |
1 |
|
|
T9 |
6 |
|
T282 |
12 |
|
T105 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
40 |
1 |
|
|
T9 |
13 |
|
T282 |
8 |
|
T105 |
8 |
| auto[1] |
40 |
1 |
|
|
T9 |
7 |
|
T282 |
12 |
|
T105 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
40 |
1 |
|
|
T9 |
9 |
|
T282 |
13 |
|
T105 |
7 |
| auto[1] |
40 |
1 |
|
|
T9 |
11 |
|
T282 |
7 |
|
T105 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
39 |
1 |
|
|
T9 |
15 |
|
T282 |
7 |
|
T105 |
8 |
| auto[1] |
41 |
1 |
|
|
T9 |
5 |
|
T282 |
13 |
|
T105 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
39 |
1 |
|
|
T9 |
8 |
|
T282 |
8 |
|
T105 |
11 |
| auto[1] |
41 |
1 |
|
|
T9 |
12 |
|
T282 |
12 |
|
T105 |
9 |