Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1265

1

T2

11

T20

12

T11

9

auto[1]

2021

1

T5

11

T2

18

T20

8

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2717

1

T5

11

T2

12

T20

20

auto[1]

569

1

T2

17

T11

3

T32

4

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3129

1

T5

11

T2

24

T20

20

auto[1]

157

1

T2

5

T11

3

T34

2

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3057

1

T5

11

T2

29

T20

20

auto[1]

229

1

T11

1

T35

5

T36

4

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3118

1

T5

11

T2

28

T20

20

auto[1]

168

1

T2

1

T37

3

T38

3

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2003

1

T5

2

T2

1

T20

20

auto[1]

1283

1

T5

9

T2

28

T32

21

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1422

1

T2

9

T20

9

T11

11

auto[1]

1864

1

T5

11

T2

20

T20

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1373

1

T5

11

T2

11

T20

7

auto[1]

1913

1

T2

18

T20

13

T11

15

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1358

1

T2

10

T20

11

T11

9

auto[1]

1928

1

T5

11

T2

19

T20

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1395

1

T5

11

T2

8

T20

10

auto[1]

1891

1

T2

21

T20

10

T11

11

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T20

2

T11

1

T35

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T2

1

T326

2

T98

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T11

1

T119

1

T120

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T37

1

T124

1

T94

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T20

2

T70

1

T91

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T248

1

T125

1

T97

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T34

1

T36

2

T91

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T2

1

T37

1

T94

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T11

1

T119

1

T242

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T2

1

T248

1

T288

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T120

2

T245

4

T253

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T2

1

T32

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T20

1

T35

1

T120

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T32

1

T37

1

T327

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T11

1

T35

1

T120

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T2

1

T32

1

T328

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T120

1

T38

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T32

1

T86

1

T248

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T20

1

T11

1

T119

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T32

1

T86

2

T90

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

39

1

T11

1

T34

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T2

1

T37

1

T124

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T20

1

T119

2

T120

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

32

1

T32

1

T86

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T11

1

T69

1

T241

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T2

1

T86

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

76

1

T20

1

T11

1

T119

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T32

1

T86

2

T37

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

33

1

T20

1

T11

1

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T32

1

T86

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T119

2

T38

1

T91

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

75

1

T32

1

T241

8

T125

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T20

1

T242

1

T92

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T32

1

T37

2

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T11

1

T35

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T32

1

T94

1

T75

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T34

1

T119

1

T120

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T37

1

T248

1

T125

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T20

1

T120

1

T38

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T86

1

T248

1

T329

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T11

1

T119

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T86

1

T248

1

T94

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T5

2

T119

1

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

39

1

T5

9

T32

2

T86

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T36

1

T69

1

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T2

1

T86

3

T125

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

68

1

T11

1

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

56

1

T86

1

T37

2

T124

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

36

1

T20

2

T11

1

T119

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T86

1

T37

1

T330

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T11

1

T34

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T32

1

T125

1

T94

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T20

1

T11

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T2

3

T92

3

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

73

1

T34

2

T35

1

T120

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

62

1

T34

9

T243

9

T124

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T2

1

T20

1

T11

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T32

1

T86

1

T248

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

81

1

T20

2

T11

1

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

34

1

T86

1

T248

1

T124

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T20

1

T120

2

T69

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

62

1

T32

2

T248

2

T94

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

306

1

T20

2

T11

3

T35

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T37

1

T326

1

T288

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T250

1

T158

1

T206

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T98

1

T207

1

T99

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T2

1

T331

2

T100

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T248

1

T326

2

T331

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T331

1

T97

1

T332

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T124

1

T327

1

T326

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T125

1

T97

1

T207

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T328

2

T331

1

T98

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T86

1

T124

1

T331

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T207

1

T99

1

T79

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T326

1

T288

1

T331

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T326

1

T333

1

T331

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T32

1

T37

2

T97

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T2

1

T32

1

T245

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T248

1

T239

1

T334

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T124

1

T326

1

T331

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T326

1

T98

1

T99

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T331

2

T330

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T2

1

T77

2

T335

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T2

1

T248

1

T329

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T124

1

T99

1

T336

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T2

1

T242

2

T331

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T94

1

T99

1

T337

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T2

1

T37

1

T248

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

9

1

T37

1

T207

1

T250

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T248

1

T124

1

T326

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T100

1

T337

1

T334

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T2

1

T37

1

T243

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T37

1

T338

1

T77

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T2

1

T124

1

T94

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T98

2

T336

1

T330

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

134

1

T2

9

T32

2

T37

6

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	31	65	67.71	31
Automatically Generated Cross Bins	96	31	65	67.71	31
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

64

1

T20

2

T11

1

T35

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T2

1

T326

2

T98

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T11

1

T119

1

T120

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T37

1

T124

1

T94

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T20

2

T35

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T2

1

T248

1

T125

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T34

1

T36

2

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T2

1

T37

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T11

1

T119

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T248

1

T288

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T120

2

T245

4

T125

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46

1

T2

1

T32

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T20

1

T35

1

T119

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T32

1

T37

1

T125

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

48

1

T11

2

T35

2

T120

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

36

1

T2

1

T32

1

T328

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T120

1

T38

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T86

2

T248

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T20

1

T11

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T32

1

T86

2

T90

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T11

1

T34

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T2

1

T37

1

T124

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T20

1

T11

1

T119

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T32

1

T86

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T11

1

T69

1

T241

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T32

1

T86

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T20

1

T11

1

T119

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T2

1

T32

2

T86

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T20

1

T11

1

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T32

1

T86

1

T248

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

61

1

T119

2

T38

1

T91

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

91

1

T32

1

T124

1

T241

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T20

1

T38

1

T242

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T37

2

T326

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T11

1

T35

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T32

1

T94

1

T75

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T34

1

T119

1

T120

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T2

1

T37

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T20

1

T120

1

T38

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T2

1

T86

1

T248

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T11

1

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T86

1

T248

1

T124

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T5

2

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

48

1

T5

9

T2

1

T32

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T36

1

T69

1

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T2

1

T86

3

T125

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

72

1

T11

1

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T2

1

T86

1

T37

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T20

2

T11

1

T119

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T86

1

T37

2

T207

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T11

1

T34

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T32

1

T248

1

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T20

1

T11

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T2

3

T92

3

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T35

1

T120

2

T70

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

76

1

T2

1

T34

9

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T2

1

T20

1

T11

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T32

1

T86

1

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

91

1

T20

2

T11

1

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

47

1

T2

1

T86

1

T248

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T20

1

T120

2

T69

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

74

1

T32

2

T248

2

T94

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

223

1

T20

2

T11

1

T35

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

137

1

T2

4

T32

2

T37

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T2

5

T326

2

T336

2

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

64

1

T20

2

T11

1

T35

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T2

1

T326

2

T98

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T11

1

T119

1

T120

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T37

1

T124

1

T94

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T20

2

T35

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T2

1

T248

1

T125

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T34

1

T36

2

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T2

1

T37

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T11

1

T119

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T248

1

T288

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

58

1

T120

2

T245

4

T125

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T2

1

T32

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T20

1

T35

1

T119

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T32

1

T37

1

T125

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T11

2

T35

2

T120

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

34

1

T2

1

T32

1

T328

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T120

1

T38

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T86

2

T248

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

67

1

T20

1

T11

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T32

1

T86

2

T90

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T11

1

T34

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T2

1

T37

1

T124

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T20

1

T11

1

T119

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T32

1

T86

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T11

1

T69

1

T241

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T32

1

T86

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T20

1

T11

1

T119

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T2

1

T32

2

T86

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T20

1

T11

1

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T32

1

T86

1

T248

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

42

1

T119

2

T38

1

T91

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

91

1

T32

1

T124

1

T241

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T20

1

T38

1

T242

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T37

2

T326

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T11

1

T35

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T32

1

T94

1

T75

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T34

1

T119

1

T120

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T2

1

T37

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T20

1

T120

1

T38

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T2

1

T86

1

T248

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T11

1

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T86

1

T248

1

T124

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T5

2

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

48

1

T5

9

T2

1

T32

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T36

1

T69

1

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T2

1

T86

3

T125

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

68

1

T11

1

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T2

1

T86

1

T37

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T20

2

T11

1

T119

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T86

1

T37

2

T207

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T11

1

T34

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T32

1

T248

1

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T20

1

T11

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T2

3

T92

3

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

72

1

T34

2

T35

1

T120

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

76

1

T2

1

T34

9

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T2

1

T20

1

T11

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T32

1

T86

1

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

89

1

T20

2

T11

1

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

47

1

T2

1

T86

1

T248

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T20

1

T120

2

T69

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

74

1

T32

2

T248

2

T94

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

172

1

T20

2

T11

3

T86

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

138

1

T2

9

T32

2

T37

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T327

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T328

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T339

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T340

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T37

3

T331

1

T207

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

64

1

T20

2

T11

1

T35

4

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T2

1

T326

2

T98

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T11

1

T119

1

T120

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T37

1

T124

1

T94

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T20

2

T35

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T2

1

T248

1

T125

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T34

1

T36

2

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T2

1

T37

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T11

1

T119

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T248

1

T288

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

59

1

T120

2

T245

2

T125

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46

1

T2

1

T32

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T20

1

T35

1

T119

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T32

1

T37

1

T125

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

60

1

T11

2

T35

2

T120

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35

1

T2

1

T32

1

T328

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T120

1

T38

1

T243

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T86

2

T248

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

67

1

T20

1

T11

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T32

1

T86

2

T90

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T11

1

T34

1

T35

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T2

1

T37

1

T124

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T20

1

T11

1

T119

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T32

1

T86

1

T248

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T11

1

T69

1

T241

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T2

1

T32

1

T86

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

79

1

T20

1

T11

1

T119

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T2

1

T32

2

T86

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T20

1

T11

1

T35

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T32

1

T86

1

T248

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T119

2

T38

1

T91

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

91

1

T32

1

T124

1

T241

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

59

1

T20

1

T38

1

T242

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T32

1

T37

2

T326

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T11

1

T35

1

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T32

1

T94

1

T75

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T34

1

T119

1

T120

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T2

1

T37

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T20

1

T120

1

T38

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T2

1

T86

1

T248

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T11

1

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T86

1

T248

1

T124

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T5

2

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

48

1

T5

9

T2

1

T32

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T36

1

T69

1

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T2

1

T86

3

T125

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T11

1

T35

1

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T2

1

T86

1

T37

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

35

1

T20

2

T11

1

T119

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T86

1

T37

2

T207

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T11

1

T34

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T32

1

T248

1

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T20

1

T11

1

T35

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T2

3

T92

3

T124

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

71

1

T34

2

T35

1

T120

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

76

1

T2

1

T34

9

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T2

1

T20

1

T11

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T32

1

T86

1

T37

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

92

1

T20

2

T11

1

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

47

1

T2

1

T86

1

T248

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T20

1

T120

2

T69

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

74

1

T32

2

T248

2

T94

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

196

1

T20

2

T11

4

T35

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

137

1

T2

8

T32

2

T37

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T341

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T328

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T339

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T342

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T2

1

T37

2

T124

2

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded