Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
661 |
1 |
|
|
T13 |
14 |
|
T14 |
11 |
|
T24 |
12 |
| auto[1] |
659 |
1 |
|
|
T13 |
6 |
|
T14 |
9 |
|
T24 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
662 |
1 |
|
|
T13 |
10 |
|
T14 |
10 |
|
T24 |
12 |
| auto[1] |
658 |
1 |
|
|
T13 |
10 |
|
T14 |
10 |
|
T24 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
669 |
1 |
|
|
T13 |
13 |
|
T14 |
6 |
|
T24 |
13 |
| auto[1] |
651 |
1 |
|
|
T13 |
7 |
|
T14 |
14 |
|
T24 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
656 |
1 |
|
|
T13 |
9 |
|
T14 |
13 |
|
T24 |
14 |
| auto[1] |
664 |
1 |
|
|
T13 |
11 |
|
T14 |
7 |
|
T24 |
6 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
630 |
1 |
|
|
T13 |
10 |
|
T14 |
9 |
|
T24 |
9 |
| auto[1] |
690 |
1 |
|
|
T13 |
10 |
|
T14 |
11 |
|
T24 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
646 |
1 |
|
|
T13 |
11 |
|
T14 |
8 |
|
T24 |
7 |
| auto[1] |
674 |
1 |
|
|
T13 |
9 |
|
T14 |
12 |
|
T24 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
668 |
1 |
|
|
T13 |
8 |
|
T14 |
11 |
|
T24 |
10 |
| auto[1] |
652 |
1 |
|
|
T13 |
12 |
|
T14 |
9 |
|
T24 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
697 |
1 |
|
|
T13 |
11 |
|
T14 |
12 |
|
T24 |
11 |
| auto[1] |
623 |
1 |
|
|
T13 |
9 |
|
T14 |
8 |
|
T24 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
669 |
1 |
|
|
T13 |
10 |
|
T14 |
12 |
|
T24 |
8 |
| auto[1] |
651 |
1 |
|
|
T13 |
10 |
|
T14 |
8 |
|
T24 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
677 |
1 |
|
|
T13 |
10 |
|
T14 |
8 |
|
T24 |
15 |
| auto[1] |
643 |
1 |
|
|
T13 |
10 |
|
T14 |
12 |
|
T24 |
5 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
646 |
1 |
|
|
T13 |
14 |
|
T14 |
8 |
|
T24 |
8 |
| auto[1] |
674 |
1 |
|
|
T13 |
6 |
|
T14 |
12 |
|
T24 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
673 |
1 |
|
|
T13 |
10 |
|
T14 |
12 |
|
T24 |
7 |
| auto[1] |
647 |
1 |
|
|
T13 |
10 |
|
T14 |
8 |
|
T24 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
675 |
1 |
|
|
T13 |
8 |
|
T14 |
8 |
|
T24 |
10 |
| auto[1] |
645 |
1 |
|
|
T13 |
12 |
|
T14 |
12 |
|
T24 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
662 |
1 |
|
|
T13 |
10 |
|
T14 |
10 |
|
T24 |
12 |
| auto[1] |
658 |
1 |
|
|
T13 |
10 |
|
T14 |
10 |
|
T24 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
670 |
1 |
|
|
T13 |
10 |
|
T14 |
8 |
|
T24 |
12 |
| auto[1] |
650 |
1 |
|
|
T13 |
10 |
|
T14 |
12 |
|
T24 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
663 |
1 |
|
|
T13 |
10 |
|
T14 |
11 |
|
T24 |
11 |
| auto[1] |
657 |
1 |
|
|
T13 |
10 |
|
T14 |
9 |
|
T24 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
650 |
1 |
|
|
T13 |
8 |
|
T14 |
11 |
|
T24 |
10 |
| auto[1] |
670 |
1 |
|
|
T13 |
12 |
|
T14 |
9 |
|
T24 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
648 |
1 |
|
|
T13 |
9 |
|
T14 |
14 |
|
T24 |
12 |
| auto[1] |
672 |
1 |
|
|
T13 |
11 |
|
T14 |
6 |
|
T24 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
649 |
1 |
|
|
T13 |
8 |
|
T14 |
7 |
|
T24 |
10 |
| auto[1] |
671 |
1 |
|
|
T13 |
12 |
|
T14 |
13 |
|
T24 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
660 |
1 |
|
|
T13 |
11 |
|
T14 |
6 |
|
T24 |
13 |
| auto[1] |
660 |
1 |
|
|
T13 |
9 |
|
T14 |
14 |
|
T24 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
661 |
1 |
|
|
T13 |
9 |
|
T14 |
10 |
|
T24 |
11 |
| auto[1] |
659 |
1 |
|
|
T13 |
11 |
|
T14 |
10 |
|
T24 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
687 |
1 |
|
|
T13 |
6 |
|
T14 |
7 |
|
T24 |
10 |
| auto[1] |
633 |
1 |
|
|
T13 |
14 |
|
T14 |
13 |
|
T24 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
632 |
1 |
|
|
T13 |
10 |
|
T14 |
5 |
|
T24 |
9 |
| auto[1] |
688 |
1 |
|
|
T13 |
10 |
|
T14 |
15 |
|
T24 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
673 |
1 |
|
|
T13 |
10 |
|
T14 |
12 |
|
T24 |
7 |
| auto[1] |
647 |
1 |
|
|
T13 |
10 |
|
T14 |
8 |
|
T24 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
338 |
1 |
|
|
T13 |
8 |
|
T14 |
3 |
|
T24 |
10 |
| auto[0] |
auto[1] |
332 |
1 |
|
|
T13 |
2 |
|
T14 |
5 |
|
T24 |
2 |
| auto[1] |
auto[0] |
331 |
1 |
|
|
T13 |
5 |
|
T14 |
3 |
|
T24 |
3 |
| auto[1] |
auto[1] |
319 |
1 |
|
|
T13 |
5 |
|
T14 |
9 |
|
T24 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
328 |
1 |
|
|
T13 |
6 |
|
T14 |
8 |
|
T24 |
10 |
| auto[0] |
auto[1] |
335 |
1 |
|
|
T13 |
4 |
|
T14 |
3 |
|
T24 |
1 |
| auto[1] |
auto[0] |
328 |
1 |
|
|
T13 |
3 |
|
T14 |
5 |
|
T24 |
4 |
| auto[1] |
auto[1] |
329 |
1 |
|
|
T13 |
7 |
|
T14 |
4 |
|
T24 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
309 |
1 |
|
|
T13 |
3 |
|
T14 |
4 |
|
T24 |
5 |
| auto[0] |
auto[1] |
341 |
1 |
|
|
T13 |
5 |
|
T14 |
7 |
|
T24 |
5 |
| auto[1] |
auto[0] |
321 |
1 |
|
|
T13 |
7 |
|
T14 |
5 |
|
T24 |
4 |
| auto[1] |
auto[1] |
349 |
1 |
|
|
T13 |
5 |
|
T14 |
4 |
|
T24 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
316 |
1 |
|
|
T13 |
4 |
|
T14 |
5 |
|
T24 |
5 |
| auto[0] |
auto[1] |
332 |
1 |
|
|
T13 |
5 |
|
T14 |
9 |
|
T24 |
7 |
| auto[1] |
auto[0] |
330 |
1 |
|
|
T13 |
7 |
|
T14 |
3 |
|
T24 |
2 |
| auto[1] |
auto[1] |
342 |
1 |
|
|
T13 |
4 |
|
T14 |
3 |
|
T24 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
314 |
1 |
|
|
T13 |
6 |
|
T14 |
4 |
|
T24 |
5 |
| auto[0] |
auto[1] |
335 |
1 |
|
|
T13 |
2 |
|
T14 |
3 |
|
T24 |
5 |
| auto[1] |
auto[0] |
354 |
1 |
|
|
T13 |
2 |
|
T14 |
7 |
|
T24 |
5 |
| auto[1] |
auto[1] |
317 |
1 |
|
|
T13 |
10 |
|
T14 |
6 |
|
T24 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
334 |
1 |
|
|
T13 |
9 |
|
T14 |
4 |
|
T24 |
7 |
| auto[0] |
auto[1] |
326 |
1 |
|
|
T13 |
2 |
|
T14 |
2 |
|
T24 |
6 |
| auto[1] |
auto[0] |
363 |
1 |
|
|
T13 |
2 |
|
T14 |
8 |
|
T24 |
4 |
| auto[1] |
auto[1] |
297 |
1 |
|
|
T13 |
7 |
|
T14 |
6 |
|
T24 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
356 |
1 |
|
|
T13 |
4 |
|
T14 |
4 |
|
T24 |
7 |
| auto[0] |
auto[1] |
331 |
1 |
|
|
T13 |
2 |
|
T14 |
3 |
|
T24 |
3 |
| auto[1] |
auto[0] |
321 |
1 |
|
|
T13 |
6 |
|
T14 |
4 |
|
T24 |
8 |
| auto[1] |
auto[1] |
312 |
1 |
|
|
T13 |
8 |
|
T14 |
9 |
|
T24 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
313 |
1 |
|
|
T13 |
8 |
|
T14 |
3 |
|
T24 |
3 |
| auto[0] |
auto[1] |
319 |
1 |
|
|
T13 |
2 |
|
T14 |
2 |
|
T24 |
6 |
| auto[1] |
auto[0] |
333 |
1 |
|
|
T13 |
6 |
|
T14 |
5 |
|
T24 |
5 |
| auto[1] |
auto[1] |
355 |
1 |
|
|
T13 |
4 |
|
T14 |
10 |
|
T24 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
339 |
1 |
|
|
T13 |
6 |
|
T14 |
4 |
|
T24 |
4 |
| auto[0] |
auto[1] |
336 |
1 |
|
|
T13 |
2 |
|
T14 |
4 |
|
T24 |
6 |
| auto[1] |
auto[0] |
322 |
1 |
|
|
T13 |
8 |
|
T14 |
7 |
|
T24 |
8 |
| auto[1] |
auto[1] |
323 |
1 |
|
|
T13 |
4 |
|
T14 |
5 |
|
T24 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
662 |
1 |
|
|
T13 |
10 |
|
T14 |
10 |
|
T24 |
12 |
| auto[1] |
auto[1] |
658 |
1 |
|
|
T13 |
10 |
|
T14 |
10 |
|
T24 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
327 |
1 |
|
|
T13 |
3 |
|
T14 |
6 |
|
T24 |
3 |
| auto[0] |
auto[1] |
334 |
1 |
|
|
T13 |
6 |
|
T14 |
4 |
|
T24 |
8 |
| auto[1] |
auto[0] |
342 |
1 |
|
|
T13 |
7 |
|
T14 |
6 |
|
T24 |
5 |
| auto[1] |
auto[1] |
317 |
1 |
|
|
T13 |
4 |
|
T14 |
4 |
|
T24 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
673 |
1 |
|
|
T13 |
10 |
|
T14 |
12 |
|
T24 |
7 |
| auto[1] |
auto[1] |
647 |
1 |
|
|
T13 |
10 |
|
T14 |
8 |
|
T24 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
39 |
1 |
|
|
T68 |
6 |
|
T124 |
9 |
|
T168 |
6 |
| auto[1] |
61 |
1 |
|
|
T68 |
14 |
|
T124 |
11 |
|
T168 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T68 |
7 |
|
T124 |
9 |
|
T168 |
9 |
| auto[1] |
53 |
1 |
|
|
T68 |
13 |
|
T124 |
11 |
|
T168 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T68 |
9 |
|
T124 |
14 |
|
T168 |
5 |
| auto[1] |
50 |
1 |
|
|
T68 |
11 |
|
T124 |
6 |
|
T168 |
15 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T68 |
8 |
|
T124 |
13 |
|
T168 |
10 |
| auto[1] |
48 |
1 |
|
|
T68 |
12 |
|
T124 |
7 |
|
T168 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T68 |
10 |
|
T124 |
12 |
|
T168 |
11 |
| auto[1] |
49 |
1 |
|
|
T68 |
10 |
|
T124 |
8 |
|
T168 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T68 |
11 |
|
T124 |
12 |
|
T168 |
9 |
| auto[1] |
47 |
1 |
|
|
T68 |
9 |
|
T124 |
8 |
|
T168 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T68 |
14 |
|
T124 |
12 |
|
T168 |
9 |
| auto[1] |
44 |
1 |
|
|
T68 |
6 |
|
T124 |
8 |
|
T168 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T68 |
12 |
|
T124 |
12 |
|
T168 |
7 |
| auto[1] |
47 |
1 |
|
|
T68 |
8 |
|
T124 |
8 |
|
T168 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
44 |
1 |
|
|
T68 |
9 |
|
T124 |
10 |
|
T168 |
11 |
| auto[1] |
56 |
1 |
|
|
T68 |
11 |
|
T124 |
10 |
|
T168 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T68 |
16 |
|
T124 |
9 |
|
T168 |
11 |
| auto[1] |
41 |
1 |
|
|
T68 |
4 |
|
T124 |
11 |
|
T168 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T68 |
11 |
|
T124 |
9 |
|
T168 |
11 |
| auto[1] |
51 |
1 |
|
|
T68 |
9 |
|
T124 |
11 |
|
T168 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T68 |
10 |
|
T124 |
12 |
|
T168 |
9 |
| auto[1] |
47 |
1 |
|
|
T68 |
10 |
|
T124 |
8 |
|
T168 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T68 |
7 |
|
T124 |
13 |
|
T168 |
8 |
| auto[1] |
53 |
1 |
|
|
T68 |
13 |
|
T124 |
7 |
|
T168 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
47 |
1 |
|
|
T68 |
7 |
|
T124 |
9 |
|
T168 |
9 |
| auto[1] |
53 |
1 |
|
|
T68 |
13 |
|
T124 |
11 |
|
T168 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T68 |
8 |
|
T124 |
11 |
|
T168 |
8 |
| auto[1] |
49 |
1 |
|
|
T68 |
12 |
|
T124 |
9 |
|
T168 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T68 |
7 |
|
T124 |
12 |
|
T168 |
11 |
| auto[1] |
55 |
1 |
|
|
T68 |
13 |
|
T124 |
8 |
|
T168 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T68 |
10 |
|
T124 |
12 |
|
T168 |
9 |
| auto[1] |
46 |
1 |
|
|
T68 |
10 |
|
T124 |
8 |
|
T168 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T68 |
11 |
|
T124 |
10 |
|
T168 |
9 |
| auto[1] |
54 |
1 |
|
|
T68 |
9 |
|
T124 |
10 |
|
T168 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
55 |
1 |
|
|
T68 |
8 |
|
T124 |
8 |
|
T168 |
13 |
| auto[1] |
45 |
1 |
|
|
T68 |
12 |
|
T124 |
12 |
|
T168 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T68 |
14 |
|
T124 |
4 |
|
T168 |
9 |
| auto[1] |
50 |
1 |
|
|
T68 |
6 |
|
T124 |
16 |
|
T168 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T68 |
12 |
|
T124 |
13 |
|
T168 |
6 |
| auto[1] |
51 |
1 |
|
|
T68 |
8 |
|
T124 |
7 |
|
T168 |
14 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T68 |
8 |
|
T124 |
7 |
|
T168 |
14 |
| auto[1] |
50 |
1 |
|
|
T68 |
12 |
|
T124 |
13 |
|
T168 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T68 |
13 |
|
T124 |
11 |
|
T168 |
12 |
| auto[1] |
48 |
1 |
|
|
T68 |
7 |
|
T124 |
9 |
|
T168 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
53 |
1 |
|
|
T68 |
10 |
|
T124 |
12 |
|
T168 |
9 |
| auto[1] |
47 |
1 |
|
|
T68 |
10 |
|
T124 |
8 |
|
T168 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
27 |
1 |
|
|
T68 |
3 |
|
T124 |
9 |
|
T168 |
2 |
| auto[0] |
auto[1] |
24 |
1 |
|
|
T68 |
5 |
|
T124 |
2 |
|
T168 |
6 |
| auto[1] |
auto[0] |
23 |
1 |
|
|
T68 |
6 |
|
T124 |
5 |
|
T168 |
3 |
| auto[1] |
auto[1] |
26 |
1 |
|
|
T68 |
6 |
|
T124 |
4 |
|
T168 |
9 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
25 |
1 |
|
|
T68 |
2 |
|
T124 |
9 |
|
T168 |
6 |
| auto[0] |
auto[1] |
20 |
1 |
|
|
T68 |
5 |
|
T124 |
3 |
|
T168 |
5 |
| auto[1] |
auto[0] |
27 |
1 |
|
|
T68 |
6 |
|
T124 |
4 |
|
T168 |
4 |
| auto[1] |
auto[1] |
28 |
1 |
|
|
T68 |
7 |
|
T124 |
4 |
|
T168 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
25 |
1 |
|
|
T68 |
4 |
|
T124 |
8 |
|
T168 |
4 |
| auto[0] |
auto[1] |
29 |
1 |
|
|
T68 |
6 |
|
T124 |
4 |
|
T168 |
5 |
| auto[1] |
auto[0] |
26 |
1 |
|
|
T68 |
6 |
|
T124 |
4 |
|
T168 |
7 |
| auto[1] |
auto[1] |
20 |
1 |
|
|
T68 |
4 |
|
T124 |
4 |
|
T168 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
22 |
1 |
|
|
T68 |
5 |
|
T124 |
7 |
|
T168 |
3 |
| auto[0] |
auto[1] |
24 |
1 |
|
|
T68 |
6 |
|
T124 |
3 |
|
T168 |
6 |
| auto[1] |
auto[0] |
31 |
1 |
|
|
T68 |
6 |
|
T124 |
5 |
|
T168 |
6 |
| auto[1] |
auto[1] |
23 |
1 |
|
|
T68 |
3 |
|
T124 |
5 |
|
T168 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
31 |
1 |
|
|
T68 |
4 |
|
T124 |
5 |
|
T168 |
8 |
| auto[0] |
auto[1] |
24 |
1 |
|
|
T68 |
4 |
|
T124 |
3 |
|
T168 |
5 |
| auto[1] |
auto[0] |
25 |
1 |
|
|
T68 |
10 |
|
T124 |
7 |
|
T168 |
1 |
| auto[1] |
auto[1] |
20 |
1 |
|
|
T68 |
2 |
|
T124 |
5 |
|
T168 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
27 |
1 |
|
|
T68 |
6 |
|
T124 |
3 |
|
T168 |
5 |
| auto[0] |
auto[1] |
23 |
1 |
|
|
T68 |
8 |
|
T124 |
1 |
|
T168 |
4 |
| auto[1] |
auto[0] |
26 |
1 |
|
|
T68 |
6 |
|
T124 |
9 |
|
T168 |
2 |
| auto[1] |
auto[1] |
24 |
1 |
|
|
T124 |
7 |
|
T168 |
9 |
|
T101 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
28 |
1 |
|
|
T68 |
5 |
|
T124 |
4 |
|
T168 |
7 |
| auto[0] |
auto[1] |
22 |
1 |
|
|
T68 |
3 |
|
T124 |
3 |
|
T168 |
7 |
| auto[1] |
auto[0] |
31 |
1 |
|
|
T68 |
11 |
|
T124 |
5 |
|
T168 |
4 |
| auto[1] |
auto[1] |
19 |
1 |
|
|
T68 |
1 |
|
T124 |
8 |
|
T168 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
24 |
1 |
|
|
T68 |
5 |
|
T124 |
6 |
|
T168 |
6 |
| auto[0] |
auto[1] |
28 |
1 |
|
|
T68 |
8 |
|
T124 |
5 |
|
T168 |
6 |
| auto[1] |
auto[0] |
25 |
1 |
|
|
T68 |
6 |
|
T124 |
3 |
|
T168 |
5 |
| auto[1] |
auto[1] |
23 |
1 |
|
|
T68 |
1 |
|
T124 |
6 |
|
T168 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
16 |
1 |
|
|
T68 |
2 |
|
T124 |
6 |
|
T168 |
1 |
| auto[0] |
auto[1] |
31 |
1 |
|
|
T68 |
5 |
|
T124 |
7 |
|
T168 |
7 |
| auto[1] |
auto[0] |
23 |
1 |
|
|
T68 |
4 |
|
T124 |
3 |
|
T168 |
5 |
| auto[1] |
auto[1] |
30 |
1 |
|
|
T68 |
9 |
|
T124 |
4 |
|
T168 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
47 |
1 |
|
|
T68 |
7 |
|
T124 |
9 |
|
T168 |
9 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T68 |
13 |
|
T124 |
11 |
|
T168 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
22 |
1 |
|
|
T68 |
7 |
|
T124 |
6 |
|
T168 |
3 |
| auto[0] |
auto[1] |
27 |
1 |
|
|
T68 |
5 |
|
T124 |
7 |
|
T168 |
3 |
| auto[1] |
auto[0] |
22 |
1 |
|
|
T68 |
2 |
|
T124 |
4 |
|
T168 |
8 |
| auto[1] |
auto[1] |
29 |
1 |
|
|
T68 |
6 |
|
T124 |
3 |
|
T168 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
53 |
1 |
|
|
T68 |
10 |
|
T124 |
12 |
|
T168 |
9 |
| auto[1] |
auto[1] |
47 |
1 |
|
|
T68 |
10 |
|
T124 |
8 |
|
T168 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T68 |
11 |
| auto[1] |
9 |
1 |
|
|
T68 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T68 |
10 |
| auto[1] |
10 |
1 |
|
|
T68 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T68 |
12 |
| auto[1] |
8 |
1 |
|
|
T68 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T68 |
13 |
| auto[1] |
7 |
1 |
|
|
T68 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T68 |
9 |
| auto[1] |
11 |
1 |
|
|
T68 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T68 |
13 |
| auto[1] |
7 |
1 |
|
|
T68 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T68 |
11 |
| auto[1] |
9 |
1 |
|
|
T68 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T68 |
8 |
| auto[1] |
12 |
1 |
|
|
T68 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T68 |
10 |
| auto[1] |
10 |
1 |
|
|
T68 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T68 |
8 |
| auto[1] |
12 |
1 |
|
|
T68 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T68 |
10 |
| auto[1] |
10 |
1 |
|
|
T68 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
7 |
1 |
|
|
T68 |
7 |
| auto[1] |
13 |
1 |
|
|
T68 |
13 |