| | | | | | |
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 1213091022 | 4662159 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 1213090441 | 4939 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 1213091022 | 19127046 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 1213091022 | 175872 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 1213090441 | 5135 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 1213091022 | 21898547 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 1213091022 | 548523 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 1213091022 | 21898547 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 1213091022 | 548523 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 1213091022 | 548523 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 1213091022 | 548523 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 1213090441 | 3312 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 1213090441 | 3228 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 1213090441 | 256889 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 1213090441 | 256885 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 1213090441 | 135793 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1306685 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1217 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1217 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1217 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1111 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1227 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1216715 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1109 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1109 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1109 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1005 | 0 | 0 |
|
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1119 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1933125 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1855 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1855 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1855 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1753 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1866 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1904712 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1740 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1856 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1869307 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1822 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1822 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1822 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1717 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1832 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1888190 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1849 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1849 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1849 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1745 | 0 | 0 |
|
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1860 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1884580 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1846 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1744 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1856 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1896652 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1843 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1843 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1843 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1739 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1854 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1887339 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1869 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1869 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1869 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1763 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1878 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1857118 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1843 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1843 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1843 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1743 | 0 | 0 |
|
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1854 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1418355 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1329 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1329 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1329 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1225 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1339 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1390654 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1320 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1320 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1320 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1219 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1330 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1361682 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1316 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1316 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1316 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1210 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1325 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1395323 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1313 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1313 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1313 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1206 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1324 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 7241630 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 7590 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 7590 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 7590 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 7481 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 7597 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 7436151 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 7762 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 7762 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 7762 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 7652 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 7770 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 7192117 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 7573 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 7573 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 7573 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 7461 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 7582 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 7002213 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 7533 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 7533 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 7533 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 7428 | 0 | 0 |
|
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 7541 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 7869461 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 8173 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 8173 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 8173 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 8068 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 8183 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 8014647 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 8341 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 8341 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 8341 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 8235 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 8351 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 7759520 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 8105 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 8105 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 8105 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 7993 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 8115 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 7541578 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 8069 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 8069 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 8069 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 7966 | 0 | 0 |
|
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 8078 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1964197 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1945 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1841 | 0 | 0 |
|
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1954 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1082392 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1017 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1017 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1017 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 915 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1026 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1948610 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1928 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1928 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1928 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1822 | 0 | 0 |
|
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1936 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 2050416 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 2215 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 2215 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 2215 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 2113 | 0 | 0 |
|
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 2227 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 3759226 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 4130 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 4130 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 4130 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 4027 | 0 | 0 |
|
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 4141 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 4790574 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 5192 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 5192 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 5192 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 5090 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 5204 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 3753821 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 4101 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 4101 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 4101 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 3999 | 0 | 0 |
|
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 4114 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 918 | 918 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1155666 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1024 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 1024 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 1024 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1033 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1109334 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 985 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 985 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 985 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 887 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 996 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1100018 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 979 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 979 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 979 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 873 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 990 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1112044 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 992 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 1213090441 | 992 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 6175620 | 992 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 890 | 0 | 0 |
|
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1003 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.BusySrcReqChk_A
| 0 | 0 | 1213090441 | 1105134 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.DstReqKnown_A
| 0 | 0 | 6175620 | 5507579 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 1213090441 | 1111 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.SrcBusyKnown_A
| 0 | 0 | 1213090441 | 1212644146 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 6175620 | 644 | 0 | 917 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 6175620 | 644 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 1213090441 | 1755 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 6175620 | 867 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 6175620 | 1004 | 0 | 0 |
|
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 1213090441 | 1119 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 1213090441 | 121092 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntClr_A
| 0 | 0 | 5916283 | 185 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntIncr_A
| 0 | 0 | 5916283 | 117559 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.CntNoWrap_A
| 0 | 0 | 5916283 | 5441290 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectStDropOut_A
| 0 | 0 | 5916283 | 2 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedOut_A
| 0 | 0 | 5916283 | 518 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DetectedPulseOut_A
| 0 | 0 | 5916283 | 75 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledIdleSt_A
| 0 | 0 | 5916283 | 5319541 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.DisabledNoDetection_A
| 0 | 0 | 5916283 | 5321502 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDebounceSt_A
| 0 | 0 | 5916283 | 109 | 0 | 0 |
|
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect.EnterDetectSt_A
| 0 | 0 | 5916283 | 77 | 0 | 0 |
|