Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T27,T29,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T27,T29,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T27,T29,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T29,T55
1	0	Covered	T5,T6,T1
1	1	Covered	T27,T29,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T29,T55
0	1	Covered	T133,T134
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T29,T55
0	1	Covered	T27,T29,T55
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T29,T55
1	-	Covered	T27,T29,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T29,T55
DetectSt	168	Covered	T27,T29,T55
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T27,T29,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T29,T55
DebounceSt->IdleSt	163	Covered	T29,T56,T117
DetectSt->IdleSt	186	Covered	T133,T134
DetectSt->StableSt	191	Covered	T27,T29,T55
IdleSt->DebounceSt	148	Covered	T27,T29,T55
StableSt->IdleSt	206	Covered	T27,T29,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T29,T55
0	1	Covered	T27,T29,T55
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T29,T55
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T29,T55
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T29,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T56,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T29,T55
DetectSt	-	-	-	-	1	-	-	Covered	T133,T134
DetectSt	-	-	-	-	0	1	-	Covered	T27,T29,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T29,T55
StableSt	-	-	-	-	-	-	0	Covered	T27,T29,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	185	0	0
CntIncr_A	5916283	117559	0	0
CntNoWrap_A	5916283	5441290	0	0
DetectStDropOut_A	5916283	2	0	0
DetectedOut_A	5916283	518	0	0
DetectedPulseOut_A	5916283	75	0	0
DisabledIdleSt_A	5916283	5319541	0	0
DisabledNoDetection_A	5916283	5321502	0	0
EnterDebounceSt_A	5916283	109	0	0
EnterDetectSt_A	5916283	77	0	0
EnterStableSt_A	5916283	75	0	0
PulseIsPulse_A	5916283	75	0	0
StayInStableSt	5916283	443	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5916283	5741	0	0
gen_low_level_sva.LowLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	75	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	185	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	2	0	0
T28	672	0	0	0
T29	0	3	0	0
T52	27581	0	0	0
T55	0	4	0	0
T56	0	3	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	6	0	0
T61	0	4	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	3	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	117559	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	55	0	0
T28	672	0	0	0
T29	0	134	0	0
T52	27581	0	0	0
T55	0	134	0	0
T56	0	177	0	0
T57	0	70	0	0
T58	0	96	0	0
T59	0	53869	0	0
T61	0	123	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	139	0	0
T118	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441290	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	2	0	0
T133	716	1	0	0
T134	0	1	0	0
T135	1312	0	0	0
T136	999	0	0	0
T137	523	0	0	0
T138	502	0	0	0
T139	14764	0	0	0
T140	492	0	0	0
T141	402	0	0	0
T142	494	0	0	0
T143	2731	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	518	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	5	0	0
T28	672	0	0	0
T29	0	4	0	0
T52	27581	0	0	0
T55	0	25	0	0
T56	0	10	0	0
T57	0	2	0	0
T58	0	5	0	0
T59	0	13	0	0
T61	0	20	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	2	0	0
T118	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	75	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	1	0	0
T28	672	0	0	0
T29	0	1	0	0
T52	27581	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0
T61	0	2	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	1	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5319541	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5321502	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	109	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	1	0	0
T28	672	0	0	0
T29	0	2	0	0
T52	27581	0	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0
T61	0	2	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	2	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	77	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	1	0	0
T28	672	0	0	0
T29	0	1	0	0
T52	27581	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0
T61	0	2	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	1	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	75	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	1	0	0
T28	672	0	0	0
T29	0	1	0	0
T52	27581	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0
T61	0	2	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	1	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	75	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	1	0	0
T28	672	0	0	0
T29	0	1	0	0
T52	27581	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0
T61	0	2	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	1	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	443	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	4	0	0
T28	672	0	0	0
T29	0	3	0	0
T52	27581	0	0	0
T55	0	23	0	0
T56	0	9	0	0
T57	0	1	0	0
T58	0	4	0	0
T59	0	10	0	0
T61	0	18	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	1	0	0
T118	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5741	0	0
T1	20180	11	0	0
T2	28487	14	0	0
T3	25937	31	0	0
T4	746	2	0	0
T5	423	4	0	0
T6	422	3	0	0
T7	17991	32	0	0
T13	527	5	0	0
T14	489	5	0	0
T15	404	0	0	0
T16	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	75	0	0
T12	21456	0	0	0
T23	494	0	0	0
T24	492	0	0	0
T27	579	1	0	0
T28	672	0	0	0
T29	0	1	0	0
T52	27581	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	3	0	0
T61	0	2	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T117	0	1	0	0
T118	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T9,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T9,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T9,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T22
1	0	Covered	T5,T6,T1
1	1	Covered	T9,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T22
0	1	Covered	T22,T116,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T22
0	1	Unreachable
1	0	Covered	T9,T21,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T21,T22
DetectSt	168	Covered	T9,T21,T22
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T9,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T21,T22
DebounceSt->IdleSt	163	Covered	T116,T105,T149
DetectSt->IdleSt	186	Covered	T22,T116,T115
DetectSt->StableSt	191	Covered	T9,T21,T22
IdleSt->DebounceSt	148	Covered	T9,T21,T22
StableSt->IdleSt	206	Covered	T9,T21,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T21,T22
0	1	Covered	T9,T21,T22
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T21,T22
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T149,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T22,T116,T115
DetectSt	-	-	-	-	0	1	-	Covered	T9,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T9,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	122	0	0
CntIncr_A	5916283	145306	0	0
CntNoWrap_A	5916283	5441353	0	0
DetectStDropOut_A	5916283	14	0	0
DetectedOut_A	5916283	231568	0	0
DetectedPulseOut_A	5916283	38	0	0
DisabledIdleSt_A	5916283	4739646	0	0
DisabledNoDetection_A	5916283	4741644	0	0
EnterDebounceSt_A	5916283	71	0	0
EnterDetectSt_A	5916283	52	0	0
EnterStableSt_A	5916283	38	0	0
PulseIsPulse_A	5916283	38	0	0
StayInStableSt	5916283	231530	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5916283	5741	0	0
gen_low_level_sva.LowLevelEvent_A	5916283	5443473	0	0
gen_sticky_sva.StableStDropOut_A	5916283	316628	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	122	0	0
T9	1451	2	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	2	0	0
T22	0	6	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	4	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	2	0	0
T100	0	4	0	0
T101	0	4	0	0
T102	0	2	0	0
T103	0	2	0	0
T104	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	145306	0	0
T9	1451	74	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	12	0	0
T22	0	189	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	74	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	87	0	0
T100	0	174	0	0
T101	0	156	0	0
T102	0	91	0	0
T103	0	83	0	0
T104	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441353	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	14	0	0
T22	1471	2	0	0
T47	2047	0	0	0
T55	744	0	0	0
T92	512	0	0	0
T96	9855	0	0	0
T97	32674	0	0	0
T98	9028	0	0	0
T115	0	3	0	0
T116	0	1	0	0
T144	15512	0	0	0
T150	0	1	0	0
T151	0	3	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	25489	0	0	0
T155	553	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	231568	0	0
T9	1451	513	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	51	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	358	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	306	0	0
T100	0	326	0	0
T101	0	467	0	0
T102	0	425	0	0
T103	0	200	0	0
T104	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	38	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4739646	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4741644	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	71	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	3	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	52	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	3	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	38	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	38	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	231530	0	0
T9	1451	512	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	50	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	356	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	305	0	0
T100	0	324	0	0
T101	0	465	0	0
T102	0	424	0	0
T103	0	199	0	0
T104	0	43	0	0
T116	0	59	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5741	0	0
T1	20180	11	0	0
T2	28487	14	0	0
T3	25937	31	0	0
T4	746	2	0	0
T5	423	4	0	0
T6	422	3	0	0
T7	17991	32	0	0
T13	527	5	0	0
T14	489	5	0	0
T15	404	0	0	0
T16	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	316628	0	0
T9	1451	420	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	217	0	0
T22	0	65	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	725	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	65	0	0
T100	0	74	0	0
T101	0	104	0	0
T102	0	109	0	0
T103	0	53	0	0
T104	0	54	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T9,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T9,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T21,T22,T71

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T22
1	0	Covered	T5,T6,T4
1	1	Covered	T9,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T71
0	1	Covered	T100,T114,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T71
0	1	Unreachable
1	0	Covered	T21,T22,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T21,T22
DetectSt	168	Covered	T21,T22,T71
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T21,T22,T71

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T22,T71
DebounceSt->IdleSt	163	Covered	T9,T100,T105
DetectSt->IdleSt	186	Covered	T100,T114,T115
DetectSt->StableSt	191	Covered	T21,T22,T71
IdleSt->DebounceSt	148	Covered	T9,T21,T22
StableSt->IdleSt	206	Covered	T21,T22,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T21,T22
0	1	Covered	T9,T21,T22
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T71
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T22,T71
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T100,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T100,T114,T115
DetectSt	-	-	-	-	0	1	-	Covered	T21,T22,T71
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T22,T71
StableSt	-	-	-	-	-	-	0	Covered	T21,T22,T71
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	124	0	0
CntIncr_A	5916283	3316	0	0
CntNoWrap_A	5916283	5441351	0	0
DetectStDropOut_A	5916283	12	0	0
DetectedOut_A	5916283	3219	0	0
DetectedPulseOut_A	5916283	34	0	0
DisabledIdleSt_A	5916283	4739646	0	0
DisabledNoDetection_A	5916283	4741644	0	0
EnterDebounceSt_A	5916283	79	0	0
EnterDetectSt_A	5916283	46	0	0
EnterStableSt_A	5916283	34	0	0
PulseIsPulse_A	5916283	34	0	0
StayInStableSt	5916283	3185	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_sticky_sva.StableStDropOut_A	5916283	685846	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	124	0	0
T9	1451	5	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	4	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	2	0	0
T100	0	7	0	0
T101	0	4	0	0
T102	0	2	0	0
T103	0	2	0	0
T104	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3316	0	0
T9	1451	350	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	54	0	0
T22	0	17	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	36	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	15	0	0
T100	0	88	0	0
T101	0	114	0	0
T102	0	37	0	0
T103	0	73	0	0
T104	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441351	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	12	0	0
T100	1632	3	0	0
T101	1959	0	0	0
T114	0	1	0	0
T115	0	4	0	0
T117	709	0	0	0
T156	0	3	0	0
T157	0	1	0	0
T158	433	0	0	0
T159	513	0	0	0
T160	451	0	0	0
T161	15420	0	0	0
T162	408	0	0	0
T163	496	0	0	0
T164	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3219	0	0
T21	823	168	0	0
T22	0	42	0	0
T35	18631	0	0	0
T37	22727	0	0	0
T38	37173	0	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T71	0	128	0	0
T99	0	70	0	0
T101	0	235	0	0
T102	0	155	0	0
T103	0	127	0	0
T104	0	31	0	0
T116	0	274	0	0
T145	0	51	0	0
T146	422	0	0	0
T147	628	0	0	0
T148	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	34	0	0
T21	823	1	0	0
T22	0	1	0	0
T35	18631	0	0	0
T37	22727	0	0	0
T38	37173	0	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T71	0	2	0	0
T99	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T116	0	2	0	0
T145	0	1	0	0
T146	422	0	0	0
T147	628	0	0	0
T148	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4739646	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4741644	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	79	0	0
T9	1451	5	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	4	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	46	0	0
T21	823	1	0	0
T22	0	1	0	0
T35	18631	0	0	0
T37	22727	0	0	0
T38	37173	0	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T71	0	2	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T116	0	2	0	0
T146	422	0	0	0
T147	628	0	0	0
T148	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	34	0	0
T21	823	1	0	0
T22	0	1	0	0
T35	18631	0	0	0
T37	22727	0	0	0
T38	37173	0	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T71	0	2	0	0
T99	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T116	0	2	0	0
T145	0	1	0	0
T146	422	0	0	0
T147	628	0	0	0
T148	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	34	0	0
T21	823	1	0	0
T22	0	1	0	0
T35	18631	0	0	0
T37	22727	0	0	0
T38	37173	0	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T71	0	2	0	0
T99	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T116	0	2	0	0
T145	0	1	0	0
T146	422	0	0	0
T147	628	0	0	0
T148	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3185	0	0
T21	823	167	0	0
T22	0	41	0	0
T35	18631	0	0	0
T37	22727	0	0	0
T38	37173	0	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T71	0	126	0	0
T99	0	69	0	0
T101	0	233	0	0
T102	0	154	0	0
T103	0	126	0	0
T104	0	30	0	0
T116	0	272	0	0
T145	0	50	0	0
T146	422	0	0	0
T147	628	0	0	0
T148	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	685846	0	0
T21	823	56	0	0
T22	0	326	0	0
T35	18631	0	0	0
T37	22727	0	0	0
T38	37173	0	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T71	0	1009	0	0
T99	0	376	0	0
T101	0	387	0	0
T102	0	438	0	0
T103	0	140	0	0
T104	0	57	0	0
T116	0	418	0	0
T145	0	58	0	0
T146	422	0	0	0
T147	628	0	0	0
T148	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T9,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T9,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T9,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T21,T22
1	0	Covered	T5,T6,T1
1	1	Covered	T9,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T22
0	1	Covered	T100,T112,T113
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T21,T22
0	1	Unreachable
1	0	Covered	T9,T21,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T21,T22
DetectSt	168	Covered	T9,T21,T22
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T9,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T21,T22
DebounceSt->IdleSt	163	Covered	T100,T104,T116
DetectSt->IdleSt	186	Covered	T100,T112,T113
DetectSt->StableSt	191	Covered	T9,T21,T22
IdleSt->DebounceSt	148	Covered	T9,T21,T22
StableSt->IdleSt	206	Covered	T9,T21,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T21,T22
0	1	Covered	T9,T21,T22
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T21,T22
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T104,T116
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T100,T112,T113
DetectSt	-	-	-	-	0	1	-	Covered	T9,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T9,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	109	0	0
CntIncr_A	5916283	82676	0	0
CntNoWrap_A	5916283	5441366	0	0
DetectStDropOut_A	5916283	7	0	0
DetectedOut_A	5916283	246853	0	0
DetectedPulseOut_A	5916283	32	0	0
DisabledIdleSt_A	5916283	4739646	0	0
DisabledNoDetection_A	5916283	4741644	0	0
EnterDebounceSt_A	5916283	71	0	0
EnterDetectSt_A	5916283	39	0	0
EnterStableSt_A	5916283	32	0	0
PulseIsPulse_A	5916283	32	0	0
StayInStableSt	5916283	246821	0	0
gen_high_event_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_sticky_sva.StableStDropOut_A	5916283	61827	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	109	0	0
T9	1451	2	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	4	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	2	0	0
T100	0	5	0	0
T101	0	4	0	0
T102	0	2	0	0
T103	0	2	0	0
T104	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	82676	0	0
T9	1451	76	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	50	0	0
T22	0	62	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	140	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	44	0	0
T100	0	261	0	0
T101	0	42	0	0
T102	0	21	0	0
T103	0	72	0	0
T104	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441366	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	7	0	0
T100	1632	1	0	0
T101	1959	0	0	0
T112	0	2	0	0
T113	0	2	0	0
T117	709	0	0	0
T153	0	1	0	0
T158	433	0	0	0
T159	513	0	0	0
T160	451	0	0	0
T161	15420	0	0	0
T162	408	0	0	0
T163	496	0	0	0
T164	491	0	0	0
T165	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	246853	0	0
T9	1451	624	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	103	0	0
T22	0	287	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	936	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	166	0	0
T100	0	88	0	0
T101	0	141	0	0
T102	0	180	0	0
T103	0	183	0	0
T145	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	32	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T145	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4739646	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4741644	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	71	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	39	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	32	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T145	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	32	0	0
T9	1451	1	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	2	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T145	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	246821	0	0
T9	1451	623	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	102	0	0
T22	0	286	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	934	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	165	0	0
T100	0	87	0	0
T101	0	139	0	0
T102	0	179	0	0
T103	0	182	0	0
T145	0	59	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	61827	0	0
T9	1451	318	0	0
T10	642	0	0	0
T11	506	0	0	0
T21	0	130	0	0
T22	0	48	0	0
T34	1679	0	0	0
T69	612	0	0	0
T70	908	0	0	0
T71	0	104	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T99	0	262	0	0
T100	0	119	0	0
T101	0	574	0	0
T102	0	441	0	0
T103	0	90	0	0
T145	0	41	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T41,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T8,T41,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T41,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T41,T50
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T41,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T41,T50
0	1	Covered	T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T41,T50
0	1	Covered	T8,T41,T167
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T41,T50
1	-	Covered	T8,T41,T167

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T41,T50
DetectSt	168	Covered	T8,T41,T50
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T8,T41,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T41,T50
DebounceSt->IdleSt	163	Covered	T105,T168,T169
DetectSt->IdleSt	186	Covered	T166
DetectSt->StableSt	191	Covered	T8,T41,T50
IdleSt->DebounceSt	148	Covered	T8,T41,T50
StableSt->IdleSt	206	Covered	T8,T41,T167

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T41,T50
0	1	Covered	T8,T41,T50
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T41,T50
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T41,T50
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T41,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T168,T169,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T41,T50
DetectSt	-	-	-	-	1	-	-	Covered	T166
DetectSt	-	-	-	-	0	1	-	Covered	T8,T41,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T41,T167
StableSt	-	-	-	-	-	-	0	Covered	T8,T41,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	63	0	0
CntIncr_A	5916283	29642	0	0
CntNoWrap_A	5916283	5441412	0	0
DetectStDropOut_A	5916283	1	0	0
DetectedOut_A	5916283	1872	0	0
DetectedPulseOut_A	5916283	28	0	0
DisabledIdleSt_A	5916283	5301223	0	0
DisabledNoDetection_A	5916283	5303183	0	0
EnterDebounceSt_A	5916283	34	0	0
EnterDetectSt_A	5916283	29	0	0
EnterStableSt_A	5916283	28	0	0
PulseIsPulse_A	5916283	28	0	0
StayInStableSt	5916283	1832	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	63	0	0
T8	612	2	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	2	0	0
T45	0	2	0	0
T50	0	2	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	4	0	0
T167	0	2	0	0
T171	0	4	0	0
T172	0	4	0	0
T173	0	2	0	0
T174	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	29642	0	0
T8	612	27	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	16	0	0
T45	0	41	0	0
T50	0	92	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	22	0	0
T167	0	22	0	0
T171	0	100	0	0
T172	0	54	0	0
T173	0	70	0	0
T174	0	136	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441412	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1	0	0
T166	887	1	0	0
T175	2023	0	0	0
T176	15236	0	0	0
T177	14815	0	0	0
T178	681	0	0	0
T179	402	0	0	0
T180	658	0	0	0
T181	1159	0	0	0
T182	422	0	0	0
T183	714	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1872	0	0
T8	612	79	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	66	0	0
T45	0	82	0	0
T50	0	49	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	84	0	0
T167	0	8	0	0
T171	0	136	0	0
T172	0	44	0	0
T173	0	143	0	0
T174	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	28	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	2	0	0
T167	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5301223	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5303183	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	34	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	2	0	0
T167	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	29	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	2	0	0
T167	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	28	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	2	0	0
T167	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	28	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	2	0	0
T167	0	1	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	1	0	0
T174	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1832	0	0
T8	612	78	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	65	0	0
T45	0	81	0	0
T50	0	47	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	81	0	0
T167	0	7	0	0
T171	0	133	0	0
T172	0	42	0	0
T173	0	141	0	0
T174	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	15	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T107	0	1	0	0
T167	0	1	0	0
T171	0	1	0	0
T172	0	2	0	0
T174	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T47,T39,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T47,T39,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T47,T39,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T47,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T47,T39,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T39,T48
0	1	Covered	T107,T181
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T39,T48
0	1	Covered	T47,T39,T186
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T39,T48
1	-	Covered	T47,T39,T186

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T47,T39,T48
DetectSt	168	Covered	T47,T39,T48
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T47,T39,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T39,T48
DebounceSt->IdleSt	163	Covered	T171,T105,T187
DetectSt->IdleSt	186	Covered	T107,T181
DetectSt->StableSt	191	Covered	T47,T39,T48
IdleSt->DebounceSt	148	Covered	T47,T39,T48
StableSt->IdleSt	206	Covered	T47,T39,T186

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T47,T39,T48
0	1	Covered	T47,T39,T48
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T47,T39,T48
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T47,T39,T48
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T39,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T171,T187,T188
DebounceSt	-	0	0	-	-	-	-	Covered	T47,T39,T48
DetectSt	-	-	-	-	1	-	-	Covered	T107,T181
DetectSt	-	-	-	-	0	1	-	Covered	T47,T39,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T39,T186
StableSt	-	-	-	-	-	-	0	Covered	T47,T39,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	106	0	0
CntIncr_A	5916283	14237	0	0
CntNoWrap_A	5916283	5441369	0	0
DetectStDropOut_A	5916283	2	0	0
DetectedOut_A	5916283	10216	0	0
DetectedPulseOut_A	5916283	48	0	0
DisabledIdleSt_A	5916283	5398833	0	0
DisabledNoDetection_A	5916283	5400793	0	0
EnterDebounceSt_A	5916283	56	0	0
EnterDetectSt_A	5916283	50	0	0
EnterStableSt_A	5916283	48	0	0
PulseIsPulse_A	5916283	48	0	0
StayInStableSt	5916283	10146	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5916283	1652	0	0
gen_low_level_sva.LowLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	106	0	0
T39	0	4	0	0
T45	0	4	0	0
T47	2047	2	0	0
T48	0	2	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	4	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	3	0	0
T172	0	6	0	0
T186	0	2	0	0
T189	0	2	0	0
T190	0	2	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	14237	0	0
T39	0	192	0	0
T45	0	82	0	0
T47	2047	100	0	0
T48	0	96	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	22	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	100	0	0
T172	0	81	0	0
T186	0	14	0	0
T189	0	92	0	0
T190	0	21	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441369	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	2	0	0
T107	615	1	0	0
T128	18465	0	0	0
T181	0	1	0	0
T194	1039	0	0	0
T195	502	0	0	0
T196	543	0	0	0
T197	22267	0	0	0
T198	437	0	0	0
T199	570	0	0	0
T200	671	0	0	0
T201	478	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	10216	0	0
T39	0	244	0	0
T45	0	201	0	0
T47	2047	2	0	0
T48	0	214	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	74	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	95	0	0
T172	0	130	0	0
T186	0	1	0	0
T189	0	580	0	0
T190	0	18	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	48	0	0
T39	0	2	0	0
T45	0	2	0	0
T47	2047	1	0	0
T48	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	1	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	1	0	0
T172	0	3	0	0
T186	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5398833	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5400793	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	56	0	0
T39	0	2	0	0
T45	0	2	0	0
T47	2047	1	0	0
T48	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	2	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	2	0	0
T172	0	3	0	0
T186	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	50	0	0
T39	0	2	0	0
T45	0	2	0	0
T47	2047	1	0	0
T48	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	2	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	1	0	0
T172	0	3	0	0
T186	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	48	0	0
T39	0	2	0	0
T45	0	2	0	0
T47	2047	1	0	0
T48	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	1	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	1	0	0
T172	0	3	0	0
T186	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	48	0	0
T39	0	2	0	0
T45	0	2	0	0
T47	2047	1	0	0
T48	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	1	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	1	0	0
T172	0	3	0	0
T186	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	10146	0	0
T39	0	241	0	0
T45	0	198	0	0
T47	2047	1	0	0
T48	0	212	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	73	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	94	0	0
T172	0	126	0	0
T189	0	578	0	0
T190	0	17	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T202	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1652	0	0
T1	20180	0	0	0
T2	28487	0	0	0
T3	25937	0	0	0
T4	746	1	0	0
T5	423	2	0	0
T6	422	4	0	0
T7	17991	0	0	0
T8	0	2	0	0
T13	527	6	0	0
T14	489	6	0	0
T15	404	0	0	0
T25	0	6	0	0
T26	0	6	0	0
T78	0	4	0	0
T79	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	25	0	0
T39	0	1	0	0
T45	0	1	0	0
T47	2047	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T107	0	1	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T171	0	1	0	0
T172	0	2	0	0
T186	0	1	0	0
T190	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T203	0	1	0	0
T204	0	3	0	0