Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1784

1

T1

4

T2

14

T3

36

auto[1]

638

1

T1

4

T3

4

T7

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1835

1

T2

8

T3

30

T7

17

auto[1]

587

1

T1

8

T2

6

T3

10

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1921

1

T1

5

T2

6

T3

40

auto[1]

501

1

T1

3

T2

8

T7

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1900

1

T1

4

T2

14

T3

38

auto[1]

522

1

T1

4

T3

2

T7

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2185

1

T1

8

T2

14

T3

36

auto[1]

237

1

T3

4

T16

1

T93

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2262

1

T1

8

T2

14

T3

36

auto[1]

160

1

T3

4

T7

3

T35

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2167

1

T1

8

T2

14

T3

30

auto[1]

255

1

T3

10

T7

2

T51

17

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2203

1

T1

8

T2

14

T3

38

auto[1]

219

1

T3

2

T7

3

T16

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2285

1

T1

8

T2

14

T3

32

auto[1]

137

1

T3

8

T7

6

T94

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1844

1

T1

3

T2

8

T3

40

auto[1]

578

1

T1

5

T2

6

T16

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	787	1			T1	8		T2	14		T12	11
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	98	1			T97	13		T124	7		T253	11
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	29	1			T270	1		T251	5		T344	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T387	3		T388	3		T389	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	73	1			T16	1		T272	2		T197	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	28	1			T16	1		T339	15		T197	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T7	3		T390	1		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T3	2		T391	1		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	82	1			T3	8		T7	2		T51	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	24	1			T270	1		T392	4		T350	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T383	1		T393	7		T394	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T3	2		T96	1		T339	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	32	1			T51	4		T96	1		T272	2
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	10	1			T241	6		T395	4		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	30	1			T35	4		T51	3		T98	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	10	1			T93	1		T251	5		T275	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	19	1			T3	4		T7	3		T94	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	9	1			T97	2		T111	3		T396	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T251	5		T391	2		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	10	1			T276	1		T397	2		T398	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T399	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	32	1			T400	3		T109	8		T397	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	11	1			T339	6		T401	1		T402	1
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T97	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	8	1			T391	1		T384	7		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T339	6		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

153

1

T3

4

T7

2

T52

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

116

1

T372

9

T264

9

T269

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

80

1

T37

8

T51

4

T36

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

81

1

T3

2

T97

13

T270

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

71

1

T7

3

T53

6

T38

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T154

1

T280

6

T339

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T144

1

T373

2

T284

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T2

8

T251

5

T253

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

44

1

T35

4

T36

2

T282

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T51

3

T259

4

T251

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T97

2

T281

2

T305

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T12

2

T372

5

T305

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T263

5

T343

3

T285

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T36

4

T93

1

T98

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T37

4

T128

1

T217

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

113

1

T3

10

T16

1

T38

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

38

1

T53

6

T94

1

T343

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T1

4

T2

6

T305

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T16

1

T96

1

T283

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T39

3

T124

7

T264

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T54

5

T343

1

T344

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T403

1

T130

2

T404

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T1

1

T39

1

T259

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T12

6

T280

3

T161

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T7

3

T12

3

T270

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T39

3

T405

4

T127

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T373

1

T405

2

T217

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T263

5

T373

4

T251

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T1

3

T52

1

T281

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T372

2

T275

1

T400

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T282

1

T263

3

T343

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded