Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

695

1

T26

8

T66

10

T88

8

auto[1]

720

1

T26

12

T66

10

T88

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

342

1

T26

5

T66

7

T88

5

from_0to1

332

1

T26

4

T66

7

T88

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

689

1

T26

8

T66

12

T88

11

auto[1]

726

1

T26

12

T66

8

T88

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T26

10

T66

10

T88

9

auto[1]

708

1

T26

10

T66

10

T88

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T66

3

T90

3

T56

3

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T66

2

T88

1

T421

2

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T26

1

T90

1

T56

1

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T26

2

T421

1

T73

2

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T88

2

T90

1

T56

2

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T88

1

T90

2

T421

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T66

1

T56

1

T73

3

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T73

1

T74

1

T330

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T26

1

T88

2

T421

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T66

1

T88

1

T90

1

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T421

1

T73

2

T74

3

auto[1]

from_1to0

auto[1]

auto[1]

36

1

T26

1

T66

1

T88

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T26

1

T66

2

T88

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T26

1

T66

1

T88

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T26

1

T66

2

T421

2

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T26

1

T66

1

T90

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703

1

T26

10

T66

11

T88

12

auto[1]

712

1

T26

10

T66

9

T88

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

334

1

T26

3

T66

5

T88

3

from_0to1

336

1

T26

4

T66

4

T88

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

698

1

T26

12

T66

15

T88

10

auto[1]

717

1

T26

8

T66

5

T88

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

720

1

T26

10

T66

9

T88

8

auto[1]

695

1

T26

10

T66

11

T88

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T66

3

T90

1

T73

3

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T26

1

T66

1

T88

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T26

1

T66

1

T90

1

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T88

1

T73

1

T74

2

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T66

1

T421

1

T73

3

auto[0]

from_0to1

auto[0]

auto[1]

31

1

T88

1

T73

1

T330

1

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T66

1

T88

1

T421

2

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T26

1

T66

1

T421

1

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T26

1

T90

1

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T73

4

T330

2

T305

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T88

1

T56

2

T422

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T421

2

T73

1

T74

2

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T26

1

T88

1

T90

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T26

2

T90

1

T73

2

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T56

2

T305

1

T331

2

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T66

1

T90

2

T421

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T26

6

T66

9

T88

10

auto[1]

740

1

T26

14

T66

11

T88

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

342

1

T26

4

T66

3

T88

2

from_0to1

342

1

T26

4

T66

3

T88

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711

1

T26

14

T66

9

T88

12

auto[1]

704

1

T26

6

T66

11

T88

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

717

1

T26

12

T66

9

T88

14

auto[1]

698

1

T26

8

T66

11

T88

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T26

1

T88

1

T421

1

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T90

1

T56

1

T73

2

auto[0]

from_1to0

auto[1]

auto[0]

44

1

T73

1

T74

1

T330

2

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T26

1

T90

1

T74

2

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T88

1

T421

1

T74

3

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T66

1

T88

1

T90

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T26

1

T88

1

T90

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T66

1

T56

1

T73

1

auto[1]

from_1to0

auto[0]

auto[0]

44

1

T26

1

T66

1

T90

2

auto[1]

from_1to0

auto[0]

auto[1]

35

1

T26

1

T90

1

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T88

1

T73

1

T74

3

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T66

2

T421

1

T73

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T66

1

T90

1

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T26

2

T74

1

T422

2

auto[1]

from_0to1

auto[1]

auto[0]

48

1

T26

1

T56

2

T74

1

auto[1]

from_0to1

auto[1]

auto[1]

39

1

T90

1

T421

1

T56

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

681

1

T26

9

T66

10

T88

11

auto[1]

734

1

T26

11

T66

10

T88

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

328

1

T26

3

T66

5

T88

3

from_0to1

337

1

T26

4

T66

4

T88

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T26

12

T66

13

T88

11

auto[1]

708

1

T26

8

T66

7

T88

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

726

1

T26

14

T66

9

T88

10

auto[1]

689

1

T26

6

T66

11

T88

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T26

1

T421

1

T56

1

auto[0]

from_1to0

auto[0]

auto[1]

37

1

T66

1

T90

1

T56

1

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T26

1

T66

1

T421

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T421

1

T73

1

T74

1

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T26

1

T90

1

T330

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T66

1

T88

1

T90

2

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T88

1

T90

1

T421

2

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T66

2

T73

2

T330

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T66

2

T88

1

T90

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T88

1

T90

1

T74

2

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T26

1

T88

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

33

1

T66

1

T90

2

T73

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T26

1

T73

2

T74

2

auto[1]

from_0to1

auto[0]

auto[1]

27

1

T66

1

T88

1

T56

1

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T26

1

T88

1

T421

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T26

1

T421

1

T56

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

736

1

T26

7

T66

14

T88

10

auto[1]

679

1

T26

13

T66

6

T88

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

329

1

T26

3

T66

6

T88

6

from_0to1

327

1

T26

4

T66

5

T88

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

731

1

T26

10

T66

14

T88

10

auto[1]

684

1

T26

10

T66

6

T88

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

685

1

T26

10

T66

7

T88

6

auto[1]

730

1

T26

10

T66

13

T88

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T73

2

T74

1

T330

1

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T66

3

T88

1

T421

2

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T421

1

T73

2

T330

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T66

2

T88

3

T421

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T26

1

T66

1

T88

1

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T66

2

T421

2

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T90

1

T56

1

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T421

2

T73

2

T74

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T26

1

T66

1

T90

2

auto[1]

from_1to0

auto[0]

auto[1]

40

1

T90

1

T56

1

T73

5

auto[1]

from_1to0

auto[1]

auto[0]

40

1

T90

1

T421

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T26

2

T88

2

T90

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T26

1

T88

1

T56

2

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T66

1

T88

1

T90

2

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T26

1

T88

1

T90

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T26

1

T66

1

T88

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T26

14

T66

12

T88

12

auto[1]

708

1

T26

6

T66

8

T88

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

342

1

T26

5

T66

4

T88

6

from_0to1

340

1

T26

5

T66

4

T88

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

716

1

T26

7

T66

8

T88

7

auto[1]

699

1

T26

13

T66

12

T88

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710

1

T26

9

T66

9

T88

11

auto[1]

705

1

T26

11

T66

11

T88

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T26

1

T421

1

T73

3

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T66

1

T421

1

T73

1

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T26

2

T88

1

T90

2

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T26

2

T88

1

T421

1

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T66

1

T88

1

T73

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T26

2

T66

1

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T26

1

T88

2

T90

1

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T90

3

T421

1

T56

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T88

1

T421

1

T56

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T66

1

T421

1

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T66

1

T88

3

T90

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T66

1

T90

2

T73

3

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T66

1

T421

2

T56

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T88

1

T421

1

T56

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T26

1

T66

1

T88

1

auto[1]

from_0to1

auto[1]

auto[1]

28

1

T26

1

T88

1

T90

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703

1

T26

10

T66

12

T88

13

auto[1]

712

1

T26

10

T66

8

T88

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

337

1

T26

6

T66

4

T88

5

from_0to1

346

1

T26

7

T66

5

T88

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T26

9

T66

5

T88

9

auto[1]

737

1

T26

11

T66

15

T88

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704

1

T26

6

T66

11

T88

11

auto[1]

711

1

T26

14

T66

9

T88

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T88

2

T90

1

T73

1

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T26

3

T66

2

T90

2

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T66

1

T73

2

T74

2

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T26

1

T421

2

T56

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T66

1

T73

2

T74

3

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T26

1

T66

1

T88

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T26

1

T66

1

T88

2

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T88

1

T56

2

T73

1

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T56

1

T73

2

T422

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T88

2

T90

1

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T26

1

T88

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T26

1

T66

1

T421

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T26

1

T90

1

T421

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T73

1

T330

2

T331

3

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T26

1

T66

2

T90

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T26

3

T88

1

T90

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

752

1

T26

9

T66

13

T88

9

auto[1]

663

1

T26

11

T66

7

T88

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

341

1

T26

7

T66

5

T88

5

from_0to1

345

1

T26

6

T66

5

T88

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

701

1

T26

6

T66

9

T88

12

auto[1]

714

1

T26

14

T66

11

T88

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

720

1

T26

13

T66

13

T88

10

auto[1]

695

1

T26

7

T66

7

T88

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T88

1

T90

2

T73

3

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T88

1

T56

2

T73

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T26

2

T66

2

T88

1

auto[0]

from_1to0

auto[1]

auto[1]

45

1

T66

1

T56

1

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

36

1

T66

1

T90

1

T422

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T26

1

T66

1

T88

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T26

1

T66

1

T88

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T26

1

T88

1

T90

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T26

1

T88

1

T73

2

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T88

1

T90

1

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T26

3

T73

1

T422

1

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T26

1

T66

2

T90

1

auto[1]

from_0to1

auto[0]

auto[0]

43

1

T66

2

T88

1

T90

1

auto[1]

from_0to1

auto[0]

auto[1]

30

1

T26

1

T88

1

T74

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T26

2

T90

2

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T56

1

T73

1

T74

1