Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116622

1

T5

1

T6

2

T1

254

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138213	1			T5	2		T6	2		T1	392
values[0x0]	63934	1			T6	1		T1	61		T2	109
values[0x1]	64445	1			T1	62		T2	111		T3	408

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145469

1

T5

1

T6

2

T1

312

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	799	1			T1	8		T3	2		T7	3
valid_sources[0x01]	894	1			T3	5		T7	3		T16	1
valid_sources[0x02]	930	1			T1	1		T3	6		T7	7
valid_sources[0x03]	798	1			T1	4		T3	2		T7	3
valid_sources[0x04]	1040	1			T1	1		T3	4		T7	4
valid_sources[0x05]	1464	1			T3	1		T7	1		T52	2
valid_sources[0x06]	813	1			T1	3		T3	5		T7	5
valid_sources[0x07]	927	1			T1	3		T3	4		T7	1
valid_sources[0x08]	1712	1			T3	3		T16	4		T79	1
valid_sources[0x09]	980	1			T1	4		T3	1		T16	2
valid_sources[0x0a]	935	1			T1	2		T3	3		T27	1
valid_sources[0x0b]	1769	1			T1	2		T3	2		T26	2
valid_sources[0x0c]	903	1			T5	1		T1	2		T3	4
valid_sources[0x0d]	764	1			T1	1		T3	13		T16	4
valid_sources[0x0e]	838	1			T1	4		T3	3		T4	2
valid_sources[0x0f]	830	1			T1	4		T3	2		T7	3
valid_sources[0x10]	954	1			T3	1		T7	7		T16	5
valid_sources[0x11]	763	1			T3	11		T7	7		T16	1
valid_sources[0x12]	957	1			T3	2		T13	2		T16	3
valid_sources[0x13]	1196	1			T1	1		T3	3		T16	3
valid_sources[0x14]	1047	1			T1	2		T3	4		T7	1
valid_sources[0x15]	878	1			T1	1		T3	6		T16	6
valid_sources[0x16]	1052	1			T3	12		T7	4		T16	1
valid_sources[0x17]	1023	1			T1	2		T3	8		T16	4
valid_sources[0x18]	1071	1			T3	1		T7	1		T16	6
valid_sources[0x19]	828	1			T1	4		T3	4		T7	6
valid_sources[0x1a]	959	1			T3	3		T7	2		T4	3
valid_sources[0x1b]	2671	1			T1	1		T3	6		T7	1
valid_sources[0x1c]	810	1			T1	6		T3	2		T7	2
valid_sources[0x1d]	962	1			T1	3		T3	3		T16	5
valid_sources[0x1e]	1080	1			T3	3		T7	7		T16	3
valid_sources[0x1f]	901	1			T1	5		T7	4		T16	3
valid_sources[0x20]	826	1			T3	5		T7	2		T16	5
valid_sources[0x21]	1329	1			T1	1		T3	2		T7	8
valid_sources[0x22]	890	1			T1	6		T3	9		T7	5
valid_sources[0x23]	976	1			T1	2		T3	8		T16	4
valid_sources[0x24]	1233	1			T1	5		T3	3		T7	7
valid_sources[0x25]	1246	1			T1	10		T3	3		T79	3
valid_sources[0x26]	1896	1			T1	5		T3	5		T7	6
valid_sources[0x27]	912	1			T1	1		T3	1		T7	1
valid_sources[0x28]	1099	1			T3	2		T4	1		T16	1
valid_sources[0x29]	1098	1			T1	1		T3	9		T7	1
valid_sources[0x2a]	973	1			T3	4		T4	1		T16	6
valid_sources[0x2b]	955	1			T1	7		T3	3		T13	1
valid_sources[0x2c]	957	1			T1	1		T3	1		T7	13
valid_sources[0x2d]	984	1			T1	1		T3	9		T7	2
valid_sources[0x2e]	771	1			T1	7		T3	7		T7	1
valid_sources[0x2f]	859	1			T1	3		T3	4		T16	1
valid_sources[0x30]	1086	1			T1	3		T3	7		T7	9
valid_sources[0x31]	772	1			T3	3		T7	13		T16	4
valid_sources[0x32]	908	1			T1	4		T3	2		T13	3
valid_sources[0x33]	955	1			T1	1		T3	7		T7	10
valid_sources[0x34]	809	1			T3	4		T7	4		T52	2
valid_sources[0x35]	833	1			T3	4		T7	14		T12	2
valid_sources[0x36]	874	1			T1	2		T3	4		T7	4
valid_sources[0x37]	895	1			T1	1		T3	4		T7	10
valid_sources[0x38]	722	1			T1	1		T3	6		T16	1
valid_sources[0x39]	744	1			T4	2		T16	5		T26	1
valid_sources[0x3a]	827	1			T3	5		T7	1		T4	2
valid_sources[0x3b]	1150	1			T1	1		T3	1		T16	8
valid_sources[0x3c]	813	1			T3	6		T7	9		T16	3
valid_sources[0x3d]	1018	1			T1	2		T3	8		T16	4
valid_sources[0x3e]	806	1			T3	10		T7	2		T16	6
valid_sources[0x3f]	945	1			T1	14		T3	8		T16	4
valid_sources[0x40]	1014	1			T1	3		T3	5		T13	2
valid_sources[0x41]	956	1			T1	3		T3	4		T12	1
valid_sources[0x42]	956	1			T1	8		T3	12		T7	3
valid_sources[0x43]	728	1			T1	2		T3	6		T7	3
valid_sources[0x44]	837	1			T1	2		T3	2		T7	20
valid_sources[0x45]	942	1			T3	6		T7	11		T16	2
valid_sources[0x46]	883	1			T3	9		T7	2		T16	5
valid_sources[0x47]	932	1			T1	3		T3	8		T16	5
valid_sources[0x48]	1049	1			T1	1		T3	11		T7	4
valid_sources[0x49]	837	1			T3	5		T7	6		T13	2
valid_sources[0x4a]	715	1			T1	2		T3	1		T7	1
valid_sources[0x4b]	914	1			T1	5		T3	1		T16	8
valid_sources[0x4c]	1005	1			T1	15		T3	12		T7	1
valid_sources[0x4d]	829	1			T3	2		T4	1		T16	11
valid_sources[0x4e]	824	1			T1	4		T3	6		T7	1
valid_sources[0x4f]	1178	1			T1	1		T3	7		T16	2
valid_sources[0x50]	1011	1			T3	8		T7	10		T16	7
valid_sources[0x51]	795	1			T1	8		T3	7		T16	4
valid_sources[0x52]	968	1			T1	1		T3	3		T7	1
valid_sources[0x53]	1063	1			T1	3		T3	6		T7	8
valid_sources[0x54]	2619	1			T1	4		T3	9		T7	3
valid_sources[0x55]	1008	1			T1	2		T3	4		T7	4
valid_sources[0x56]	1131	1			T3	1		T7	10		T16	2
valid_sources[0x57]	890	1			T3	11		T7	7		T16	2
valid_sources[0x58]	841	1			T1	3		T3	4		T7	9
valid_sources[0x59]	861	1			T3	7		T7	20		T52	1
valid_sources[0x5a]	990	1			T1	2		T3	3		T7	1
valid_sources[0x5b]	967	1			T1	1		T3	9		T7	1
valid_sources[0x5c]	917	1			T1	4		T3	11		T7	12
valid_sources[0x5d]	888	1			T1	6		T3	6		T13	1
valid_sources[0x5e]	923	1			T1	1		T3	11		T13	4
valid_sources[0x5f]	1145	1			T1	2		T3	8		T7	4
valid_sources[0x60]	849	1			T1	3		T3	4		T7	3
valid_sources[0x61]	902	1			T6	1		T3	7		T16	11
valid_sources[0x62]	1895	1			T1	1		T3	3		T7	3
valid_sources[0x63]	1956	1			T1	8		T3	9		T7	3
valid_sources[0x64]	805	1			T1	3		T3	10		T16	2
valid_sources[0x65]	732	1			T3	5		T13	2		T16	2
valid_sources[0x66]	887	1			T1	4		T3	1		T7	2
valid_sources[0x67]	814	1			T1	5		T3	2		T16	8
valid_sources[0x68]	1140	1			T3	3		T7	1		T16	2
valid_sources[0x69]	747	1			T1	6		T3	7		T7	9
valid_sources[0x6a]	1857	1			T6	1		T1	5		T3	2
valid_sources[0x6b]	940	1			T1	4		T3	1		T16	1
valid_sources[0x6c]	1766	1			T1	9		T3	4		T7	4
valid_sources[0x6d]	2240	1			T3	7		T7	1		T12	1
valid_sources[0x6e]	904	1			T3	5		T7	4		T16	2
valid_sources[0x6f]	858	1			T3	2		T7	22		T16	4
valid_sources[0x70]	1811	1			T1	2		T3	2		T7	5
valid_sources[0x71]	927	1			T1	2		T3	1		T7	3
valid_sources[0x72]	782	1			T1	1		T3	7		T7	1
valid_sources[0x73]	2048	1			T1	1		T3	14		T16	7
valid_sources[0x74]	938	1			T1	1		T3	2		T7	1
valid_sources[0x75]	822	1			T1	11		T3	4		T16	4
valid_sources[0x76]	877	1			T1	2		T3	1		T7	6
valid_sources[0x77]	871	1			T1	3		T3	1		T7	9
valid_sources[0x78]	830	1			T16	2		T12	4		T53	2
valid_sources[0x79]	815	1			T3	7		T16	3		T26	1
valid_sources[0x7a]	742	1			T3	3		T7	2		T26	1
valid_sources[0x7b]	2181	1			T1	2		T3	9		T16	5
valid_sources[0x7c]	1898	1			T1	3		T3	1		T7	5
valid_sources[0x7d]	987	1			T3	3		T7	7		T16	1
valid_sources[0x7e]	770	1			T1	1		T3	7		T7	5
valid_sources[0x7f]	872	1			T1	3		T3	2		T16	3
valid_sources[0x80]	907	1			T1	1		T3	3		T16	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62179

1

T5

1

T6

2

T1

198

values[0x0]

all_enables

biggest_size

31726

1

T1

32

T2

56

T3

181

values[0x1]

all_enables

biggest_size

22717

1

T1

24

T2

47

T3

121