Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T10,T42,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T10,T42,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T10,T42,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T42,T49
1	0	Covered	T5,T6,T1
1	1	Covered	T10,T42,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T42,T49
0	1	Covered	T44,T256,T258
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T42,T49
0	1	Covered	T42,T39,T46
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T42,T49
1	-	Covered	T42,T39,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T42,T49
DetectSt	168	Covered	T10,T42,T49
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T10,T42,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T42,T49
DebounceSt->IdleSt	163	Covered	T171,T237,T105
DetectSt->IdleSt	186	Covered	T44,T256,T258
DetectSt->StableSt	191	Covered	T10,T42,T49
IdleSt->DebounceSt	148	Covered	T10,T42,T49
StableSt->IdleSt	206	Covered	T42,T39,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T42,T49
0	1	Covered	T10,T42,T49
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T42,T49
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T42,T49
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T42,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T171,T237,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T42,T49
DetectSt	-	-	-	-	1	-	-	Covered	T44,T256,T258
DetectSt	-	-	-	-	0	1	-	Covered	T10,T42,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T39,T46
StableSt	-	-	-	-	-	-	0	Covered	T10,T42,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	106	0	0
CntIncr_A	5916283	14207	0	0
CntNoWrap_A	5916283	5441369	0	0
DetectStDropOut_A	5916283	3	0	0
DetectedOut_A	5916283	11062	0	0
DetectedPulseOut_A	5916283	48	0	0
DisabledIdleSt_A	5916283	5398072	0	0
DisabledNoDetection_A	5916283	5400027	0	0
EnterDebounceSt_A	5916283	55	0	0
EnterDetectSt_A	5916283	51	0	0
EnterStableSt_A	5916283	48	0	0
PulseIsPulse_A	5916283	48	0	0
StayInStableSt	5916283	10989	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	106	0	0
T10	642	2	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	4	0	0
T42	0	4	0	0
T44	0	2	0	0
T46	0	4	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	2	0	0
T216	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	14207	0	0
T10	642	88	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	192	0	0
T42	0	124	0	0
T44	0	45	0	0
T46	0	140	0	0
T48	0	96	0	0
T49	0	45	0	0
T50	0	92	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	14	0	0
T216	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441369	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3	0	0
T44	543	1	0	0
T61	61537	0	0	0
T124	22072	0	0	0
T167	585	0	0	0
T256	0	1	0	0
T258	0	1	0	0
T259	38552	0	0	0
T260	421	0	0	0
T261	434	0	0	0
T262	872	0	0	0
T263	19984	0	0	0
T264	23577	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	11062	0	0
T10	642	145	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	97	0	0
T42	0	205	0	0
T46	0	355	0	0
T48	0	214	0	0
T49	0	89	0	0
T50	0	149	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	41	0	0
T205	0	14	0	0
T216	0	150	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	48	0	0
T10	642	1	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	1	0	0
T205	0	1	0	0
T216	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5398072	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5400027	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	55	0	0
T10	642	1	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	1	0	0
T216	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	51	0	0
T10	642	1	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	1	0	0
T216	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	48	0	0
T10	642	1	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	1	0	0
T205	0	1	0	0
T216	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	48	0	0
T10	642	1	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	2	0	0
T42	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	1	0	0
T205	0	1	0	0
T216	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	10989	0	0
T10	642	143	0	0
T11	506	0	0	0
T12	21456	0	0	0
T27	579	0	0	0
T39	0	94	0	0
T42	0	203	0	0
T46	0	352	0	0
T48	0	212	0	0
T49	0	87	0	0
T50	0	147	0	0
T63	8402	0	0	0
T64	674	0	0	0
T70	908	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T79	453	0	0	0
T186	0	39	0	0
T205	0	13	0	0
T216	0	148	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	22	0	0
T35	18631	0	0	0
T38	37173	0	0	0
T39	0	1	0	0
T42	968	2	0	0
T46	0	1	0	0
T54	15540	0	0	0
T80	500	0	0	0
T87	533	0	0	0
T88	502	0	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	1	0	0
T189	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T209	871	0	0	0
T210	402	0	0	0
T211	402	0	0	0
T256	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T43,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T4,T43,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T43,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Covered	T5,T6,T1
1	1	Covered	T4,T43,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T43,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T43,T39
0	1	Covered	T4,T39,T46
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T43,T39
1	-	Covered	T4,T39,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T43,T39
DetectSt	168	Covered	T4,T43,T39
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T4,T43,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T43,T39
DebounceSt->IdleSt	163	Covered	T40,T105,T213
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T43,T39
IdleSt->DebounceSt	148	Covered	T4,T43,T39
StableSt->IdleSt	206	Covered	T4,T43,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T43,T39
0	1	Covered	T4,T43,T39
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T43,T39
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T43,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T43,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T213
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T43,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T43,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T39,T46
StableSt	-	-	-	-	-	-	0	Covered	T4,T43,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	49	0	0
CntIncr_A	5916283	6978	0	0
CntNoWrap_A	5916283	5441426	0	0
DetectStDropOut_A	5916283	0	0	0
DetectedOut_A	5916283	7465	0	0
DetectedPulseOut_A	5916283	23	0	0
DisabledIdleSt_A	5916283	5271292	0	0
DisabledNoDetection_A	5916283	5273247	0	0
EnterDebounceSt_A	5916283	26	0	0
EnterDetectSt_A	5916283	23	0	0
EnterStableSt_A	5916283	23	0	0
PulseIsPulse_A	5916283	23	0	0
StayInStableSt	5916283	7431	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5916283	5212	0	0
gen_low_level_sva.LowLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	49	0	0
T4	746	2	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T46	0	2	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	4	0	0
T172	0	4	0	0
T189	0	2	0	0
T205	0	2	0	0
T237	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	6978	0	0
T4	746	32	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	96	0	0
T40	0	81	0	0
T43	0	52	0	0
T46	0	70	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	100	0	0
T172	0	54	0	0
T189	0	92	0	0
T205	0	44	0	0
T237	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441426	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	343	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	7465	0	0
T4	746	85	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	326	0	0
T43	0	41	0	0
T46	0	47	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	83	0	0
T172	0	87	0	0
T189	0	222	0	0
T203	0	44	0	0
T205	0	39	0	0
T237	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	23	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	2	0	0
T172	0	2	0	0
T189	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T237	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5271292	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	3	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5273247	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	3	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	26	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	2	0	0
T172	0	2	0	0
T189	0	1	0	0
T205	0	1	0	0
T237	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	23	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	2	0	0
T172	0	2	0	0
T189	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T237	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	23	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	2	0	0
T172	0	2	0	0
T189	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T237	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	23	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	2	0	0
T172	0	2	0	0
T189	0	1	0	0
T203	0	1	0	0
T205	0	1	0	0
T237	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	7431	0	0
T4	746	84	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	325	0	0
T43	0	39	0	0
T46	0	46	0	0
T62	405	0	0	0
T68	653	0	0	0
T171	0	80	0	0
T172	0	84	0	0
T189	0	220	0	0
T203	0	43	0	0
T205	0	37	0	0
T237	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5212	0	0
T1	20180	11	0	0
T2	28487	12	0	0
T3	25937	33	0	0
T4	746	1	0	0
T5	423	3	0	0
T6	422	3	0	0
T7	17991	28	0	0
T13	527	3	0	0
T14	489	6	0	0
T15	404	0	0	0
T16	0	33	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	11	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T46	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T169	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T188	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T47,T46,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T47,T46,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T47,T46,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T47,T46
1	0	Covered	T5,T6,T1
1	1	Covered	T47,T46,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T46,T48
0	1	Covered	T44,T45
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T46,T48
0	1	Covered	T167,T45,T172
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T46,T48
1	-	Covered	T167,T45,T172

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T47,T46,T48
DetectSt	168	Covered	T47,T46,T48
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T47,T46,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T46,T48
DebounceSt->IdleSt	163	Covered	T167,T237,T173
DetectSt->IdleSt	186	Covered	T44,T45
DetectSt->StableSt	191	Covered	T47,T46,T48
IdleSt->DebounceSt	148	Covered	T47,T46,T48
StableSt->IdleSt	206	Covered	T47,T167,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T47,T46,T48
0	1	Covered	T47,T46,T48
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T47,T46,T48
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T47,T46,T48
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T46,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T237,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T47,T46,T48
DetectSt	-	-	-	-	1	-	-	Covered	T44,T45
DetectSt	-	-	-	-	0	1	-	Covered	T47,T46,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T167,T45,T172
StableSt	-	-	-	-	-	-	0	Covered	T47,T46,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	85	0	0
CntIncr_A	5916283	2324	0	0
CntNoWrap_A	5916283	5441390	0	0
DetectStDropOut_A	5916283	3	0	0
DetectedOut_A	5916283	2475	0	0
DetectedPulseOut_A	5916283	37	0	0
DisabledIdleSt_A	5916283	5430664	0	0
DisabledNoDetection_A	5916283	5432627	0	0
EnterDebounceSt_A	5916283	45	0	0
EnterDetectSt_A	5916283	40	0	0
EnterStableSt_A	5916283	37	0	0
PulseIsPulse_A	5916283	37	0	0
StayInStableSt	5916283	2424	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	85	0	0
T44	0	2	0	0
T45	0	6	0	0
T46	0	2	0	0
T47	2047	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	3	0	0
T172	0	2	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	2	0	0
T206	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	2324	0	0
T44	0	45	0	0
T45	0	123	0	0
T46	0	70	0	0
T47	2047	100	0	0
T48	0	96	0	0
T50	0	92	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	44	0	0
T172	0	27	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	44	0	0
T206	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441390	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3	0	0
T44	543	1	0	0
T45	0	2	0	0
T61	61537	0	0	0
T124	22072	0	0	0
T167	585	0	0	0
T259	38552	0	0	0
T260	421	0	0	0
T261	434	0	0	0
T262	872	0	0	0
T263	19984	0	0	0
T264	23577	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	2475	0	0
T45	0	30	0	0
T46	0	42	0	0
T47	2047	43	0	0
T48	0	43	0	0
T50	0	148	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	7	0	0
T172	0	27	0	0
T189	0	270	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	98	0	0
T206	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	37	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	2047	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	1	0	0
T172	0	1	0	0
T189	0	2	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	1	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5430664	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5432627	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	45	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	2047	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	2	0	0
T172	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	1	0	0
T206	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	40	0	0
T44	0	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	2047	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	1	0	0
T172	0	1	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	1	0	0
T206	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	37	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	2047	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	1	0	0
T172	0	1	0	0
T189	0	2	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	1	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	37	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	2047	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	1	0	0
T172	0	1	0	0
T189	0	2	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	1	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	2424	0	0
T45	0	29	0	0
T46	0	40	0	0
T47	2047	41	0	0
T48	0	41	0	0
T50	0	146	0	0
T55	744	0	0	0
T92	512	0	0	0
T98	9028	0	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T167	0	6	0	0
T172	0	26	0	0
T189	0	267	0	0
T191	738	0	0	0
T192	1513	0	0	0
T193	1354	0	0	0
T205	0	96	0	0
T206	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	22	0	0
T45	0	1	0	0
T124	22072	0	0	0
T167	585	1	0	0
T172	0	1	0	0
T173	0	2	0	0
T189	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0
T256	0	2	0	0
T260	421	0	0	0
T261	434	0	0	0
T262	872	0	0	0
T263	19984	0	0	0
T264	23577	0	0	0
T265	492	0	0	0
T266	526	0	0	0
T267	97812	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T8,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T41,T42
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T41,T42
0	1	Covered	T39,T167,T189
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T41,T42
1	-	Covered	T39,T167,T189

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T41,T42
DetectSt	168	Covered	T8,T41,T42
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T8,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T41,T42
DebounceSt->IdleSt	163	Covered	T105,T185
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T41,T42
IdleSt->DebounceSt	148	Covered	T8,T41,T42
StableSt->IdleSt	206	Covered	T39,T167,T189

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T41,T42
0	1	Covered	T8,T41,T42
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T41,T42
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T185
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T167,T189
StableSt	-	-	-	-	-	-	0	Covered	T8,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	56	0	0
CntIncr_A	5916283	34948	0	0
CntNoWrap_A	5916283	5441419	0	0
DetectStDropOut_A	5916283	0	0	0
DetectedOut_A	5916283	19799	0	0
DetectedPulseOut_A	5916283	27	0	0
DisabledIdleSt_A	5916283	5273625	0	0
DisabledNoDetection_A	5916283	5275591	0	0
EnterDebounceSt_A	5916283	29	0	0
EnterDetectSt_A	5916283	27	0	0
EnterStableSt_A	5916283	27	0	0
PulseIsPulse_A	5916283	27	0	0
StayInStableSt	5916283	19757	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5916283	5260	0	0
gen_low_level_sva.LowLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	56	0	0
T8	612	2	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T49	0	2	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	4	0	0
T172	0	2	0	0
T173	0	6	0	0
T189	0	2	0	0
T216	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	34948	0	0
T8	612	27	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	96	0	0
T41	0	16	0	0
T42	0	62	0	0
T49	0	45	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	44	0	0
T172	0	27	0	0
T173	0	210	0	0
T189	0	92	0	0
T216	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441419	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	19799	0	0
T8	612	76	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	137	0	0
T41	0	41	0	0
T42	0	229	0	0
T49	0	44	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	86	0	0
T172	0	285	0	0
T173	0	125	0	0
T189	0	217	0	0
T216	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	27	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T189	0	1	0	0
T216	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5273625	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5275591	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	29	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T189	0	1	0	0
T216	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	27	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T189	0	1	0	0
T216	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	27	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T189	0	1	0	0
T216	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	27	0	0
T8	612	1	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T49	0	1	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	2	0	0
T172	0	1	0	0
T173	0	3	0	0
T189	0	1	0	0
T216	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	19757	0	0
T8	612	74	0	0
T9	1451	0	0	0
T10	642	0	0	0
T11	506	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T39	0	136	0	0
T41	0	39	0	0
T42	0	227	0	0
T49	0	42	0	0
T69	612	0	0	0
T76	404	0	0	0
T77	410	0	0	0
T78	522	0	0	0
T167	0	83	0	0
T172	0	283	0	0
T173	0	121	0	0
T189	0	216	0	0
T216	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5260	0	0
T1	20180	11	0	0
T2	28487	11	0	0
T3	25937	32	0	0
T4	746	1	0	0
T5	423	1	0	0
T6	422	3	0	0
T7	17991	20	0	0
T13	527	4	0	0
T14	489	6	0	0
T15	404	0	0	0
T16	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	11	0	0
T39	22265	1	0	0
T71	2083	0	0	0
T90	506	0	0	0
T91	526	0	0	0
T120	5519	0	0	0
T167	0	1	0	0
T173	0	2	0	0
T174	0	1	0	0
T189	0	1	0	0
T204	0	1	0	0
T208	0	1	0	0
T225	425	0	0	0
T226	422	0	0	0
T228	0	1	0	0
T230	0	1	0	0
T231	0	1	0	0
T233	402	0	0	0
T234	404	0	0	0
T235	523	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T11,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T4,T11,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T11,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T41
1	0	Covered	T5,T6,T1
1	1	Covered	T4,T11,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T41
0	1	Covered	T39,T230
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T41
0	1	Covered	T4,T41,T42
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T41
1	-	Covered	T4,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T41
DetectSt	168	Covered	T4,T11,T41
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T4,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T41
DebounceSt->IdleSt	163	Covered	T92,T105,T177
DetectSt->IdleSt	186	Covered	T39,T230
DetectSt->StableSt	191	Covered	T4,T11,T41
IdleSt->DebounceSt	148	Covered	T4,T11,T41
StableSt->IdleSt	206	Covered	T4,T41,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T41
0	1	Covered	T4,T11,T41
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T41
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T41
DetectSt	-	-	-	-	1	-	-	Covered	T39,T230
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	109	0	0
CntIncr_A	5916283	14263	0	0
CntNoWrap_A	5916283	5441366	0	0
DetectStDropOut_A	5916283	2	0	0
DetectedOut_A	5916283	3545	0	0
DetectedPulseOut_A	5916283	51	0	0
DisabledIdleSt_A	5916283	5397179	0	0
DisabledNoDetection_A	5916283	5399133	0	0
EnterDebounceSt_A	5916283	56	0	0
EnterDetectSt_A	5916283	53	0	0
EnterStableSt_A	5916283	51	0	0
PulseIsPulse_A	5916283	51	0	0
StayInStableSt	5916283	3474	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	109	0	0
T4	746	6	0	0
T8	612	0	0	0
T11	0	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	6	0	0
T42	0	4	0	0
T43	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T62	405	0	0	0
T68	653	0	0	0
T92	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	14263	0	0
T4	746	96	0	0
T8	612	0	0	0
T11	0	25	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	96	0	0
T40	0	81	0	0
T41	0	48	0	0
T42	0	124	0	0
T43	0	52	0	0
T47	0	100	0	0
T48	0	96	0	0
T62	405	0	0	0
T68	653	0	0	0
T92	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441366	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	339	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	2	0	0
T39	22265	1	0	0
T71	2083	0	0	0
T90	506	0	0	0
T91	526	0	0	0
T120	5519	0	0	0
T225	425	0	0	0
T226	422	0	0	0
T230	0	1	0	0
T233	402	0	0	0
T234	404	0	0	0
T235	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3545	0	0
T4	746	133	0	0
T8	612	0	0	0
T11	0	71	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T40	0	53	0	0
T41	0	76	0	0
T42	0	325	0	0
T43	0	32	0	0
T44	0	89	0	0
T47	0	145	0	0
T48	0	43	0	0
T62	405	0	0	0
T68	653	0	0	0
T186	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	51	0	0
T4	746	3	0	0
T8	612	0	0	0
T11	0	1	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T186	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5397179	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	3	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5399133	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	3	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	56	0	0
T4	746	3	0	0
T8	612	0	0	0
T11	0	1	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T92	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	53	0	0
T4	746	3	0	0
T8	612	0	0	0
T11	0	1	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	51	0	0
T4	746	3	0	0
T8	612	0	0	0
T11	0	1	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T186	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	51	0	0
T4	746	3	0	0
T8	612	0	0	0
T11	0	1	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T186	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3474	0	0
T4	746	129	0	0
T8	612	0	0	0
T11	0	69	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T40	0	52	0	0
T41	0	72	0	0
T42	0	322	0	0
T43	0	31	0	0
T44	0	87	0	0
T47	0	143	0	0
T48	0	41	0	0
T62	405	0	0	0
T68	653	0	0	0
T216	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	30	0	0
T4	746	2	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T172	0	2	0	0
T186	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T216	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T4,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T4,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T47,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T4,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T40
0	1	Covered	T4
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T39,T40
0	1	Covered	T4,T172,T173
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T39,T40
1	-	Covered	T4,T172,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T39,T40
DetectSt	168	Covered	T4,T39,T40
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T4,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T39,T40
DebounceSt->IdleSt	163	Covered	T105,T168
DetectSt->IdleSt	186	Covered	T4
DetectSt->StableSt	191	Covered	T4,T39,T40
IdleSt->DebounceSt	148	Covered	T4,T39,T40
StableSt->IdleSt	206	Covered	T4,T172,T189

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T39,T40
0	1	Covered	T4,T39,T40
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T39,T40
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T168
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T4
DetectSt	-	-	-	-	0	1	-	Covered	T4,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T172,T173
StableSt	-	-	-	-	-	-	0	Covered	T4,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	56	0	0
CntIncr_A	5916283	12855	0	0
CntNoWrap_A	5916283	5441419	0	0
DetectStDropOut_A	5916283	1	0	0
DetectedOut_A	5916283	8351	0	0
DetectedPulseOut_A	5916283	26	0	0
DisabledIdleSt_A	5916283	5400184	0	0
DisabledNoDetection_A	5916283	5402149	0	0
EnterDebounceSt_A	5916283	29	0	0
EnterDetectSt_A	5916283	27	0	0
EnterStableSt_A	5916283	26	0	0
PulseIsPulse_A	5916283	26	0	0
StayInStableSt	5916283	8311	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5916283	5741	0	0
gen_low_level_sva.LowLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	56	0	0
T4	746	4	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	2	0	0
T172	0	4	0	0
T173	0	4	0	0
T189	0	2	0	0
T203	0	4	0	0
T204	0	2	0	0
T206	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	12855	0	0
T4	746	64	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	96	0	0
T40	0	81	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	22	0	0
T172	0	54	0	0
T173	0	140	0	0
T189	0	92	0	0
T203	0	66	0	0
T204	0	100	0	0
T206	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5441419	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	341	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T62	405	0	0	0
T68	653	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	8351	0	0
T4	746	40	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	616	0	0
T40	0	39	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	41	0	0
T172	0	88	0	0
T173	0	164	0	0
T189	0	221	0	0
T203	0	91	0	0
T204	0	51	0	0
T206	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	26	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	1	0	0
T172	0	2	0	0
T173	0	2	0	0
T189	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T206	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5400184	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25518	0	0
T4	746	3	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5402149	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	3	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	29	0	0
T4	746	2	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	1	0	0
T172	0	2	0	0
T173	0	2	0	0
T189	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T206	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	27	0	0
T4	746	2	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	1	0	0
T172	0	2	0	0
T173	0	2	0	0
T189	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T206	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	26	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	1	0	0
T172	0	2	0	0
T173	0	2	0	0
T189	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T206	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	26	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	1	0	0
T172	0	2	0	0
T173	0	2	0	0
T189	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T206	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	8311	0	0
T4	746	39	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T39	0	614	0	0
T40	0	37	0	0
T62	405	0	0	0
T68	653	0	0	0
T167	0	39	0	0
T172	0	85	0	0
T173	0	161	0	0
T189	0	219	0	0
T203	0	88	0	0
T204	0	50	0	0
T206	0	63	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5741	0	0
T1	20180	11	0	0
T2	28487	14	0	0
T3	25937	31	0	0
T4	746	2	0	0
T5	423	4	0	0
T6	422	3	0	0
T7	17991	32	0	0
T13	527	5	0	0
T14	489	5	0	0
T15	404	0	0	0
T16	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	11	0	0
T4	746	1	0	0
T8	612	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T25	526	0	0	0
T62	405	0	0	0
T68	653	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T208	0	1	0	0
T230	0	1	0	0
T257	0	1	0	0